Add support for MSI in interrupt controlller.
MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
This commit is contained in:
Grzegorz Bernacki
parent
373bc54ab1
commit
aa0ea9d07a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=240492
@ -55,7 +55,12 @@
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#elif defined(CPU_ARM11)
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#define NIRQ 128
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#elif defined(SOC_MV_ARMADAXP)
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#define NIRQ 148
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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#define ERR_IRQ (MAIN_IRQ_NUM)
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#define MSI_IRQ_NUM 32
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#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
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#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
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#else
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#define NIRQ 32
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#endif
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@ -1,6 +1,7 @@
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/*-
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* Copyright (c) 2006 Benno Rice.
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* Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
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* Copyright (c) 2012 Semihalf.
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* All rights reserved.
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*
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* Developed by Semihalf.
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@ -46,23 +47,34 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpufunc.h>
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#include <machine/smp.h>
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#include <arm/mv/mvvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_common.h>
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#define IRQ_ERR 4
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#define MAIN_IRQS 116
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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#define MPIC_INT_ERR 4
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#define MPIC_INT_MSI 96
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#define IRQ_MASK 0x3ff
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#define MPIC_CTRL 0x0
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#define MPIC_SOFT_INT 0x4
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#define MPIC_SOFT_INT_DRBL1 (1 << 5)
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#define MPIC_ERR_CAUSE 0x20
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#define MPIC_ISE 0x30
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#define MPIC_ICE 0x34
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#define MPIC_IN_DOORBELL 0x78
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#define MPIC_IN_DOORBELL_MASK 0x7c
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#define MPIC_IN_DRBL 0x78
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#define MPIC_IN_DRBL_MASK 0x7c
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#define MPIC_CTP 0xb0
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#define MPIC_CTP 0xb0
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#define MPIC_IIACK 0xb4
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@ -71,16 +83,20 @@ __FBSDID("$FreeBSD$");
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#define MPIC_ERR_MASK 0xec0
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struct mv_mpic_softc {
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struct resource * mpic_res[2];
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device_t sc_dev;
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struct resource * mpic_res[3];
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bus_space_tag_t mpic_bst;
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bus_space_handle_t mpic_bsh;
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bus_space_tag_t cpu_bst;
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bus_space_handle_t cpu_bsh;
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bus_space_tag_t drbl_bst;
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bus_space_handle_t drbl_bsh;
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};
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static struct resource_spec mv_mpic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE },
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{ -1, 0 }
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};
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@ -92,14 +108,21 @@ static int mv_mpic_probe(device_t);
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static int mv_mpic_attach(device_t);
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uint32_t mv_mpic_get_cause(void);
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uint32_t mv_mpic_get_cause_err(void);
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uint32_t mv_mpic_get_msi(void);
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static void arm_mask_irq_err(uintptr_t);
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static void arm_unmask_irq_err(uintptr_t);
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static void arm_unmask_msi(void);
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#define MPIC_CPU_WRITE(softc, reg, val) \
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bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
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#define MPIC_CPU_READ(softc, reg) \
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bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
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#define MPIC_DRBL_WRITE(softc, reg, val) \
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bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
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#define MPIC_DRBL_READ(softc, reg) \
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bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
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static int
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mv_mpic_probe(device_t dev)
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{
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@ -123,6 +146,8 @@ mv_mpic_attach(device_t dev)
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return (ENXIO);
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mv_mpic_sc = sc;
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sc->sc_dev = dev;
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error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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@ -135,10 +160,15 @@ mv_mpic_attach(device_t dev)
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sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
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sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
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sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
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sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_CTRL, 1);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
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arm_unmask_msi();
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return (0);
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}
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@ -167,8 +197,10 @@ arm_get_next_irq(int last)
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CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);
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if (irq != IRQ_MASK) {
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if (irq == IRQ_ERR)
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if (irq == MPIC_INT_ERR)
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irq = mv_mpic_get_cause_err();
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if (irq == MPIC_INT_MSI)
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irq = mv_mpic_get_msi();
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next = irq;
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}
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@ -186,11 +218,11 @@ arm_mask_irq(uintptr_t nb)
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1);
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if (nb < MAIN_IRQS) {
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if (nb < ERR_IRQ) {
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ICE, nb);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
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} else
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} else if (nb < MSI_IRQ)
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arm_mask_irq_err(nb);
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}
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@ -201,7 +233,7 @@ arm_mask_irq_err(uintptr_t nb)
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uint32_t mask;
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uint8_t bit_off;
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bit_off = nb - MAIN_IRQS;
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bit_off = nb - ERR_IRQ;
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mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
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mask &= ~(1 << bit_off);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
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@ -213,15 +245,15 @@ arm_unmask_irq(uintptr_t nb)
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
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if (nb < MAIN_IRQS) {
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if (nb < ERR_IRQ) {
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ISE, nb);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
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} else
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} else if (nb < MSI_IRQ)
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arm_unmask_irq_err(nb);
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if (nb == 0)
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DOORBELL_MASK, 0xffffffff);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
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}
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void
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@ -231,15 +263,22 @@ arm_unmask_irq_err(uintptr_t nb)
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uint8_t bit_off;
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bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
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MPIC_ISE, IRQ_ERR);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, IRQ_ERR);
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MPIC_ISE, MPIC_INT_ERR);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
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bit_off = nb - MAIN_IRQS;
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bit_off = nb - ERR_IRQ;
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mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
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mask |= (1 << bit_off);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
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}
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static void
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arm_unmask_msi(void)
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{
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arm_unmask_irq(MPIC_INT_MSI);
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}
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uint32_t
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mv_mpic_get_cause(void)
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{
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@ -260,7 +299,61 @@ mv_mpic_get_cause_err(void)
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bit_off = ffs(err_cause) - 1;
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else
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return (-1);
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return (MAIN_IRQS + bit_off);
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debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
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return (ERR_IRQ + bit_off);
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}
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uint32_t
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mv_mpic_get_msi(void)
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{
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uint32_t cause;
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uint8_t bit_off;
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cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
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if (cause)
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bit_off = ffs(cause) - 1;
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else
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return (-1);
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debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
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cause &= ~(1 << bit_off);
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MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
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return (MSI_IRQ + bit_off);
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}
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int
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mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
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{
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u_long phys, base, size;
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phandle_t node;
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int error;
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node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
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/* Get physical addres of register space */
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error = fdt_get_range(OF_parent(node), 0, &phys, &size);
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if (error) {
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printf("%s: Cannot get register physical address, err:%d",
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__func__, error);
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return (error);
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}
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/* Get offset of MPIC register space */
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error = fdt_regsize(node, &base, &size);
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if (error) {
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printf("%s: Cannot get MPIC register offset, err:%d",
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__func__, error);
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return (error);
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}
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*addr = phys + base + MPIC_SOFT_INT;
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*data = MPIC_SOFT_INT_DRBL1 | irq;
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return (0);
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}
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#if defined(SMP)
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@ -283,7 +376,7 @@ pic_ipi_get(int i __unused)
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{
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uint32_t val;
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val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DOORBELL);
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val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
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if (val)
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return (ffs(val) - 1);
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@ -296,7 +389,7 @@ pic_ipi_clear(int ipi)
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uint32_t val;
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val = ~(1 << ipi);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DOORBELL, val);
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MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, val);
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}
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#endif
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@ -134,4 +134,6 @@ uint32_t mv_drbl_get_cause(int dir, int unit);
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void mv_drbl_set_msg(uint32_t val, int mnr, int dir, int unit);
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uint32_t mv_drbl_get_msg(int mnr, int dir, int unit);
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int mv_msi_data(int irq, uint64_t *addr, uint32_t *data);
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#endif /* _MVVAR_H_ */
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@ -75,7 +75,7 @@
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x20a00 0x500 0x21000 0x800>;
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reg = <0x20a00 0x500 0x21000 0x800 0x20400 0x100>;
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compatible = "mrvl,mpic";
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};
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