Extract vendor specific Book-E pieces into separate files and have a common
skeleton (maybe we should kobj-tize this one day). Note the PPC4xx bit is not connected to the build yet. Obtained from: AppliedMicro, Semihalf.
This commit is contained in:
parent
87e7271687
commit
aa6bc7dc29
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=236324
@ -102,6 +102,7 @@ powerpc/booke/copyinout.c optional booke
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powerpc/booke/interrupt.c optional booke
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powerpc/booke/locore.S optional booke no-obj
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powerpc/booke/machdep.c optional booke
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powerpc/booke/machdep_e500.c optional booke_e500
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powerpc/booke/mp_cpudep.c optional booke smp
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powerpc/booke/platform_bare.c optional mpc85xx
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powerpc/booke/pmap.c optional booke
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@ -1,5 +1,5 @@
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/*-
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* Copyright (C) 2006-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -129,6 +129,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/md_var.h>
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#include <machine/mmuvar.h>
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#include <machine/sigframe.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/platform.h>
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@ -138,8 +139,6 @@ __FBSDID("$FreeBSD$");
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#ifdef DDB
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extern vm_offset_t ksym_start, ksym_end;
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#endif
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@ -158,11 +157,6 @@ extern unsigned char __sbss_start[];
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extern unsigned char __sbss_end[];
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extern unsigned char _end[];
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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/*
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* Bootinfo is passed to us by legacy loaders. Save the address of the
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* structure to handle backward compatibility.
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@ -286,7 +280,6 @@ booke_init(uint32_t arg1, uint32_t arg2)
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struct pcpu *pc;
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void *kmdp, *mdp;
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vm_offset_t dtbp, end;
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uint32_t csr;
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kmdp = NULL;
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@ -359,9 +352,9 @@ booke_init(uint32_t arg1, uint32_t arg2)
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while (1);
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OF_interpret("perform-fixup", 0);
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/* Initialize TLB1 handling */
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tlb1_init(fdt_immr_pa);
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/* Set up TLB initially */
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booke_init_tlb(fdt_immr_pa);
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/* Reset Time Base */
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mttb(0);
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@ -396,10 +389,6 @@ booke_init(uint32_t arg1, uint32_t arg2)
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debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
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debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
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debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
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__asm __volatile("msync; isync");
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csr = ccsr_read4(OCP85XX_L2CTL);
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debugf(" L2CTL = 0x%08x\n", csr);
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#endif
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debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
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@ -447,29 +436,8 @@ booke_init(uint32_t arg1, uint32_t arg2)
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mtmsr(mfmsr() | PSL_ME);
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isync();
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/* Enable D-cache if applicable */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
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printf("L1 D-cache %sabled\n",
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(csr & L1CSR0_DCE) ? "en" : "dis");
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/* Enable L1 I-cache if applicable. */
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
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printf("L1 I-cache %sabled\n",
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(csr & L1CSR1_ICE) ? "en" : "dis");
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/* Enable L1 caches */
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booke_enable_l1_cache();
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debugf("%s: SP = 0x%08x\n", __func__,
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((uintptr_t)thread0.td_pcb - 16) & ~15);
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158
sys/powerpc/booke/machdep_e500.c
Normal file
158
sys/powerpc/booke/machdep_e500.c
Normal file
@ -0,0 +1,158 @@
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/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/reboot.h>
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#include <machine/machdep.h>
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#include <dev/fdt/fdt_common.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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extern void l2cache_enable(void);
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extern void l2cache_inval(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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/* Initialize TLB1 handling */
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tlb1_init(fdt_immr_pa);
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}
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void
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booke_enable_l1_cache(void)
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{
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uint32_t csr;
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/* Enable D-cache if applicable */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
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printf("L1 D-cache %sabled\n",
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(csr & L1CSR0_DCE) ? "en" : "dis");
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/* Enable L1 I-cache if applicable. */
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
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printf("L1 I-cache %sabled\n",
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(csr & L1CSR1_ICE) ? "en" : "dis");
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}
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#if 0
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void
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booke_enable_l2_cache(void)
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{
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uint32_t csr;
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/* Enable L2 cache on E500mc */
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if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
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(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
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csr = mfspr(SPR_L2CSR0);
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if ((csr & L2CSR0_L2E) == 0) {
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l2cache_inval();
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l2cache_enable();
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}
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csr = mfspr(SPR_L2CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
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printf("L2 cache %sabled\n",
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(csr & L2CSR0_L2E) ? "en" : "dis");
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}
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}
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void
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booke_enable_l3_cache(void)
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{
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uint32_t csr, size, ver;
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/* Enable L3 CoreNet Platform Cache (CPC) */
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
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ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
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l3cache_inval();
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l3cache_enable();
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}
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((boothowto & RB_VERBOSE) != 0 ||
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(csr & OCP85XX_CPC_CSR0_CE) == 0) {
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size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
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printf("L3 Corenet Platform Cache: %d KB %sabled\n",
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size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
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"dis" : "en");
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}
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}
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}
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void
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booke_disable_l2_cache(void)
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{
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}
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static void
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l3cache_inval(void)
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{
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/* Flash invalidate the CPC and clear all the locks */
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC);
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while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC))
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;
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}
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static void
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l3cache_enable(void)
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{
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
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OCP85XX_CPC_CSR0_PE);
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/* Read back to sync write */
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ccsr_read4(OCP85XX_CPC_CSR0);
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}
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#endif
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sys/powerpc/booke/machdep_ppc4xx.c
Normal file
219
sys/powerpc/booke/machdep_ppc4xx.c
Normal file
@ -0,0 +1,219 @@
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/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
|
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/machdep.h>
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#include <powerpc/booke/dcr.h>
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#include <powerpc/apm86xxx/apm86xxx.h>
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#include <dev/fdt/fdt_common.h>
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#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF))
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#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32))
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extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t,
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uint32_t);
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extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *,
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uint32_t *, uint32_t *);
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unsigned int tlb_static_entries;
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unsigned int tlb_current_entry = TLB_SIZE;
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unsigned int tlb_misses = 0;
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unsigned int tlb_invals = 0;
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void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);
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void tlb_map_mem(uint32_t, uint32_t, uint32_t);
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void tlb_dump(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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/* Map register space */
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tlb_map(APM86XXX_DEEP_SLEEP_VA,
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OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA),
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OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA),
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OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_PRIMARY_FABRIC_VA,
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OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA),
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OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA),
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OCP_ADDR_WORDHI(APM86XXX_AHB_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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/* Map MailBox space */
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tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA),
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x1000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x2000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
|
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TLB_UX | TLB_UW | TLB_UR |
|
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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}
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void
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booke_enable_l1_cache(void)
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{
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}
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|
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void
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booke_enable_l2_cache(void)
|
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{
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}
|
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|
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void
|
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booke_enable_l3_cache(void)
|
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{
|
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}
|
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|
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void
|
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booke_disable_l2_cache(void)
|
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{
|
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uint32_t ccr1,l2cr0;
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|
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/* Disable L2 cache op broadcast */
|
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ccr1 = mfspr(SPR_CCR1);
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ccr1 &= ~CCR1_L2COBE;
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mtspr(SPR_CCR1, ccr1);
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/* Set L2 array size to 0 i.e. disable L2 cache */
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mtdcr(DCR_L2DCDCRAI, DCR_L2CR0);
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l2cr0 = mfdcr(DCR_L2DCDCRDI);
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l2cr0 &= ~L2CR0_AS;
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mtdcr(DCR_L2DCDCRDI, l2cr0);
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}
|
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void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags,
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uint32_t perms)
|
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{
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tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms);
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}
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|
||||
static void tlb_dump_entry(u_int entry)
|
||||
{
|
||||
uint32_t epn, rpn, erpn, tid, flags, perms;
|
||||
const char *size;
|
||||
|
||||
tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms);
|
||||
|
||||
switch (flags & TLB_SIZE_MASK) {
|
||||
case TLB_SIZE_1K:
|
||||
size = " 1k";
|
||||
break;
|
||||
case TLB_SIZE_4K:
|
||||
size = " 4k";
|
||||
break;
|
||||
case TLB_SIZE_16K:
|
||||
size = " 16k";
|
||||
break;
|
||||
case TLB_SIZE_256K:
|
||||
size = "256k";
|
||||
break;
|
||||
case TLB_SIZE_1M:
|
||||
size = " 1M";
|
||||
break;
|
||||
case TLB_SIZE_16M:
|
||||
size = " 16M";
|
||||
break;
|
||||
case TLB_SIZE_256M:
|
||||
size = "256M";
|
||||
break;
|
||||
case TLB_SIZE_1G:
|
||||
size = " 1G";
|
||||
break;
|
||||
default:
|
||||
size = "????";
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
printf("TLB[%02u]: 0x%08X => "
|
||||
"0x%01X_%08X %s %c %c %s %s %s %s %s "
|
||||
"%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n",
|
||||
entry, epn, erpn, rpn, size,
|
||||
(flags & TLB_TS) ? '1' : '0',
|
||||
(flags & TLB_VALID) ? 'V' : '.',
|
||||
(perms & TLB_WL1) ? "WL1" : "___",
|
||||
(perms & TLB_IL1I) ? "IL1I" : "____",
|
||||
(perms & TLB_IL1D) ? "IL1D" : "____",
|
||||
(perms & TLB_IL2I) ? "IL2I" : "____",
|
||||
(perms & TLB_IL2D) ? "IL2D" : "____",
|
||||
(perms & TLB_U0) ? '1' : '.',
|
||||
(perms & TLB_U1) ? '2' : '.',
|
||||
(perms & TLB_U2) ? '3' : '.',
|
||||
(perms & TLB_U3) ? '4' : '.',
|
||||
(perms & TLB_W) ? 'W' : '.',
|
||||
(perms & TLB_I) ? 'I' : '.',
|
||||
(perms & TLB_M) ? 'M' : '.',
|
||||
(perms & TLB_G) ? 'G' : '.',
|
||||
(perms & TLB_E) ? 'E' : '.',
|
||||
(perms & TLB_UX) ? 'x' : '.',
|
||||
(perms & TLB_UW) ? 'w' : '.',
|
||||
(perms & TLB_UR) ? 'r' : '.',
|
||||
(perms & TLB_SX) ? 'X' : '.',
|
||||
(perms & TLB_SW) ? 'W' : '.',
|
||||
(perms & TLB_SR) ? 'R' : '.',
|
||||
tid);
|
||||
}
|
||||
|
||||
void tlb_dump(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < TLB_SIZE; i++)
|
||||
tlb_dump_entry(i);
|
||||
}
|
39
sys/powerpc/include/machdep.h
Normal file
39
sys/powerpc/include/machdep.h
Normal file
@ -0,0 +1,39 @@
|
||||
/*-
|
||||
* Copyright (c) 2011-2012 Semihalf
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _POWERPC_MACHDEP_H_
|
||||
#define _POWERPC_MACHDEP_H_
|
||||
|
||||
void booke_disable_l2_cache(void);
|
||||
void booke_enable_l1_cache(void);
|
||||
void booke_enable_l2_cache(void);
|
||||
void booke_enable_l3_cache(void);
|
||||
void booke_enable_bpred(void);
|
||||
void booke_init_tlb(vm_paddr_t);
|
||||
|
||||
#endif /* _POWERPC_MACHDEP_H_ */
|
Loading…
Reference in New Issue
Block a user