o Convert to <inttypes.h> style fixed sized types to facilitate porting to
other systems. o Normalize copyright text. o Clean up probe code function interfaces by passing around a single structure of common arguments instead of passing "too many" args in each function call. o Add support for the AAA-131 as a SCSI adapter. o Add support for the AHA-4944 courtesy of "Matthew N. Dodd" <winter@jurai.net o Correct manual termination support for PCI cards. The bit definitions for manual termination control in the SEEPROM were incorrect. o Add support for extracting NVRAM information from SCB 2 for BIOSen that use this mechanism to pass this data to OS drivers. o Properly set the STPWLEVEL bit in PCI config space based on the setting in an SEEPROM. o Go back to useing 32byte SCBs for all controllers. The current firmware allows us to embed 12byte cdbs on all controllers in a 32byte SCB, and larger cdbs are rarely used, so it is a better use of this space to offer more SCBs (32). o Add support for U160 transfers. o Add an idle loop executed during data transfers that prefetches S/G segments on controllers that have a secondary DMA engine (aic789X). o Improve the performance of reselections by avoiding an extra one byte DMA in the case of an SCB lookup miss for the reselecting target. We now keep a 16byte "untagged target" array on the card for dealing with untagged reselections. If the controller has external SCB ram and can support 64byte SCBs, then we use an "untagged target/lun" array to maximize concurrency. Without external SCB ram, the controller is limited to one untagged transaction per target, auto-request sense operations excluded. o Correct the setup of the STPWEN bit in SXFRCTL1. This control line is tri-stated until set to one, so set it to one and then set it to the desired value. o Add tagged queuing support to our target role implementation. o Handle the common cases of the ignore wide residue message in firmware. o Add preliminary support for 39bit addressing. o Add support for assembling on big-endian machines. Big-endian support is not complete in the driver. o Correctly remove SCBs in the waiting for selection queue when freezing a device queue. o Now that we understand more about the autoflush bug on the aic7890, only use the workaround on devices that need it. o Add a workaround for the "aic7890 hangs the system when you attempt to pause it" problem. We can now pause the aic7890 safely regardless of what instruction it is executing.
This commit is contained in:
Justin T. Gibbs
parent
d4e2be3050
commit
aa6dfd9d3d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=63457
@ -89,14 +89,14 @@ static struct seeprom_cmd {
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int
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read_seeprom(sd, buf, start_addr, count)
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struct seeprom_descriptor *sd;
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u_int16_t *buf;
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uint16_t *buf;
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bus_size_t start_addr;
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bus_size_t count;
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{
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int i = 0;
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u_int k = 0;
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u_int16_t v;
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u_int8_t temp;
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uint16_t v;
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uint8_t temp;
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/*
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* Read the requested registers of the seeprom. The loop
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@ -16,7 +16,7 @@
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* the GNU Public License ("GPL").
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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@ -52,12 +52,12 @@ struct seeprom_descriptor {
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bus_size_t sd_status_offset;
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bus_size_t sd_dataout_offset;
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seeprom_chip_t sd_chip;
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u_int16_t sd_MS;
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u_int16_t sd_RDY;
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u_int16_t sd_CS;
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u_int16_t sd_CK;
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u_int16_t sd_DO;
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u_int16_t sd_DI;
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uint16_t sd_MS;
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uint16_t sd_RDY;
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uint16_t sd_CS;
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uint16_t sd_CK;
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uint16_t sd_DO;
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uint16_t sd_DI;
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};
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/*
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@ -85,7 +85,7 @@ struct seeprom_descriptor {
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#define SEEPROM_DATA_INB(sd) \
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bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset)
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int read_seeprom(struct seeprom_descriptor *sd, u_int16_t *buf,
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int read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
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bus_size_t start_addr, bus_size_t count);
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#endif /* _KERNEL */
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@ -90,10 +90,10 @@ static int
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aic7770_probe(device_t dev)
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{
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const char *desc;
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u_int32_t iobase;
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u_int32_t irq;
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u_int8_t intdef;
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u_int8_t hcntrl;
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uint32_t iobase;
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uint32_t irq;
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uint8_t intdef;
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uint8_t hcntrl;
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int shared;
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desc = aic7770_match(eisa_get_id(dev));
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@ -138,7 +138,7 @@ aic7770_probe(device_t dev)
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static int
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aic7770_attach(device_t dev)
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{
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ahc_chip chip;
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struct ahc_probe_config probe_config;
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bus_dma_tag_t parent_dmat;
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struct ahc_softc *ahc;
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struct resource *io;
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@ -147,20 +147,27 @@ aic7770_attach(device_t dev)
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rid = 0;
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io = NULL;
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ahc = NULL;
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ahc_init_probe_config(&probe_config);
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switch (eisa_get_id(dev)) {
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case EISA_DEVICE_ID_ADAPTEC_274x:
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case EISA_DEVICE_ID_ADAPTEC_AIC7770:
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chip = AHC_AIC7770|AHC_EISA;
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probe_config.chip = AHC_AIC7770|AHC_EISA;
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break;
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case EISA_DEVICE_ID_ADAPTEC_284xB:
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case EISA_DEVICE_ID_ADAPTEC_284x:
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chip = AHC_AIC7770|AHC_VL;
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probe_config.chip = AHC_AIC7770|AHC_VL;
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break;
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default:
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printf("aic7770_attach: Unknown device type!\n");
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goto bad;
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}
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probe_config.description = aic7770_match(eisa_get_id(dev));
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probe_config.channel = 'A';
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probe_config.channel_b = 'B';
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probe_config.features = AHC_AIC7770_FE;
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probe_config.bugs |= AHC_TMODE_WIDEODD_BUG;
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probe_config.flags |= AHC_PAGESCBS;
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/* XXX Should be a child of the EISA bus dma tag */
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error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
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/*boundary*/0,
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@ -186,14 +193,11 @@ aic7770_attach(device_t dev)
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}
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if (!(ahc = ahc_alloc(dev, io, SYS_RES_IOPORT, rid,
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parent_dmat, chip, AHC_AIC7770_FE, AHC_FNONE,
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NULL)))
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parent_dmat, &probe_config, NULL)))
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goto bad;
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io = NULL;
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ahc->channel = 'A';
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ahc->channel_b = 'B';
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if (ahc_reset(ahc) != 0) {
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goto bad;
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}
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@ -228,7 +232,7 @@ aic7770_attach(device_t dev)
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*
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* First, the aic7770 card specific setup.
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*/
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switch (chip & (AHC_EISA|AHC_VL)) {
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switch (probe_config.chip & (AHC_EISA|AHC_VL)) {
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case AHC_EISA:
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{
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u_int biosctrl;
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@ -299,8 +303,8 @@ aic7770_attach(device_t dev)
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*/
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{
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char *id_string;
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u_int8_t sblkctl;
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u_int8_t sblkctl_orig;
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uint8_t sblkctl;
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uint8_t sblkctl_orig;
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sblkctl_orig = ahc_inb(ahc, SBLKCTL);
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sblkctl = sblkctl_orig ^ AUTOFLUSHDIS;
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@ -322,7 +326,7 @@ aic7770_attach(device_t dev)
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/* Setup the FIFO threshold and the bus off time */
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{
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u_int8_t hostconf = ahc_inb(ahc, HOSTCONF);
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uint8_t hostconf = ahc_inb(ahc, HOSTCONF);
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ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
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ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
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}
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@ -366,8 +370,8 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
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{
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struct seeprom_descriptor sd;
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struct seeprom_config sc;
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u_int16_t checksum = 0;
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u_int8_t scsi_conf;
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uint16_t checksum = 0;
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uint8_t scsi_conf;
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int have_seeprom;
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sd.sd_tag = ahc->tag;
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@ -386,7 +390,7 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
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if (bootverbose)
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printf("%s: Reading SEEPROM...", ahc_name(ahc));
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have_seeprom = read_seeprom(&sd,
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(u_int16_t *)&sc,
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(uint16_t *)&sc,
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/*start_addr*/0,
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sizeof(sc)/2);
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@ -394,7 +398,7 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
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/* Check checksum */
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int i;
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int maxaddr = (sizeof(sc)/2) - 1;
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u_int16_t *scarray = (u_int16_t *)≻
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uint16_t *scarray = (uint16_t *)≻
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for (i = 0; i < maxaddr; i++)
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checksum = checksum + scarray[i];
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@ -418,11 +422,11 @@ aha2840_load_seeprom(struct ahc_softc *ahc)
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*/
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int i;
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int max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
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u_int16_t discenable;
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uint16_t discenable;
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discenable = 0;
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for (i = 0; i < max_targ; i++){
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u_int8_t target_settings;
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uint8_t target_settings;
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target_settings = (sc.device_flags[i] & CFXFER) << 4;
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if (sc.device_flags[i] & CFSYNCH)
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target_settings |= SOFS;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -16,7 +16,7 @@
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* the GNU Public License ("GPL").
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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@ -37,6 +37,7 @@
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#define _AIC7XXX_H_
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#include "opt_aic7xxx.h" /* for config options */
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#include "aic7xxx_reg.h"
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#include <sys/bus.h> /* For device_t */
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@ -48,21 +49,38 @@
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#define MIN(a,b) (((a) < (b)) ? (a) : (b))
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#endif
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/*
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* The maximum number of supported targets.
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*/
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#define AHC_NUM_TARGETS 16
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/*
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* The maximum number of supported luns.
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* Although the identify message only supports 64 luns in SPI3, you
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* can have 2^64 luns when information unit transfers are enabled.
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* The max we can do sanely given the 8bit nature of the RISC engine
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* on these chips is 256.
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*/
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#define AHC_NUM_LUNS 256
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/*
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* The maximum transfer per S/G segment.
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*/
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#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
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/*
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* The number of dma segments supported. The current implementation limits
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* us to 255 S/G entries (this may change to be unlimited at some point).
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* To reduce the driver's memory consumption, we further limit the number
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* supported to be sufficient to handle the largest mapping supported by
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* the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible
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* and unaligned, this turns out to be the number of paged sized transfers
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* in MAXPHYS plus an extra element to handle any unaligned residual.
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* The number of dma segments supported. The sequencer can handle any number
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* of physically contiguous S/G entrys. To reduce the driver's memory
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* consumption, we limit the number supported to be sufficient to handle
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* the largest mapping supported by the kernel, MAXPHYS. Assuming the
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* transfer is as fragmented as possible and unaligned, this turns out to
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* be the number of paged sized transfers in MAXPHYS plus an extra element
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* to handle any unaligned residual. The sequencer fetches SG elements
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* in 128 byte chucks, so make the number per-transaction a nice multiple
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* of 16 (8 byte S/G elements).
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*/
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#define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255))
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/* XXX Worth the space??? */
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#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16))
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#define AHC_SCB_MAX 255 /*
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* Up to 255 SCBs on some types of aic7xxx
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@ -79,11 +97,23 @@
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* wrap point of an 8bit counter.
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*/
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/*
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* The aic7xxx chips only support a 24bit length. We use the top
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* byte of the length to store additional address bits as well
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* as an indicator if this is the last SG segment in a transfer.
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* This gives us an addressable range of 512GB on machines with
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* 64bit PCI or with chips that can support dual address cycles
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* on 32bit PCI busses.
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*/
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struct ahc_dma_seg {
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u_int32_t addr;
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u_int32_t len;
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uint32_t addr;
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uint32_t len;
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#define AHC_DMA_LAST_SEG 0x80000000
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#define AHC_SG_HIGH_ADDR_MASK 0x7F000000
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#define AHC_SG_LEN_MASK 0x00FFFFFF
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};
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/* The chip order is from least sophisticated to most sophisticated */
|
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typedef enum {
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AHC_NONE = 0x0000,
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AHC_CHIPID_MASK = 0x00FF,
|
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@ -94,10 +124,10 @@ typedef enum {
|
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AHC_AIC7860 = 0x0005,
|
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AHC_AIC7870 = 0x0006,
|
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AHC_AIC7880 = 0x0007,
|
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AHC_AIC7890 = 0x0008,
|
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AHC_AIC7892 = 0x0009,
|
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AHC_AIC7895 = 0x000a,
|
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AHC_AIC7896 = 0x000b,
|
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AHC_AIC7895 = 0x0008,
|
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AHC_AIC7890 = 0x0009,
|
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AHC_AIC7896 = 0x000a,
|
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AHC_AIC7892 = 0x000b,
|
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AHC_AIC7899 = 0x000c,
|
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AHC_VL = 0x0100, /* Bus type VL */
|
||||
AHC_EISA = 0x0200, /* Bus type EISA */
|
||||
@ -123,25 +153,41 @@ typedef enum {
|
||||
AHC_DT = 0x0800, /* Double Transition transfers */
|
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AHC_NEW_TERMCTL = 0x1000,
|
||||
AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */
|
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AHC_TARG_DMABUG = 0x4000, /* WideOdd Data-In bug in TMODE */
|
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AHC_AIC7770_FE = AHC_TARG_DMABUG,
|
||||
AHC_AIC7850_FE = AHC_TARG_DMABUG|AHC_SPIOCAP,
|
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AHC_LARGE_SCBS = 0x4000, /* 64byte SCBs */
|
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AHC_AIC7770_FE = AHC_FENONE,
|
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AHC_AIC7850_FE = AHC_SPIOCAP,
|
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AHC_AIC7855_FE = AHC_AIC7850_FE,
|
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AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA,
|
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AHC_AIC7860_FE = AHC_AIC7859_FE,
|
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AHC_AIC7870_FE = AHC_TARG_DMABUG,
|
||||
AHC_AIC7880_FE = AHC_TARG_DMABUG|AHC_ULTRA,
|
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AHC_AIC7870_FE = AHC_FENONE,
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AHC_AIC7880_FE = AHC_ULTRA,
|
||||
AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
|
||||
|AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX
|
||||
|AHC_NEW_TERMCTL,
|
||||
|AHC_NEW_TERMCTL|AHC_LARGE_SCBS,
|
||||
AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT,
|
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AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM
|
||||
|AHC_CMD_CHAN|AHC_MULTI_FUNC,
|
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|AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
|
||||
AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
|
||||
AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
|
||||
AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
|
||||
} ahc_feature;
|
||||
|
||||
typedef enum {
|
||||
AHC_BUGNONE = 0x00,
|
||||
/*
|
||||
* On all chips prior to the U2 product line,
|
||||
* the WIDEODD S/G segment feature does not
|
||||
* work during scsi->HostBus transfers.
|
||||
*/
|
||||
AHC_TMODE_WIDEODD_BUG = 0x01,
|
||||
/*
|
||||
* On the aic7890/91 Rev 0 chips, the autoflush
|
||||
* feature does not work. A manual flush of
|
||||
* the DMA FIFO is required.
|
||||
*/
|
||||
AHC_AUTOFLUSH_BUG = 0x02
|
||||
} ahc_bug;
|
||||
|
||||
typedef enum {
|
||||
AHC_FNONE = 0x000,
|
||||
AHC_PAGESCBS = 0x001,/* Enable SCB paging */
|
||||
@ -179,8 +225,23 @@ typedef enum {
|
||||
* Internal 50pin connector
|
||||
* sits behind an aic3860
|
||||
*/
|
||||
AHC_SCB_BTT = 0x40000 /*
|
||||
* The busy targets table is
|
||||
* stored in SCB space rather
|
||||
* than SRAM.
|
||||
*/
|
||||
} ahc_flag;
|
||||
|
||||
struct ahc_probe_config {
|
||||
const char *description;
|
||||
char channel;
|
||||
char channel_b;
|
||||
ahc_chip chip;
|
||||
ahc_feature features;
|
||||
ahc_bug bugs;
|
||||
ahc_flag flags;
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
SCB_FREE = 0x0000,
|
||||
SCB_OTHERTCL_TIMEOUT = 0x0002,/*
|
||||
@ -194,6 +255,7 @@ typedef enum {
|
||||
SCB_DEVICE_RESET = 0x0004,
|
||||
SCB_SENSE = 0x0008,
|
||||
SCB_RECOVERY_SCB = 0x0040,
|
||||
SCB_NEGOTIATE = 0x0080,
|
||||
SCB_ABORT = 0x1000,
|
||||
SCB_QUEUED_MSG = 0x2000,
|
||||
SCB_ACTIVE = 0x4000,
|
||||
@ -204,57 +266,116 @@ typedef enum {
|
||||
* The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
|
||||
* consists of a "hardware SCB" mirroring the fields availible on the card
|
||||
* and additional information the kernel stores for each transaction.
|
||||
*
|
||||
* To minimize space utilization, a portion of the hardware scb stores
|
||||
* different data during different portions of a SCSI transaction.
|
||||
* As initialized by the host driver for the initiator role, this area
|
||||
* contains the SCSI cdb (or pointer to the cdb) to be executed. After
|
||||
* the cdb has been presented to the target, this area serves to store
|
||||
* residual transfer information and the SCSI status byte.
|
||||
* For the target role, the contents of this area do not change, but
|
||||
* still serve a different purpose than for the initiator role. See
|
||||
* struct target_data for details.
|
||||
*/
|
||||
|
||||
struct status_pkt {
|
||||
uint32_t residual_datacnt;
|
||||
uint32_t residual_sg_ptr;
|
||||
uint8_t scsi_status;
|
||||
};
|
||||
|
||||
struct target_data {
|
||||
uint8_t target_phases;
|
||||
uint8_t data_phase;
|
||||
uint8_t scsi_status;
|
||||
uint8_t initiator_tag;
|
||||
};
|
||||
|
||||
struct hardware_scb {
|
||||
/*0*/ u_int8_t control;
|
||||
/*1*/ u_int8_t tcl; /* 4/1/3 bits */
|
||||
/*2*/ u_int8_t status;
|
||||
/*3*/ u_int8_t SG_count;
|
||||
/*4*/ u_int32_t SG_pointer;
|
||||
/*8*/ u_int8_t residual_SG_count;
|
||||
/*9*/ u_int8_t residual_data_count[3];
|
||||
/*12*/ u_int32_t data;
|
||||
/*16*/ u_int32_t datalen; /* Really only three bytes, but its
|
||||
* faster to treat it as a long on
|
||||
* a quad boundary.
|
||||
/*0*/ uint8_t control;
|
||||
/*1*/ uint8_t scsiid; /* what to load in the SCSIID register */
|
||||
/*2*/ uint8_t lun;
|
||||
/*3*/ uint8_t cdb_len;
|
||||
/*4*/ union {
|
||||
/*
|
||||
* 12 bytes of cdb information only
|
||||
* used on chips with 32byte SCBs.
|
||||
*/
|
||||
uint8_t cdb[12];
|
||||
uint32_t cdb_ptr;
|
||||
struct status_pkt status;
|
||||
struct target_data tdata;
|
||||
} shared_data;
|
||||
/*
|
||||
* A word about residuals. The scb is presented to the sequencer with
|
||||
* the dataptr and datacnt fields initialized to the contents of the
|
||||
* first S/G element to transfer. The sgptr field is initialized to
|
||||
* the bus address for the S/G element that follows the first in the
|
||||
* in core S/G array or'ed with the SG_FULL_RESID flag. Sgptr may point
|
||||
* to an invalid S/G entry for this transfer. If no transfer is to occur,
|
||||
* sgptr is set to SG_LIST_NULL. The SG_FULL_RESID flag insures that
|
||||
* the residual will be correctly noted even if no data transfers occur.
|
||||
* Once the data phase is entered, the residual sgptr and datacnt are
|
||||
* loaded from the sgptr and the datacnt fields. After each S/G element's
|
||||
* dataptr and length are loaded into the hardware, the residual sgptr
|
||||
* is advanced. After each S/G element is expired, its datacnt field
|
||||
* is checked to see if the LAST_SEG flag is set. If so, SG_LIST_NULL
|
||||
* is set in the residual sg ptr and the transfer is considered complete.
|
||||
* If the sequencer determines that three is a residual in the tranfer,
|
||||
* it will set the SG_RESID_VALID flag in sgptr and dma the scb back into
|
||||
* host memory. To sumarize:
|
||||
*
|
||||
* Sequencer:
|
||||
* o A residual has occurred if SG_FULL_RESID is set in sgptr,
|
||||
* or residual_sgptr does not have SG_LIST_NULL set.
|
||||
*
|
||||
* o We are transfering the last segment if residual_datacnt has
|
||||
* the SG_LAST_SEG flag set.
|
||||
*
|
||||
* Host:
|
||||
* o A residual has occurred if a completed scb has the
|
||||
* SG_RESID_VALID flag set.
|
||||
*
|
||||
* o residual_sgptr and sgptr refer to the "next" sg entry
|
||||
* and so may point beyond the last valid sg entry for the
|
||||
* transfer.
|
||||
*/
|
||||
/*16*/ uint32_t dataptr;
|
||||
/*20*/ uint32_t datacnt; /*
|
||||
* The highest address byte is
|
||||
* really the 5th. byte in the
|
||||
* dataptr.
|
||||
*/
|
||||
/*20*/ u_int32_t cmdpointer;
|
||||
/*24*/ u_int8_t cmdlen;
|
||||
/*25*/ u_int8_t tag; /* Index into our kernel SCB array.
|
||||
/*24*/ uint32_t sgptr;
|
||||
#define SG_PTR_MASK 0xFFFFFFF8
|
||||
/*28*/ uint8_t tag; /* Index into our kernel SCB array.
|
||||
* Also used as the tag for tagged I/O
|
||||
*/
|
||||
/*26*/ u_int8_t next; /* Used for threading SCBs in the
|
||||
/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
|
||||
/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
|
||||
/*31*/ uint8_t next; /* Used for threading SCBs in the
|
||||
* "Waiting for Selection" and
|
||||
* "Disconnected SCB" lists down
|
||||
* in the sequencer.
|
||||
*/
|
||||
/*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */
|
||||
/*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */
|
||||
/*29*/ u_int8_t spare[3]; /*
|
||||
* Spare space available on
|
||||
* all controller types.
|
||||
*/
|
||||
/*32*/ u_int8_t cmdstore[16]; /*
|
||||
/*32*/ uint8_t cdb32[32]; /*
|
||||
* CDB storage for controllers
|
||||
* supporting 64 byte SCBs.
|
||||
*/
|
||||
/*48*/ u_int32_t cmdstore_busaddr; /*
|
||||
* Address of command store for
|
||||
* 32byte SCB adapters
|
||||
*/
|
||||
/*48*/ u_int8_t spare_64[12]; /*
|
||||
* Pad to 64 bytes.
|
||||
*/
|
||||
};
|
||||
|
||||
struct scb {
|
||||
struct hardware_scb *hscb;
|
||||
SLIST_ENTRY(scb) links; /* for chaining */
|
||||
union {
|
||||
SLIST_ENTRY(scb) sle;
|
||||
TAILQ_ENTRY(scb) tqe;
|
||||
} links;
|
||||
union ccb *ccb; /* the ccb for this cmd */
|
||||
scb_flag flags;
|
||||
bus_dmamap_t dmamap;
|
||||
struct ahc_dma_seg *sg_list;
|
||||
bus_addr_t sg_list_phys;
|
||||
bus_addr_t cdb32_busaddr;
|
||||
u_int sg_count;/* How full ahc_dma_seg is */
|
||||
};
|
||||
|
||||
@ -267,12 +388,11 @@ struct scb {
|
||||
* which only has limited direct access to the DMA FIFO.
|
||||
*/
|
||||
struct target_cmd {
|
||||
u_int8_t initiator_channel;
|
||||
u_int8_t targ_id; /* Target ID we were selected at */
|
||||
u_int8_t identify; /* Identify message */
|
||||
u_int8_t bytes[21];
|
||||
u_int8_t cmd_valid;
|
||||
u_int8_t pad[7];
|
||||
uint8_t scsiid;
|
||||
uint8_t identify; /* Identify message */
|
||||
uint8_t bytes[22];
|
||||
uint8_t cmd_valid;
|
||||
uint8_t pad[7];
|
||||
};
|
||||
|
||||
/*
|
||||
@ -281,10 +401,10 @@ struct target_cmd {
|
||||
*/
|
||||
#define AHC_TMODE_EVENT_BUFFER_SIZE 8
|
||||
struct ahc_tmode_event {
|
||||
u_int8_t initiator_id;
|
||||
u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
|
||||
uint8_t initiator_id;
|
||||
uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
|
||||
#define EVENT_TYPE_BUS_RESET 0xFF
|
||||
u_int8_t event_arg;
|
||||
uint8_t event_arg;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -296,8 +416,8 @@ struct tmode_lstate {
|
||||
struct ccb_hdr_slist accept_tios;
|
||||
struct ccb_hdr_slist immed_notifies;
|
||||
struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
|
||||
u_int8_t event_r_idx;
|
||||
u_int8_t event_w_idx;
|
||||
uint8_t event_r_idx;
|
||||
uint8_t event_w_idx;
|
||||
};
|
||||
|
||||
#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
|
||||
@ -306,14 +426,16 @@ struct tmode_lstate {
|
||||
#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
|
||||
|
||||
struct ahc_transinfo {
|
||||
u_int8_t width;
|
||||
u_int8_t period;
|
||||
u_int8_t offset;
|
||||
u_int8_t ppr_flags;
|
||||
uint8_t protocol_version;
|
||||
uint8_t transport_version;
|
||||
uint8_t width;
|
||||
uint8_t period;
|
||||
uint8_t offset;
|
||||
uint8_t ppr_options;
|
||||
};
|
||||
|
||||
struct ahc_initiator_tinfo {
|
||||
u_int8_t scsirate;
|
||||
uint8_t scsirate;
|
||||
struct ahc_transinfo current;
|
||||
struct ahc_transinfo goal;
|
||||
struct ahc_transinfo user;
|
||||
@ -326,15 +448,15 @@ struct ahc_initiator_tinfo {
|
||||
* are the initiator).
|
||||
*/
|
||||
struct tmode_tstate {
|
||||
struct tmode_lstate* enabled_luns[8];
|
||||
struct tmode_lstate* enabled_luns[64];
|
||||
struct ahc_initiator_tinfo transinfo[16];
|
||||
|
||||
/*
|
||||
* Per initiator state bitmasks.
|
||||
*/
|
||||
u_int16_t ultraenb; /* Using ultra sync rate */
|
||||
u_int16_t discenable; /* Disconnection allowed */
|
||||
u_int16_t tagenable; /* Tagged Queuing allowed */
|
||||
uint16_t ultraenb; /* Using ultra sync rate */
|
||||
uint16_t discenable; /* Disconnection allowed */
|
||||
uint16_t tagenable; /* Tagged Queuing allowed */
|
||||
};
|
||||
|
||||
/*
|
||||
@ -345,7 +467,7 @@ struct seeprom_config {
|
||||
/*
|
||||
* SCSI ID Configuration Flags
|
||||
*/
|
||||
u_int16_t device_flags[16]; /* words 0-15 */
|
||||
uint16_t device_flags[16]; /* words 0-15 */
|
||||
#define CFXFER 0x0007 /* synchronous transfer rate */
|
||||
#define CFSYNCH 0x0008 /* enable synchronous transfer */
|
||||
#define CFDISC 0x0010 /* enable disconnection */
|
||||
@ -355,28 +477,29 @@ struct seeprom_config {
|
||||
#define CFSTART 0x0100 /* send start unit SCSI command */
|
||||
#define CFINCBIOS 0x0200 /* include in BIOS scan */
|
||||
#define CFRNFOUND 0x0400 /* report even if not found */
|
||||
#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */
|
||||
#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
|
||||
#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
|
||||
#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
|
||||
|
||||
/*
|
||||
* BIOS Control Bits
|
||||
*/
|
||||
u_int16_t bios_control; /* word 16 */
|
||||
uint16_t bios_control; /* word 16 */
|
||||
#define CFSUPREM 0x0001 /* support all removeable drives */
|
||||
#define CFSUPREMB 0x0002 /* support removeable boot drives */
|
||||
#define CFBIOSEN 0x0004 /* BIOS enabled */
|
||||
/* UNUSED 0x0008 */
|
||||
#define CFSM2DRV 0x0010 /* support more than two drives */
|
||||
#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
|
||||
/* UNUSED 0x0040 */
|
||||
#define CFSTPWLEVEL 0x0010 /* Termination level control */
|
||||
#define CFEXTEND 0x0080 /* extended translation enabled */
|
||||
#define CFSCAMEN 0x0100 /* SCAM enable */
|
||||
/* UNUSED 0xff00 */
|
||||
|
||||
/*
|
||||
* Host Adapter Control Bits
|
||||
*/
|
||||
u_int16_t adapter_control; /* word 17 */
|
||||
uint16_t adapter_control; /* word 17 */
|
||||
#define CFAUTOTERM 0x0001 /* Perform Auto termination */
|
||||
#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
|
||||
#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
|
||||
@ -385,16 +508,19 @@ struct seeprom_config {
|
||||
#define CFWSTERM 0x0008 /* SCSI high byte termination */
|
||||
#define CFSPARITY 0x0010 /* SCSI parity */
|
||||
#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
|
||||
#define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */
|
||||
#define CFRESETB 0x0040 /* reset SCSI bus at boot */
|
||||
#define CFCLUSTERENB 0x0080 /* Cluster Enable */
|
||||
#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */
|
||||
#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/
|
||||
#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */
|
||||
/* UNUSED 0xf280 */
|
||||
#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
|
||||
#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
|
||||
#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
|
||||
#define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/
|
||||
|
||||
/*
|
||||
* Bus Release, Host Adapter ID
|
||||
*/
|
||||
u_int16_t brtime_id; /* word 18 */
|
||||
uint16_t brtime_id; /* word 18 */
|
||||
#define CFSCSIID 0x000f /* host adapter SCSI ID */
|
||||
/* UNUSED 0x00f0 */
|
||||
#define CFBRTIME 0xff00 /* bus release time */
|
||||
@ -402,20 +528,24 @@ struct seeprom_config {
|
||||
/*
|
||||
* Maximum targets
|
||||
*/
|
||||
u_int16_t max_targets; /* word 19 */
|
||||
uint16_t max_targets; /* word 19 */
|
||||
#define CFMAXTARG 0x00ff /* maximum targets */
|
||||
/* UNUSED 0xff00 */
|
||||
u_int16_t res_1[11]; /* words 20-30 */
|
||||
u_int16_t checksum; /* word 31 */
|
||||
#define CFBOOTLUN 0x0f00 /* Lun to boot from */
|
||||
#define CFBOOTID 0xf000 /* Target to boot from */
|
||||
uint16_t res_1[10]; /* words 20-29 */
|
||||
uint16_t signature; /* Signature == 0x250 */
|
||||
#define CFSIGNATURE 0x250
|
||||
uint16_t checksum; /* word 31 */
|
||||
};
|
||||
|
||||
struct ahc_syncrate {
|
||||
int sxfr_u2;
|
||||
int sxfr;
|
||||
u_int sxfr_u2;
|
||||
u_int sxfr;
|
||||
/* Rates in Ultra mode have bit 8 of sxfr set */
|
||||
#define ULTRA_SXFR 0x100
|
||||
#define ST_SXFR 0x010
|
||||
u_int8_t period; /* Period to send to SCSI target */
|
||||
#define ST_SXFR 0x010 /* Rate Single Transition Only */
|
||||
#define DT_SXFR 0x040 /* Rate Double Transition Only */
|
||||
uint8_t period; /* Period to send to SCSI target */
|
||||
char *rate;
|
||||
};
|
||||
|
||||
@ -454,14 +584,16 @@ struct scb_data {
|
||||
bus_addr_t sense_busaddr;
|
||||
bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
|
||||
SLIST_HEAD(, sg_map_node) sg_maps;
|
||||
u_int8_t numscbs;
|
||||
u_int8_t maxhscbs; /* Number of SCBs on the card */
|
||||
u_int8_t init_level; /*
|
||||
uint8_t numscbs;
|
||||
uint8_t maxhscbs; /* Number of SCBs on the card */
|
||||
uint8_t init_level; /*
|
||||
* How far we've initialized
|
||||
* this structure.
|
||||
*/
|
||||
};
|
||||
|
||||
TAILQ_HEAD(scb_tailq, scb);
|
||||
|
||||
struct ahc_softc {
|
||||
bus_space_tag_t tag;
|
||||
bus_space_handle_t bsh;
|
||||
@ -473,6 +605,23 @@ struct ahc_softc {
|
||||
*/
|
||||
LIST_HEAD(, ccb_hdr) pending_ccbs;
|
||||
|
||||
/*
|
||||
* Counting lock for deferring the release of additional
|
||||
* untagged transactions from the untagged_queues. When
|
||||
* the lock is decremented to 0, all queues in the
|
||||
* untagged_queues array are run.
|
||||
*/
|
||||
u_int untagged_queue_lock;
|
||||
|
||||
/*
|
||||
* Per-target queue of untagged-transactions. The
|
||||
* transaction at the head of the queue is the
|
||||
* currently pending untagged transaction for the
|
||||
* target. The driver only allows a single untagged
|
||||
* transaction per target.
|
||||
*/
|
||||
struct scb_tailq untagged_queues[16];
|
||||
|
||||
/*
|
||||
* Target mode related state kept on a per enabled lun basis.
|
||||
* Targets that are not enabled will have null entries.
|
||||
@ -498,23 +647,18 @@ struct ahc_softc {
|
||||
*/
|
||||
ahc_chip chip;
|
||||
ahc_feature features;
|
||||
ahc_bug bugs;
|
||||
ahc_flag flags;
|
||||
|
||||
/* Values to store in the SEQCTL register for pause and unpause */
|
||||
u_int8_t unpause;
|
||||
u_int8_t pause;
|
||||
uint8_t unpause;
|
||||
uint8_t pause;
|
||||
|
||||
/* Command Queues */
|
||||
u_int8_t qoutfifonext;
|
||||
u_int8_t qinfifonext;
|
||||
u_int8_t *qoutfifo;
|
||||
u_int8_t *qinfifo;
|
||||
|
||||
/*
|
||||
* 256 byte array storing the SCBID of outstanding
|
||||
* untagged SCBs indexed by TCL.
|
||||
*/
|
||||
u_int8_t *untagged_scbs;
|
||||
uint8_t qoutfifonext;
|
||||
uint8_t qinfifonext;
|
||||
uint8_t *qoutfifo;
|
||||
uint8_t *qinfifo;
|
||||
|
||||
/*
|
||||
* Hooks into the XPT.
|
||||
@ -531,11 +675,11 @@ struct ahc_softc {
|
||||
char channel_b;
|
||||
|
||||
/* Initiator Bus ID */
|
||||
u_int8_t our_id;
|
||||
u_int8_t our_id_b;
|
||||
uint8_t our_id;
|
||||
uint8_t our_id_b;
|
||||
|
||||
/* Targets that need negotiation messages */
|
||||
u_int16_t targ_msg_req;
|
||||
uint16_t targ_msg_req;
|
||||
|
||||
/*
|
||||
* PCI error detection and data for running the
|
||||
@ -548,15 +692,15 @@ struct ahc_softc {
|
||||
* Target incoming command FIFO.
|
||||
*/
|
||||
struct target_cmd *targetcmds;
|
||||
u_int8_t tqinfifonext;
|
||||
uint8_t tqinfifonext;
|
||||
|
||||
/*
|
||||
* Incoming and outgoing message handling.
|
||||
*/
|
||||
u_int8_t send_msg_perror;
|
||||
uint8_t send_msg_perror;
|
||||
ahc_msg_type msg_type;
|
||||
u_int8_t msgout_buf[8]; /* Message we are sending */
|
||||
u_int8_t msgin_buf[8]; /* Message we are receiving */
|
||||
uint8_t msgout_buf[8]; /* Message we are sending */
|
||||
uint8_t msgin_buf[8]; /* Message we are receiving */
|
||||
u_int msgout_len; /* Length of message to send */
|
||||
u_int msgout_index; /* Current index in msgout */
|
||||
u_int msgin_index; /* Current index in msgin */
|
||||
@ -579,8 +723,8 @@ struct ahc_softc {
|
||||
/* Initialization level of this data structure */
|
||||
u_int init_level;
|
||||
|
||||
u_int16_t user_discenable;/* Disconnection allowed */
|
||||
u_int16_t user_tagenable;/* Tagged Queuing allowed */
|
||||
uint16_t user_discenable;/* Disconnection allowed */
|
||||
uint16_t user_tagenable;/* Tagged Queuing allowed */
|
||||
};
|
||||
|
||||
struct full_ahc_softc {
|
||||
@ -601,20 +745,6 @@ struct full_ahc_softc {
|
||||
extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */
|
||||
#endif
|
||||
|
||||
char *ahc_name(struct ahc_softc *ahc);
|
||||
|
||||
struct ahc_softc*
|
||||
ahc_alloc(device_t dev, struct resource *regs, int regs_type,
|
||||
int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip,
|
||||
ahc_feature features, ahc_flag flags,
|
||||
struct scb_data *scb_data);
|
||||
int ahc_reset(struct ahc_softc *ahc);
|
||||
void ahc_free(struct ahc_softc *);
|
||||
int ahc_probe_scbs(struct ahc_softc *);
|
||||
int ahc_init(struct ahc_softc *);
|
||||
int ahc_attach(struct ahc_softc *);
|
||||
void ahc_intr(void *arg);
|
||||
|
||||
#define ahc_inb(ahc, port) \
|
||||
bus_space_read_1((ahc)->tag, (ahc)->bsh, port)
|
||||
|
||||
@ -627,4 +757,64 @@ void ahc_intr(void *arg);
|
||||
#define ahc_insb(ahc, port, valp, count) \
|
||||
bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count)
|
||||
|
||||
char *ahc_name(struct ahc_softc *ahc);
|
||||
|
||||
void ahc_init_probe_config(struct ahc_probe_config *config);
|
||||
struct ahc_softc*
|
||||
ahc_alloc(device_t dev, struct resource *regs, int regs_type,
|
||||
int regs_id, bus_dma_tag_t parent_dmat,
|
||||
struct ahc_probe_config *config, struct scb_data *scb_data);
|
||||
int ahc_reset(struct ahc_softc *ahc);
|
||||
void ahc_free(struct ahc_softc *);
|
||||
int ahc_probe_scbs(struct ahc_softc *);
|
||||
int ahc_init(struct ahc_softc *);
|
||||
int ahc_attach(struct ahc_softc *);
|
||||
void ahc_intr(void *arg);
|
||||
static __inline int sequencer_paused(struct ahc_softc *ahc);
|
||||
static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
|
||||
static __inline void pause_sequencer(struct ahc_softc *ahc);
|
||||
static __inline void unpause_sequencer(struct ahc_softc *ahc);
|
||||
|
||||
static __inline void
|
||||
ahc_pause_bug_fix(struct ahc_softc *ahc)
|
||||
{
|
||||
/*
|
||||
* Clear the CIOBUS stretch signal by reading a register that will
|
||||
* set this signal and deassert it. Without this workaround, if
|
||||
* the chip is paused, by an interrupt or manual pause, while
|
||||
* accessing scb ram, then accesses to certain registers will hang
|
||||
* the system (infinite pci retries).
|
||||
*/
|
||||
if ((ahc->features & AHC_ULTRA2) != 0)
|
||||
(void)ahc_inb(ahc, CCSCBCTL);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
sequencer_paused(struct ahc_softc *ahc)
|
||||
{
|
||||
return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
pause_sequencer(struct ahc_softc *ahc)
|
||||
{
|
||||
ahc_outb(ahc, HCNTRL, ahc->pause);
|
||||
|
||||
/*
|
||||
* Since the sequencer can disable pausing in a critical section, we
|
||||
* must loop until it actually stops.
|
||||
*/
|
||||
while (sequencer_paused(ahc) == 0)
|
||||
;
|
||||
|
||||
ahc_pause_bug_fix(ahc);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
unpause_sequencer(struct ahc_softc *ahc)
|
||||
{
|
||||
if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
|
||||
ahc_outb(ahc, HCNTRL, ahc->unpause);
|
||||
}
|
||||
|
||||
#endif /* _AIC7XXX_H_ */
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* the GNU Public License ("GPL").
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
@ -172,6 +172,8 @@ register SCSIID {
|
||||
address 0x005
|
||||
access_mode RW
|
||||
mask TID 0xf0 /* Target ID mask */
|
||||
mask TWIN_TID 0x70
|
||||
bit TWIN_CHNLB 0x80
|
||||
mask OID 0x0f /* Our ID mask */
|
||||
/*
|
||||
* SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
|
||||
@ -704,7 +706,6 @@ register HS_MAILBOX {
|
||||
address 0x086
|
||||
mask HOST_MAILBOX 0xF0
|
||||
mask SEQ_MAILBOX 0x0F
|
||||
mask HOST_REQ_INT 0x10
|
||||
mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
|
||||
}
|
||||
|
||||
@ -746,7 +747,7 @@ register HCNT {
|
||||
|
||||
/*
|
||||
* SCB Pointer (p. 3-49)
|
||||
* Gate one of the four SCBs into the SCBARRAY window.
|
||||
* Gate one of the SCBs into the SCBARRAY window.
|
||||
*/
|
||||
register SCBPTR {
|
||||
address 0x090
|
||||
@ -768,10 +769,10 @@ register INTSTAT {
|
||||
mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
|
||||
mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
|
||||
mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
|
||||
mask UPDATE_TMSG_REQ 0x60|SEQINT /* Update TMSG_REQ values */
|
||||
mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
|
||||
mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
|
||||
mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
|
||||
mask TRACE_POINT 0x90|SEQINT
|
||||
mask TRACEPOINT2 0x90|SEQINT
|
||||
mask HOST_MSG_LOOP 0xa0|SEQINT /*
|
||||
* The bus is ready for the
|
||||
* host to perform another
|
||||
@ -787,11 +788,6 @@ register INTSTAT {
|
||||
* noticed a parity error.
|
||||
*/
|
||||
mask TRACEPOINT 0xd0|SEQINT
|
||||
mask MSGIN_PHASEMIS 0xe0|SEQINT /*
|
||||
* Target changed phase on us
|
||||
* when we were expecting
|
||||
* another msgin byte.
|
||||
*/
|
||||
mask DATA_OVERRUN 0xf0|SEQINT /*
|
||||
* Target attempted to write
|
||||
* beyond the bounds of its
|
||||
@ -962,33 +958,41 @@ scb {
|
||||
address 0x0a0
|
||||
SCB_CONTROL {
|
||||
size 1
|
||||
bit TARGET_SCB 0x80
|
||||
bit DISCENB 0x40
|
||||
bit TAG_ENB 0x20
|
||||
bit MK_MESSAGE 0x10
|
||||
bit ULTRAENB 0x08
|
||||
bit DISCONNECTED 0x04
|
||||
mask SCB_TAG_TYPE 0x03
|
||||
bit TARGET_SCB 0x80
|
||||
bit DISCENB 0x40
|
||||
bit TAG_ENB 0x20
|
||||
bit MK_MESSAGE 0x10
|
||||
bit ULTRAENB 0x08
|
||||
bit DISCONNECTED 0x04
|
||||
mask SCB_TAG_TYPE 0x03
|
||||
}
|
||||
SCB_TCL {
|
||||
SCB_SCSIID {
|
||||
size 1
|
||||
bit SELBUSB 0x08
|
||||
mask TID 0xf0
|
||||
mask LID 0x07
|
||||
bit TWIN_CHNLB 0x80
|
||||
mask TWIN_TID 0x70
|
||||
mask TID 0xf0
|
||||
mask OID 0x0f
|
||||
}
|
||||
SCB_TARGET_STATUS {
|
||||
SCB_LUN {
|
||||
mask LID 0xff
|
||||
size 1
|
||||
}
|
||||
SCB_SGCOUNT {
|
||||
SCB_CDB_LEN {
|
||||
size 1
|
||||
}
|
||||
SCB_SGPTR {
|
||||
SCB_CDB_PTR {
|
||||
size 4
|
||||
alias SCB_RESIDUAL_DATACNT
|
||||
alias SCB_CDB_STORE
|
||||
alias SCB_TARGET_INFO
|
||||
}
|
||||
SCB_RESIDUAL_SGPTR {
|
||||
size 4
|
||||
}
|
||||
SCB_RESID_SGCNT {
|
||||
SCB_SCSI_STATUS {
|
||||
size 1
|
||||
}
|
||||
SCB_RESID_DCNT {
|
||||
SCB_CDB_STORE_PAD {
|
||||
size 3
|
||||
}
|
||||
SCB_DATAPTR {
|
||||
@ -996,48 +1000,41 @@ scb {
|
||||
}
|
||||
SCB_DATACNT {
|
||||
/*
|
||||
* Really only 3 bytes, but padded to make
|
||||
* the kernel's job easier.
|
||||
* The last byte is really the high address bits for
|
||||
* the data address.
|
||||
*/
|
||||
size 4
|
||||
bit SG_LAST_SEG 0x80 /* In the fourth byte */
|
||||
mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
|
||||
}
|
||||
SCB_CMDPTR {
|
||||
alias SCB_TARGET_PHASES
|
||||
bit TARGET_DATA_IN 0x1 /* In the second byte */
|
||||
SCB_SGPTR {
|
||||
size 4
|
||||
}
|
||||
SCB_CMDLEN {
|
||||
alias SCB_INITIATOR_TAG
|
||||
size 1
|
||||
bit SG_RESID_VALID 0x04 /* In the first byte */
|
||||
bit SG_FULL_RESID 0x02 /* In the first byte */
|
||||
bit SG_LIST_NULL 0x01 /* In the first byte */
|
||||
}
|
||||
SCB_TAG {
|
||||
size 1
|
||||
}
|
||||
SCB_NEXT {
|
||||
size 1
|
||||
}
|
||||
SCB_SCSIRATE {
|
||||
size 1
|
||||
}
|
||||
SCB_SCSIOFFSET {
|
||||
size 1
|
||||
}
|
||||
SCB_SPARE {
|
||||
size 3
|
||||
SCB_NEXT {
|
||||
size 1
|
||||
}
|
||||
SCB_CMDSTORE {
|
||||
SCB_64_BTT {
|
||||
size 16
|
||||
}
|
||||
SCB_CMDSTORE_BUSADDR {
|
||||
size 4
|
||||
}
|
||||
SCB_64BYTE_SPARE {
|
||||
size 12
|
||||
SCB_64_SPARE {
|
||||
size 16
|
||||
}
|
||||
}
|
||||
|
||||
const SCB_32BYTE_SIZE 28
|
||||
const SCB_64BYTE_SIZE 48
|
||||
const SCB_32BYTE_SIZE 30 /* Cards supporting 32byte scbs */
|
||||
const SCB_64BYTE_SIZE 32 /* Cards supporting 64byte scbs */
|
||||
|
||||
const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
|
||||
|
||||
@ -1083,7 +1080,7 @@ register CCSGCTL {
|
||||
address 0x0EB
|
||||
bit CCSGDONE 0x80
|
||||
bit CCSGEN 0x08
|
||||
bit FLAG 0x02
|
||||
bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */
|
||||
bit CCSGRESET 0x01
|
||||
}
|
||||
|
||||
@ -1164,14 +1161,23 @@ register DFF_THRSH {
|
||||
mask WR_DFTHRSH_MAX 0x70
|
||||
}
|
||||
|
||||
register SG_CACHEPTR {
|
||||
access_mode RW
|
||||
register SG_CACHE_PRE {
|
||||
access_mode WO
|
||||
address 0x0fc
|
||||
mask SG_USER_DATA 0xfc
|
||||
mask SG_ADDR_MASK 0xf8
|
||||
bit ODD_SEG 0x04
|
||||
bit LAST_SEG 0x02
|
||||
bit LAST_SEG_DONE 0x01
|
||||
}
|
||||
|
||||
register SG_CACHE_SHADOW {
|
||||
access_mode RO
|
||||
address 0x0fc
|
||||
mask SG_ADDR_MASK 0xf8
|
||||
bit ODD_SEG 0x04
|
||||
bit LAST_SEG 0x02
|
||||
bit LAST_SEG_DONE 0x01
|
||||
}
|
||||
/* ---------------------- Scratch RAM Offsets ------------------------- */
|
||||
/* These offsets are either to values that are initialized by the board's
|
||||
* BIOS or are specified by the sequencer code.
|
||||
@ -1193,8 +1199,11 @@ scratch_ram {
|
||||
/*
|
||||
* 1 byte per target starting at this address for configuration values
|
||||
*/
|
||||
TARG_SCSIRATE {
|
||||
alias CMDSIZE_TABLE
|
||||
CMDSIZE_TABLE {
|
||||
alias TARG_SCSIRATE
|
||||
size 8
|
||||
}
|
||||
BUSY_TARGETS {
|
||||
size 16
|
||||
}
|
||||
/*
|
||||
@ -1234,6 +1243,7 @@ scratch_ram {
|
||||
size 1
|
||||
bit IDENTIFY_SEEN 0x80
|
||||
bit SCBPTR_VALID 0x40
|
||||
bit TARGET_CMD_IS_TAGGED 0x40
|
||||
bit DPHASE 0x20
|
||||
/* Target flags */
|
||||
bit TARG_CMD_PENDING 0x10
|
||||
@ -1247,17 +1257,12 @@ scratch_ram {
|
||||
* target/channel/lun of a
|
||||
* reconnecting target
|
||||
*/
|
||||
SAVED_TCL {
|
||||
SAVED_SCSIID {
|
||||
size 1
|
||||
}
|
||||
/* Working value of the number of SG segments left */
|
||||
SG_COUNT {
|
||||
SAVED_LUN {
|
||||
size 1
|
||||
}
|
||||
/* Working value of SG pointer */
|
||||
SG_NEXT {
|
||||
size 4
|
||||
}
|
||||
/*
|
||||
* The last bus phase as seen by the sequencer.
|
||||
*/
|
||||
@ -1304,17 +1309,11 @@ scratch_ram {
|
||||
size 4
|
||||
}
|
||||
/*
|
||||
* Address of the 256 byte array storing the SCBID of outstanding
|
||||
* untagged SCBs indexed by TCL.
|
||||
* Base address of our shared data with the kernel driver in host
|
||||
* memory. This includes the qinfifo, qoutfifo, and target mode
|
||||
* incoming command queue.
|
||||
*/
|
||||
SCBID_ADDR {
|
||||
size 4
|
||||
}
|
||||
/*
|
||||
* Address of the array of command descriptors used to store
|
||||
* information about incoming selections.
|
||||
*/
|
||||
TMODE_CMDADDR {
|
||||
SHARED_DATA_ADDR {
|
||||
size 4
|
||||
}
|
||||
KERNEL_QINPOS {
|
||||
@ -1360,14 +1359,6 @@ scratch_ram {
|
||||
size 1
|
||||
}
|
||||
|
||||
/*
|
||||
* Number of times we have filled the CCSGRAM with prefetched
|
||||
* SG elements.
|
||||
*/
|
||||
PREFETCH_CNT {
|
||||
size 1
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt kernel for a message to this target on
|
||||
* the next transaction. This is usually used for
|
||||
@ -1441,17 +1432,13 @@ scratch_ram {
|
||||
}
|
||||
}
|
||||
|
||||
const TID_SHIFT 4
|
||||
const SCB_LIST_NULL 0xff
|
||||
const TARGET_CMD_CMPLT 0xfe
|
||||
|
||||
const CCSGADDR_MAX 0x80
|
||||
const CCSGRAM_MAXSEGS 16
|
||||
|
||||
/* Offsets into the SCBID array where different data is stored */
|
||||
const QOUTFIFO_OFFSET 0
|
||||
const QINFIFO_OFFSET 1
|
||||
const UNTAGGEDSCB_OFFSET 2
|
||||
|
||||
/* WDTR Message values */
|
||||
const BUS_8_BIT 0x00
|
||||
const BUS_16_BIT 0x01
|
||||
@ -1466,18 +1453,17 @@ const HOST_MSG 0xff
|
||||
/* Target mode command processing constants */
|
||||
const CMD_GROUP_CODE_SHIFT 0x05
|
||||
|
||||
const TCL_TARGET_SHIFT 4
|
||||
|
||||
const STATUS_BUSY 0x08
|
||||
const STATUS_QUEUE_FULL 0x28
|
||||
const STATUS_QUEUE_FULL 0x28
|
||||
const SCB_TARGET_PHASES 0
|
||||
const SCB_TARGET_DATA_DIR 1
|
||||
const SCB_TARGET_STATUS 2
|
||||
const SCB_INITIATOR_TAG 3
|
||||
const TARGET_DATA_IN 1
|
||||
|
||||
/*
|
||||
* Downloaded (kernel inserted) constants
|
||||
*/
|
||||
|
||||
/*
|
||||
* Number of command descriptors in the command descriptor array.
|
||||
* No longer used, but left here as an example for how downloaded
|
||||
* constantants can be defined.
|
||||
const TMODE_NUMCMDS download
|
||||
*/
|
||||
/* Offsets into the SCBID array where different data is stored */
|
||||
const QOUTFIFO_OFFSET download
|
||||
const QINFIFO_OFFSET download
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -89,14 +89,14 @@ static struct seeprom_cmd {
|
||||
int
|
||||
read_seeprom(sd, buf, start_addr, count)
|
||||
struct seeprom_descriptor *sd;
|
||||
u_int16_t *buf;
|
||||
uint16_t *buf;
|
||||
bus_size_t start_addr;
|
||||
bus_size_t count;
|
||||
{
|
||||
int i = 0;
|
||||
u_int k = 0;
|
||||
u_int16_t v;
|
||||
u_int8_t temp;
|
||||
uint16_t v;
|
||||
uint8_t temp;
|
||||
|
||||
/*
|
||||
* Read the requested registers of the seeprom. The loop
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* the GNU Public License ("GPL").
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
@ -52,12 +52,12 @@ struct seeprom_descriptor {
|
||||
bus_size_t sd_status_offset;
|
||||
bus_size_t sd_dataout_offset;
|
||||
seeprom_chip_t sd_chip;
|
||||
u_int16_t sd_MS;
|
||||
u_int16_t sd_RDY;
|
||||
u_int16_t sd_CS;
|
||||
u_int16_t sd_CK;
|
||||
u_int16_t sd_DO;
|
||||
u_int16_t sd_DI;
|
||||
uint16_t sd_MS;
|
||||
uint16_t sd_RDY;
|
||||
uint16_t sd_CS;
|
||||
uint16_t sd_CK;
|
||||
uint16_t sd_DO;
|
||||
uint16_t sd_DI;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -85,7 +85,7 @@ struct seeprom_descriptor {
|
||||
#define SEEPROM_DATA_INB(sd) \
|
||||
bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset)
|
||||
|
||||
int read_seeprom(struct seeprom_descriptor *sd, u_int16_t *buf,
|
||||
int read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
|
||||
bus_size_t start_addr, bus_size_t count);
|
||||
|
||||
#endif /* _KERNEL */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Aic7xxx SCSI host adapter firmware asssembler
|
||||
*
|
||||
* Copyright (c) 1997, 1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -39,7 +42,7 @@
|
||||
|
||||
#include "aicasm.h"
|
||||
#include "aicasm_symbol.h"
|
||||
#include "sequencer.h"
|
||||
#include "aicasm_insformat.h"
|
||||
|
||||
typedef struct patch {
|
||||
STAILQ_ENTRY(patch) links;
|
||||
@ -53,8 +56,8 @@ STAILQ_HEAD(patch_list, patch) patches;
|
||||
|
||||
static void usage(void);
|
||||
static void back_patch(void);
|
||||
static void output_code(FILE *ofile);
|
||||
static void output_listing(FILE *listfile, char *ifilename);
|
||||
static void output_code(void);
|
||||
static void output_listing(char *ifilename);
|
||||
static void dump_scope(scope_t *scope);
|
||||
static void emit_patch(scope_t *scope, int patch);
|
||||
static int check_patch(patch_t **start_patch, int start_instr,
|
||||
@ -238,12 +241,12 @@ main(argc, argv)
|
||||
back_patch();
|
||||
|
||||
if (ofile != NULL)
|
||||
output_code(ofile);
|
||||
output_code();
|
||||
if (regfile != NULL) {
|
||||
symtable_dump(regfile);
|
||||
}
|
||||
if (listfile != NULL)
|
||||
output_listing(listfile, inputfilename);
|
||||
output_listing(inputfilename);
|
||||
}
|
||||
|
||||
stop(NULL, 0);
|
||||
@ -293,8 +296,7 @@ back_patch()
|
||||
}
|
||||
|
||||
static void
|
||||
output_code(ofile)
|
||||
FILE *ofile;
|
||||
output_code()
|
||||
{
|
||||
struct instruction *cur_instr;
|
||||
patch_t *cur_patch;
|
||||
@ -307,16 +309,23 @@ output_code(ofile)
|
||||
* DO NOT EDIT - This file is automatically generated.
|
||||
*/\n");
|
||||
|
||||
fprintf(ofile, "static u_int8_t seqprog[] = {\n");
|
||||
fprintf(ofile, "static uint8_t seqprog[] = {\n");
|
||||
for(cur_instr = seq_program.stqh_first;
|
||||
cur_instr != NULL;
|
||||
cur_instr = cur_instr->links.stqe_next) {
|
||||
|
||||
fprintf(ofile, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x,\n",
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
cur_instr->format.bytes[0],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[3]);
|
||||
#else
|
||||
cur_instr->format.bytes[3],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[0]);
|
||||
#endif
|
||||
instrcount++;
|
||||
}
|
||||
fprintf(ofile, "};\n\n");
|
||||
@ -344,7 +353,7 @@ ahc_patch%d_func(struct ahc_softc *ahc)
|
||||
"typedef int patch_func_t __P((struct ahc_softc *));
|
||||
struct patch {
|
||||
patch_func_t *patch_func;
|
||||
u_int32_t begin :10,
|
||||
uint32_t begin :10,
|
||||
skip_instr :10,
|
||||
skip_patch :12;
|
||||
} patches[] = {\n");
|
||||
@ -422,7 +431,7 @@ emit_patch(scope_t *scope, int patch)
|
||||
}
|
||||
|
||||
void
|
||||
output_listing(FILE *listfile, char *ifilename)
|
||||
output_listing(char *ifilename)
|
||||
{
|
||||
char buf[1024];
|
||||
FILE *ifile;
|
||||
@ -517,10 +526,17 @@ output_listing(FILE *listfile, char *ifilename)
|
||||
line++;
|
||||
}
|
||||
fprintf(listfile, "%03x %02x%02x%02x%02x", instrptr,
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
cur_instr->format.bytes[0],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[3]);
|
||||
#else
|
||||
cur_instr->format.bytes[3],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[0]);
|
||||
#endif
|
||||
fgets(buf, sizeof(buf), ifile);
|
||||
fprintf(listfile, "\t%s", buf);
|
||||
line++;
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Aic7xxx SCSI host adapter firmware asssembler
|
||||
*
|
||||
* Copyright (c) 1997, 1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -39,7 +42,7 @@
|
||||
|
||||
#include "aicasm.h"
|
||||
#include "aicasm_symbol.h"
|
||||
#include "sequencer.h"
|
||||
#include "aicasm_insformat.h"
|
||||
|
||||
typedef struct patch {
|
||||
STAILQ_ENTRY(patch) links;
|
||||
@ -53,8 +56,8 @@ STAILQ_HEAD(patch_list, patch) patches;
|
||||
|
||||
static void usage(void);
|
||||
static void back_patch(void);
|
||||
static void output_code(FILE *ofile);
|
||||
static void output_listing(FILE *listfile, char *ifilename);
|
||||
static void output_code(void);
|
||||
static void output_listing(char *ifilename);
|
||||
static void dump_scope(scope_t *scope);
|
||||
static void emit_patch(scope_t *scope, int patch);
|
||||
static int check_patch(patch_t **start_patch, int start_instr,
|
||||
@ -238,12 +241,12 @@ main(argc, argv)
|
||||
back_patch();
|
||||
|
||||
if (ofile != NULL)
|
||||
output_code(ofile);
|
||||
output_code();
|
||||
if (regfile != NULL) {
|
||||
symtable_dump(regfile);
|
||||
}
|
||||
if (listfile != NULL)
|
||||
output_listing(listfile, inputfilename);
|
||||
output_listing(inputfilename);
|
||||
}
|
||||
|
||||
stop(NULL, 0);
|
||||
@ -293,8 +296,7 @@ back_patch()
|
||||
}
|
||||
|
||||
static void
|
||||
output_code(ofile)
|
||||
FILE *ofile;
|
||||
output_code()
|
||||
{
|
||||
struct instruction *cur_instr;
|
||||
patch_t *cur_patch;
|
||||
@ -307,16 +309,23 @@ output_code(ofile)
|
||||
* DO NOT EDIT - This file is automatically generated.
|
||||
*/\n");
|
||||
|
||||
fprintf(ofile, "static u_int8_t seqprog[] = {\n");
|
||||
fprintf(ofile, "static uint8_t seqprog[] = {\n");
|
||||
for(cur_instr = seq_program.stqh_first;
|
||||
cur_instr != NULL;
|
||||
cur_instr = cur_instr->links.stqe_next) {
|
||||
|
||||
fprintf(ofile, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x,\n",
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
cur_instr->format.bytes[0],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[3]);
|
||||
#else
|
||||
cur_instr->format.bytes[3],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[0]);
|
||||
#endif
|
||||
instrcount++;
|
||||
}
|
||||
fprintf(ofile, "};\n\n");
|
||||
@ -344,7 +353,7 @@ ahc_patch%d_func(struct ahc_softc *ahc)
|
||||
"typedef int patch_func_t __P((struct ahc_softc *));
|
||||
struct patch {
|
||||
patch_func_t *patch_func;
|
||||
u_int32_t begin :10,
|
||||
uint32_t begin :10,
|
||||
skip_instr :10,
|
||||
skip_patch :12;
|
||||
} patches[] = {\n");
|
||||
@ -422,7 +431,7 @@ emit_patch(scope_t *scope, int patch)
|
||||
}
|
||||
|
||||
void
|
||||
output_listing(FILE *listfile, char *ifilename)
|
||||
output_listing(char *ifilename)
|
||||
{
|
||||
char buf[1024];
|
||||
FILE *ifile;
|
||||
@ -517,10 +526,17 @@ output_listing(FILE *listfile, char *ifilename)
|
||||
line++;
|
||||
}
|
||||
fprintf(listfile, "%03x %02x%02x%02x%02x", instrptr,
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
cur_instr->format.bytes[0],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[3]);
|
||||
#else
|
||||
cur_instr->format.bytes[3],
|
||||
cur_instr->format.bytes[2],
|
||||
cur_instr->format.bytes[1],
|
||||
cur_instr->format.bytes[0]);
|
||||
#endif
|
||||
fgets(buf, sizeof(buf), ifile);
|
||||
fprintf(listfile, "\t%s", buf);
|
||||
line++;
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
|
||||
*
|
||||
* Copyright (c) 1997-1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -14,6 +14,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -39,7 +42,7 @@
|
||||
|
||||
#include "aicasm.h"
|
||||
#include "aicasm_symbol.h"
|
||||
#include "sequencer.h"
|
||||
#include "aicasm_insformat.h"
|
||||
|
||||
int yylineno;
|
||||
char *yyfilename;
|
||||
@ -130,7 +133,7 @@ static int is_download_const __P((expression_t *immed));
|
||||
|
||||
%token <value> T_STC T_CLC
|
||||
|
||||
%token <value> T_CMP T_XOR
|
||||
%token <value> T_CMP T_NOT T_XOR
|
||||
|
||||
%token <value> T_TEST T_AND
|
||||
|
||||
@ -551,6 +554,21 @@ reg_symbol:
|
||||
$$.symbol = $1;
|
||||
$$.offset = 0;
|
||||
}
|
||||
| T_SYMBOL '[' T_SYMBOL ']'
|
||||
{
|
||||
process_register(&$1);
|
||||
if ($3->type != CONST) {
|
||||
stop("register offset must be a constant", EX_DATAERR);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
if (($3->info.cinfo->value + 1) > $1->info.rinfo->size) {
|
||||
stop("Accessing offset beyond range of register",
|
||||
EX_DATAERR);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
$$.symbol = $1;
|
||||
$$.offset = $3->info.cinfo->value;
|
||||
}
|
||||
| T_SYMBOL '[' T_NUMBER ']'
|
||||
{
|
||||
process_register(&$1);
|
||||
@ -827,7 +845,7 @@ code:
|
||||
;
|
||||
|
||||
code:
|
||||
T_BMOV destination ',' source ',' immediate ret ';'
|
||||
T_BMOV destination ',' source ',' immediate_or_a ret ';'
|
||||
{
|
||||
format_1_instr(AIC_OP_BMOV, &$2, &$6, &$4, $7);
|
||||
}
|
||||
@ -850,6 +868,16 @@ code:
|
||||
}
|
||||
;
|
||||
|
||||
code:
|
||||
T_NOT destination opt_source ret ';'
|
||||
{
|
||||
expression_t immed;
|
||||
|
||||
make_expression(&immed, 0xff);
|
||||
format_1_instr(AIC_OP_XOR, &$2, &immed, &$3, $4);
|
||||
}
|
||||
;
|
||||
|
||||
code:
|
||||
T_CLR destination ret ';'
|
||||
{
|
||||
@ -1173,7 +1201,7 @@ format_2_instr(opcode, dest, places, src, ret)
|
||||
{
|
||||
struct instruction *instr;
|
||||
struct ins_format2 *f2_instr;
|
||||
u_int8_t shift_control;
|
||||
uint8_t shift_control;
|
||||
|
||||
if (src->symbol == NULL)
|
||||
src = dest;
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* Instruction formats for the sequencer program downloaded to
|
||||
* Aic7xxx SCSI host adapters
|
||||
*
|
||||
* Copyright (c) 1997, 1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -15,7 +15,7 @@
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* the GNU Public License ("GPL").
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
@ -32,38 +32,66 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include <machine/endian.h>
|
||||
|
||||
struct ins_format1 {
|
||||
u_int32_t immediate : 8,
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t immediate : 8,
|
||||
source : 9,
|
||||
destination : 9,
|
||||
ret : 1,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
ret : 1,
|
||||
destination : 9,
|
||||
source : 9,
|
||||
immediate : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ins_format2 {
|
||||
u_int32_t shift_control : 8,
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t shift_control : 8,
|
||||
source : 9,
|
||||
destination : 9,
|
||||
ret : 1,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
ret : 1,
|
||||
destination : 9,
|
||||
source : 9,
|
||||
shift_control : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ins_format3 {
|
||||
u_int32_t immediate : 8,
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t immediate : 8,
|
||||
source : 9,
|
||||
address : 10,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
address : 10,
|
||||
source : 9,
|
||||
immediate : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
union ins_formats {
|
||||
struct ins_format1 format1;
|
||||
struct ins_format2 format2;
|
||||
struct ins_format3 format3;
|
||||
u_int8_t bytes[4];
|
||||
u_int32_t integer;
|
||||
uint8_t bytes[4];
|
||||
uint32_t integer;
|
||||
};
|
||||
struct instruction {
|
||||
union ins_formats format;
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
|
||||
*
|
||||
* Copyright (c) 1997-1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -14,6 +14,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -145,6 +148,7 @@ dec { return T_DEC; }
|
||||
stc { return T_STC; }
|
||||
clc { return T_CLC; }
|
||||
cmp { return T_CMP; }
|
||||
not { return T_NOT; }
|
||||
xor { return T_XOR; }
|
||||
test { return T_TEST;}
|
||||
and { return T_AND; }
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -397,7 +400,7 @@ symtable_dump(ofile)
|
||||
*/\n");
|
||||
while (registers.slh_first != NULL) {
|
||||
symbol_node_t *curnode;
|
||||
u_int8_t value;
|
||||
uint8_t value;
|
||||
char *tab_str;
|
||||
char *tab_str2;
|
||||
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -51,10 +54,10 @@ typedef enum {
|
||||
}amode_t;
|
||||
|
||||
struct reg_info {
|
||||
u_int8_t address;
|
||||
uint8_t address;
|
||||
int size;
|
||||
amode_t mode;
|
||||
u_int8_t valid_bitmask;
|
||||
uint8_t valid_bitmask;
|
||||
int typecheck_masks;
|
||||
};
|
||||
|
||||
@ -62,11 +65,11 @@ typedef SLIST_HEAD(symlist, symbol_node) symlist_t;
|
||||
|
||||
struct mask_info {
|
||||
symlist_t symrefs;
|
||||
u_int8_t mask;
|
||||
uint8_t mask;
|
||||
};
|
||||
|
||||
struct const_info {
|
||||
u_int8_t value;
|
||||
uint8_t value;
|
||||
int define;
|
||||
};
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Parser for the Aic7xxx SCSI Host adapter sequencer assembler.
|
||||
*
|
||||
* Copyright (c) 1997-1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -14,6 +14,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -39,7 +42,7 @@
|
||||
|
||||
#include "aicasm.h"
|
||||
#include "aicasm_symbol.h"
|
||||
#include "sequencer.h"
|
||||
#include "aicasm_insformat.h"
|
||||
|
||||
int yylineno;
|
||||
char *yyfilename;
|
||||
@ -130,7 +133,7 @@ static int is_download_const __P((expression_t *immed));
|
||||
|
||||
%token <value> T_STC T_CLC
|
||||
|
||||
%token <value> T_CMP T_XOR
|
||||
%token <value> T_CMP T_NOT T_XOR
|
||||
|
||||
%token <value> T_TEST T_AND
|
||||
|
||||
@ -551,6 +554,21 @@ reg_symbol:
|
||||
$$.symbol = $1;
|
||||
$$.offset = 0;
|
||||
}
|
||||
| T_SYMBOL '[' T_SYMBOL ']'
|
||||
{
|
||||
process_register(&$1);
|
||||
if ($3->type != CONST) {
|
||||
stop("register offset must be a constant", EX_DATAERR);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
if (($3->info.cinfo->value + 1) > $1->info.rinfo->size) {
|
||||
stop("Accessing offset beyond range of register",
|
||||
EX_DATAERR);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
$$.symbol = $1;
|
||||
$$.offset = $3->info.cinfo->value;
|
||||
}
|
||||
| T_SYMBOL '[' T_NUMBER ']'
|
||||
{
|
||||
process_register(&$1);
|
||||
@ -827,7 +845,7 @@ code:
|
||||
;
|
||||
|
||||
code:
|
||||
T_BMOV destination ',' source ',' immediate ret ';'
|
||||
T_BMOV destination ',' source ',' immediate_or_a ret ';'
|
||||
{
|
||||
format_1_instr(AIC_OP_BMOV, &$2, &$6, &$4, $7);
|
||||
}
|
||||
@ -850,6 +868,16 @@ code:
|
||||
}
|
||||
;
|
||||
|
||||
code:
|
||||
T_NOT destination opt_source ret ';'
|
||||
{
|
||||
expression_t immed;
|
||||
|
||||
make_expression(&immed, 0xff);
|
||||
format_1_instr(AIC_OP_XOR, &$2, &immed, &$3, $4);
|
||||
}
|
||||
;
|
||||
|
||||
code:
|
||||
T_CLR destination ret ';'
|
||||
{
|
||||
@ -1173,7 +1201,7 @@ format_2_instr(opcode, dest, places, src, ret)
|
||||
{
|
||||
struct instruction *instr;
|
||||
struct ins_format2 *f2_instr;
|
||||
u_int8_t shift_control;
|
||||
uint8_t shift_control;
|
||||
|
||||
if (src->symbol == NULL)
|
||||
src = dest;
|
||||
|
||||
123
sys/dev/aic7xxx/aicasm_insformat.h
Normal file
123
sys/dev/aic7xxx/aicasm_insformat.h
Normal file
@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Instruction formats for the sequencer program downloaded to
|
||||
* Aic7xxx SCSI host adapters
|
||||
*
|
||||
* Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include <machine/endian.h>
|
||||
|
||||
struct ins_format1 {
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t immediate : 8,
|
||||
source : 9,
|
||||
destination : 9,
|
||||
ret : 1,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
ret : 1,
|
||||
destination : 9,
|
||||
source : 9,
|
||||
immediate : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ins_format2 {
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t shift_control : 8,
|
||||
source : 9,
|
||||
destination : 9,
|
||||
ret : 1,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
ret : 1,
|
||||
destination : 9,
|
||||
source : 9,
|
||||
shift_control : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ins_format3 {
|
||||
#if BYTE_ORDER == LITTLE_ENDIAN
|
||||
uint32_t immediate : 8,
|
||||
source : 9,
|
||||
address : 10,
|
||||
opcode : 4,
|
||||
parity : 1;
|
||||
#else
|
||||
uint32_t parity : 1,
|
||||
opcode : 4,
|
||||
address : 10,
|
||||
source : 9,
|
||||
immediate : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
union ins_formats {
|
||||
struct ins_format1 format1;
|
||||
struct ins_format2 format2;
|
||||
struct ins_format3 format3;
|
||||
uint8_t bytes[4];
|
||||
uint32_t integer;
|
||||
};
|
||||
struct instruction {
|
||||
union ins_formats format;
|
||||
u_int srcline;
|
||||
struct symbol *patch_label;
|
||||
STAILQ_ENTRY(instruction) links;
|
||||
};
|
||||
|
||||
#define AIC_OP_OR 0x0
|
||||
#define AIC_OP_AND 0x1
|
||||
#define AIC_OP_XOR 0x2
|
||||
#define AIC_OP_ADD 0x3
|
||||
#define AIC_OP_ADC 0x4
|
||||
#define AIC_OP_ROL 0x5
|
||||
#define AIC_OP_BMOV 0x6
|
||||
|
||||
#define AIC_OP_JMP 0x8
|
||||
#define AIC_OP_JC 0x9
|
||||
#define AIC_OP_JNC 0xa
|
||||
#define AIC_OP_CALL 0xb
|
||||
#define AIC_OP_JNE 0xc
|
||||
#define AIC_OP_JNZ 0xd
|
||||
#define AIC_OP_JE 0xe
|
||||
#define AIC_OP_JZ 0xf
|
||||
|
||||
/* Pseudo Ops */
|
||||
#define AIC_OP_SHL 0x10
|
||||
#define AIC_OP_SHR 0x20
|
||||
#define AIC_OP_ROR 0x30
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler.
|
||||
*
|
||||
* Copyright (c) 1997-1998 Justin T. Gibbs.
|
||||
* Copyright (c) 1997, 1998 Justin T. Gibbs.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -14,6 +14,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -145,6 +148,7 @@ dec { return T_DEC; }
|
||||
stc { return T_STC; }
|
||||
clc { return T_CLC; }
|
||||
cmp { return T_CMP; }
|
||||
not { return T_NOT; }
|
||||
xor { return T_XOR; }
|
||||
test { return T_TEST;}
|
||||
and { return T_AND; }
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -397,7 +400,7 @@ symtable_dump(ofile)
|
||||
*/\n");
|
||||
while (registers.slh_first != NULL) {
|
||||
symbol_node_t *curnode;
|
||||
u_int8_t value;
|
||||
uint8_t value;
|
||||
char *tab_str;
|
||||
char *tab_str2;
|
||||
|
||||
|
||||
@ -13,6 +13,9 @@
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU Public License ("GPL").
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
@ -51,10 +54,10 @@ typedef enum {
|
||||
}amode_t;
|
||||
|
||||
struct reg_info {
|
||||
u_int8_t address;
|
||||
uint8_t address;
|
||||
int size;
|
||||
amode_t mode;
|
||||
u_int8_t valid_bitmask;
|
||||
uint8_t valid_bitmask;
|
||||
int typecheck_masks;
|
||||
};
|
||||
|
||||
@ -62,11 +65,11 @@ typedef SLIST_HEAD(symlist, symbol_node) symlist_t;
|
||||
|
||||
struct mask_info {
|
||||
symlist_t symrefs;
|
||||
u_int8_t mask;
|
||||
uint8_t mask;
|
||||
};
|
||||
|
||||
struct const_info {
|
||||
u_int8_t value;
|
||||
uint8_t value;
|
||||
int define;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user