PMC: remove now orphaned PMC for INTEL XScale processors.
Support for XScale architecture has been deleted in FreeBSD 13.
This commit is contained in:
Michal Meloun
Michal Meloun
parent
f5baf8bb12
commit
aa76f0c397
@ -93,7 +93,6 @@ MAN+= pmc.tsc.3
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MAN+= pmc.ucf.3
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MAN+= pmc.westmere.3
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MAN+= pmc.westmereuc.3
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MAN+= pmc.xscale.3
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MLINKS+= \
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pmc_allocate.3 pmc_release.3 \
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@ -59,10 +59,6 @@ static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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#endif
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#if defined(__arm__)
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#if defined(__XSCALE__)
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static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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#endif
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static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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#endif
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@ -140,7 +136,6 @@ struct pmc_class_descr {
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PMC_CLASSDEP_TABLE(iaf, IAF);
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PMC_CLASSDEP_TABLE(k8, K8);
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PMC_CLASSDEP_TABLE(xscale, XSCALE);
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PMC_CLASSDEP_TABLE(armv7, ARMV7);
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PMC_CLASSDEP_TABLE(armv8, ARMV8);
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PMC_CLASSDEP_TABLE(beri, BERI);
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@ -193,7 +188,6 @@ static const struct pmc_event_descr cortex_a76_event_table[] =
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}
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PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
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PMC_MDEP_TABLE(beri, BERI, PMC_CLASS_SOFT, PMC_CLASS_BERI);
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PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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@ -234,9 +228,6 @@ PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
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PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
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#endif
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#if defined(__arm__)
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#if defined(__XSCALE__)
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PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
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#endif
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PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
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PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
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#endif
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@ -770,29 +761,6 @@ soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
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}
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#if defined(__arm__)
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#if defined(__XSCALE__)
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static struct pmc_event_alias xscale_aliases[] = {
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EV_ALIAS("branches", "BRANCH_RETIRED"),
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EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
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EV_ALIAS("dc-misses", "DC_MISS"),
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EV_ALIAS("ic-misses", "IC_MISS"),
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EV_ALIAS("instructions", "INSTR_RETIRED"),
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EV_ALIAS(NULL, NULL)
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};
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static int
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xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
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struct pmc_op_pmcallocate *pmc_config __unused)
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{
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switch (pe) {
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default:
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break;
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}
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return (0);
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}
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#endif
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static struct pmc_event_alias cortex_a8_aliases[] = {
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EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
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EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
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@ -1264,10 +1232,6 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
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ev = k8_event_table;
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count = PMC_EVENT_TABLE_SIZE(k8);
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break;
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case PMC_CLASS_XSCALE:
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ev = xscale_event_table;
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count = PMC_EVENT_TABLE_SIZE(xscale);
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break;
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case PMC_CLASS_ARMV7:
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switch (cpu_info.pm_cputype) {
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default:
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@ -1521,12 +1485,6 @@ pmc_init(void)
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PMC_MDEP_INIT(generic);
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break;
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#if defined(__arm__)
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#if defined(__XSCALE__)
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case PMC_CPU_INTEL_XSCALE:
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PMC_MDEP_INIT(xscale);
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pmc_class_table[n] = &xscale_class_table_descr;
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break;
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#endif
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case PMC_CPU_ARMV7_CORTEX_A8:
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PMC_MDEP_INIT(cortex_a8);
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pmc_class_table[n] = &cortex_a8_class_table_descr;
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@ -1667,9 +1625,7 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
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if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
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ev = k8_event_table;
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evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
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} else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
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ev = xscale_event_table;
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evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
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} else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
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switch (cpu) {
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case PMC_CPU_ARMV7_CORTEX_A8:
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@ -23,7 +23,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd April 6, 2017
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.Dd December 12, 2020
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.Dt PMC 3
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.Os
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.Sh NAME
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@ -545,7 +545,6 @@ API is
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.Xr pmc.tsc 3 ,
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.Xr pmc.westmere 3 ,
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.Xr pmc.westmereuc 3 ,
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.Xr pmc.xscale 3 ,
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.Xr pmc_allocate 3 ,
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.Xr pmc_attach 3 ,
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.Xr pmc_capabilities 3 ,
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@ -1,156 +0,0 @@
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.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 23, 2009
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.Dt PMC.XSCALE 3
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.Os
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.Sh NAME
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.Nm pmc.xscale
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.Nd measurement events for
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.Tn Intel
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.Tn XScale
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel XScale
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CPUs are ARM CPUs based on the ARMv5e core.
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.Pp
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Second generation cores have 2 counters, while third generation cores
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have 4 counters.
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Third generation cores also have an increased number of PMC events.
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.Pp
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.Tn Intel XScale
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PMCs are documented in
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.Rs
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.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
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.%D May 2007
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.Re
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.Ss Event Specifiers (Programmable PMCs)
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.Tn Intel XScale
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programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li IC_FETCH
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External memory fetch due to L1 instruction cache miss.
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.It Li IC_MISS
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Instruction cache or TLB miss.
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.It Li DATA_DEPENDENCY_STALLED
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A data dependency stalled
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.It Li ITLB_MISS
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Instruction TLB miss.
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.It Li DTLB_MISS
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Data TLB miss.
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.It Li BRANCH_RETIRED
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Branch instruction retired (executed).
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.It Li BRANCH_MISPRED
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Branch mispredicted.
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.It Li INSTR_RETIRED
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Instructions retired (executed).
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.It Li DC_FULL_CYCLE
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L1 data cache buffer full stall.
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Event occurs on every cycle the
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condition is present.
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.It Li DC_FULL_CONTIG
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L1 data cache buffer full stall.
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Event occurs once for each contiguous sequence of this type of stall.
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.It Li DC_ACCESS
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L1 data cache access, not including cache operations.
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.It Li DC_MISS
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L1 data cache miss, not including cache operations.
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.It Li DC_WRITEBACK
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L1 data cache write-back.
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Occurs for each cache line that's written back from the cache.
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.It Li PC_CHANGE
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Software changed the program counter.
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.It Li BRANCH_RETIRED_ALL
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Branch instruction retired (executed).
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This event counts all branch instructions, indirect or direct.
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.It Li INSTR_CYCLE
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Count the number of microarchitecture cycles each instruction requires
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to issue.
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.It Li CP_STALL
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Coprocessor stalled the instruction pipeline.
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.It Li PC_CHANGE_ALL
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Software changed the program counter (includes exceptions).
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.It Li PIPELINE_FLUSH
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Pipeline flushes due to mispredictions or exceptions.
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.It Li BACKEND_STALL
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Backend stalled the instruction pipeline.
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.It Li MULTIPLIER_USE
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Multiplier used.
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.It Li MULTIPLIER_STALLED
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Multiplier stalled the instruction pipeline.
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.It Li DATA_CACHE_STALLED
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Data cache stalled the instruction pipeline.
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.It Li L2_CACHE_REQ
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L2 cache request, not including cache operations.
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.It Li L2_CACHE_MISS
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L2 cache miss, not including cache operations.
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.It Li ADDRESS_BUS_TRANS
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Address bus transaction.
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.It Li SELF_ADDRESS_BUS_TRANS
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Self initiated address bus transaction.
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.It Li DATA_BUS_TRANS
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Data bus transaction.
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.El
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.Ss Event Name Aliases
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
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.It Em Alias Ta Em Event
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.It Li branches Ta Li BRANCH_RETIRED
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.It Li branch-mispredicts Ta Li BRANCH_MISPRED
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.It Li dc-misses Ta Li DC_MISS
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.It Li ic-misses Ta Li IC_MISS
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.It Li instructions Ta Li INSTR_RETIRED
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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Intel XScale support first appeared in
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.Fx 9.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Lb libpmc
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library was written by
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.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
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.Pp
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Intel XScale support was added by
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.An Rui Paulo Aq Mt rpaulo@FreeBSD.org .
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.Sh CAVEATS
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The Intel XScale code does not yet support sampling.
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@ -31,15 +31,12 @@
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#ifndef _MACHINE_PMC_MDEP_H_
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#define _MACHINE_PMC_MDEP_H_
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#define PMC_MDEP_CLASS_INDEX_XSCALE 1
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#define PMC_MDEP_CLASS_INDEX_ARMV7 1
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/*
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* On the ARM platform we support the following PMCs.
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*
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* XSCALE Intel XScale processors
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* ARMV7 ARM Cortex-A processors
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*/
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#include <dev/hwpmc/hwpmc_xscale.h>
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#include <dev/hwpmc/hwpmc_armv7.h>
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union pmc_md_op_pmcallocate {
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@ -52,7 +49,6 @@ union pmc_md_op_pmcallocate {
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#ifdef _KERNEL
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union pmc_md_pmc {
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struct pmc_md_xscale_pmc pm_xscale;
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struct pmc_md_armv7_pmc pm_armv7;
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};
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@ -80,8 +76,6 @@ union pmc_md_pmc {
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/*
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* Prototypes
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*/
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struct pmc_mdep *pmc_xscale_initialize(void);
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void pmc_xscale_finalize(struct pmc_mdep *_md);
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struct pmc_mdep *pmc_armv7_initialize(void);
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void pmc_armv7_finalize(struct pmc_mdep *_md);
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#endif /* _KERNEL */
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@ -1,72 +0,0 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_HWPMC_XSCALE_H_
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#define _DEV_HWPMC_XSCALE_H_
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#define XSCALE_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
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PMC_CAP_THRESHOLD | PMC_CAP_READ | \
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PMC_CAP_WRITE | PMC_CAP_INVERT | \
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PMC_CAP_QUALIFIER)
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#define XSCALE_PMNC_ENABLE 0x01 /* Enable all Counters */
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#define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */
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#define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */
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#define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */
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#define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */
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#define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */
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#define XSCALE_INTEN_PMN1 0x04 /* Enable PMN1 Interrupts */
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#define XSCALE_INTEN_PMN2 0x08 /* Enable PMN2 Interrupts */
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#define XSCALE_INTEN_PMN3 0x10 /* Enable PMN3 Interrupts */
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#define XSCALE_EVTSEL_EVT0_MASK 0x000000ff
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#define XSCALE_EVTSEL_EVT1_MASK 0x0000ff00
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#define XSCALE_EVTSEL_EVT2_MASK 0x00ff0000
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#define XSCALE_EVTSEL_EVT3_MASK 0xff000000
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#define XSCALE_FLAG_CCNT_OVERFLOW 0x01
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#define XSCALE_FLAG_PMN0_OVERFLOW 0x02
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#define XSCALE_FLAG_PMN1_OVERFLOW 0x04
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#define XSCALE_FLAG_PMN2_OVERFLOW 0x08
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#define XSCALE_FLAG_PMN3_OVERFLOW 0x10
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#define XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R))
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#define XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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struct pmc_md_xscale_pmc {
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uint32_t pm_xscale_evsel;
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};
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_XSCALE_H_ */
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@ -227,52 +227,6 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
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__PMC_EV(UCP, EVENT_0CH_08H_M) \
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__PMC_EV(UCP, EVENT_0CH_08H_S) \
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/*
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* Intel XScale events from:
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*
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* Intel XScale Core Developer's Manual
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* January, 2004, #27347302
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*
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* 3rd Generation Intel XScale Microarchitecture
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* Developer's Manual
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* May 2007, #31628302
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*
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* First 14 events are for 1st and 2nd Generation Intel XScale cores. The
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* remaining are available only on 3rd Generation Intel XScale cores.
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*/
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#define __PMC_EV_XSCALE() \
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__PMC_EV(XSCALE, IC_FETCH) \
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__PMC_EV(XSCALE, IC_MISS) \
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__PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \
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__PMC_EV(XSCALE, ITLB_MISS) \
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__PMC_EV(XSCALE, DTLB_MISS) \
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__PMC_EV(XSCALE, BRANCH_RETIRED) \
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__PMC_EV(XSCALE, BRANCH_MISPRED) \
|
||||
__PMC_EV(XSCALE, INSTR_RETIRED) \
|
||||
__PMC_EV(XSCALE, DC_FULL_CYCLE) \
|
||||
__PMC_EV(XSCALE, DC_FULL_CONTIG) \
|
||||
__PMC_EV(XSCALE, DC_ACCESS) \
|
||||
__PMC_EV(XSCALE, DC_MISS) \
|
||||
__PMC_EV(XSCALE, DC_WRITEBACK) \
|
||||
__PMC_EV(XSCALE, PC_CHANGE) \
|
||||
__PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \
|
||||
__PMC_EV(XSCALE, INSTR_CYCLE) \
|
||||
__PMC_EV(XSCALE, CP_STALL) \
|
||||
__PMC_EV(XSCALE, PC_CHANGE_ALL) \
|
||||
__PMC_EV(XSCALE, PIPELINE_FLUSH) \
|
||||
__PMC_EV(XSCALE, BACKEND_STALL) \
|
||||
__PMC_EV(XSCALE, MULTIPLIER_USE) \
|
||||
__PMC_EV(XSCALE, MULTIPLIER_STALLED) \
|
||||
__PMC_EV(XSCALE, DATA_CACHE_STALLED) \
|
||||
__PMC_EV(XSCALE, L2_CACHE_REQ) \
|
||||
__PMC_EV(XSCALE, L2_CACHE_MISS) \
|
||||
__PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \
|
||||
__PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \
|
||||
__PMC_EV(XSCALE, DATA_BUS_TRANS)
|
||||
|
||||
#define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH
|
||||
#define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS
|
||||
|
||||
/*
|
||||
* ARMv7 Events
|
||||
*/
|
||||
@ -1899,7 +1853,7 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
|
||||
* 0x11000 0x0080 INTEL Pentium 4 events
|
||||
* 0x11080 0x0080 INTEL Pentium MMX events
|
||||
* 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
|
||||
* 0x11200 0x00FF INTEL XScale events
|
||||
* 0x11200 0x00FF free (was INTEL XScale events)
|
||||
* 0x11300 0x00FF MIPS 24K events
|
||||
* 0x11400 0x00FF Octeon events
|
||||
* 0x11500 0x00FF MIPS 74K events
|
||||
@ -1921,8 +1875,6 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
|
||||
__PMC_EV_K7() \
|
||||
__PMC_EV_BLOCK(K8, 0x2080) \
|
||||
__PMC_EV_K8() \
|
||||
__PMC_EV_BLOCK(XSCALE, 0x11200) \
|
||||
__PMC_EV_XSCALE() \
|
||||
__PMC_EV_BLOCK(MIPS24K, 0x11300) \
|
||||
__PMC_EV_MIPS24K() \
|
||||
__PMC_EV_BLOCK(OCTEON, 0x11400) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user