PMC: remove now orphaned PMC for INTEL XScale processors.

Support for XScale architecture has been deleted in FreeBSD 13.
This commit is contained in:
Michal Meloun 2020-12-25 11:41:34 +01:00 committed by Michal Meloun
parent f5baf8bb12
commit aa76f0c397
7 changed files with 3 additions and 331 deletions

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@ -93,7 +93,6 @@ MAN+= pmc.tsc.3
MAN+= pmc.ucf.3 MAN+= pmc.ucf.3
MAN+= pmc.westmere.3 MAN+= pmc.westmere.3
MAN+= pmc.westmereuc.3 MAN+= pmc.westmereuc.3
MAN+= pmc.xscale.3
MLINKS+= \ MLINKS+= \
pmc_allocate.3 pmc_release.3 \ pmc_allocate.3 pmc_release.3 \

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@ -59,10 +59,6 @@ static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
struct pmc_op_pmcallocate *_pmc_config); struct pmc_op_pmcallocate *_pmc_config);
#endif #endif
#if defined(__arm__) #if defined(__arm__)
#if defined(__XSCALE__)
static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
struct pmc_op_pmcallocate *_pmc_config);
#endif
static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
struct pmc_op_pmcallocate *_pmc_config); struct pmc_op_pmcallocate *_pmc_config);
#endif #endif
@ -140,7 +136,6 @@ struct pmc_class_descr {
PMC_CLASSDEP_TABLE(iaf, IAF); PMC_CLASSDEP_TABLE(iaf, IAF);
PMC_CLASSDEP_TABLE(k8, K8); PMC_CLASSDEP_TABLE(k8, K8);
PMC_CLASSDEP_TABLE(xscale, XSCALE);
PMC_CLASSDEP_TABLE(armv7, ARMV7); PMC_CLASSDEP_TABLE(armv7, ARMV7);
PMC_CLASSDEP_TABLE(armv8, ARMV8); PMC_CLASSDEP_TABLE(armv8, ARMV8);
PMC_CLASSDEP_TABLE(beri, BERI); PMC_CLASSDEP_TABLE(beri, BERI);
@ -193,7 +188,6 @@ static const struct pmc_event_descr cortex_a76_event_table[] =
} }
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
PMC_MDEP_TABLE(beri, BERI, PMC_CLASS_SOFT, PMC_CLASS_BERI); PMC_MDEP_TABLE(beri, BERI, PMC_CLASS_SOFT, PMC_CLASS_BERI);
PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
@ -234,9 +228,6 @@ PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
#endif #endif
#if defined(__arm__) #if defined(__arm__)
#if defined(__XSCALE__)
PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale);
#endif
PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7); PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
#endif #endif
@ -770,29 +761,6 @@ soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
} }
#if defined(__arm__) #if defined(__arm__)
#if defined(__XSCALE__)
static struct pmc_event_alias xscale_aliases[] = {
EV_ALIAS("branches", "BRANCH_RETIRED"),
EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
EV_ALIAS("dc-misses", "DC_MISS"),
EV_ALIAS("ic-misses", "IC_MISS"),
EV_ALIAS("instructions", "INSTR_RETIRED"),
EV_ALIAS(NULL, NULL)
};
static int
xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
struct pmc_op_pmcallocate *pmc_config __unused)
{
switch (pe) {
default:
break;
}
return (0);
}
#endif
static struct pmc_event_alias cortex_a8_aliases[] = { static struct pmc_event_alias cortex_a8_aliases[] = {
EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
@ -1264,10 +1232,6 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
ev = k8_event_table; ev = k8_event_table;
count = PMC_EVENT_TABLE_SIZE(k8); count = PMC_EVENT_TABLE_SIZE(k8);
break; break;
case PMC_CLASS_XSCALE:
ev = xscale_event_table;
count = PMC_EVENT_TABLE_SIZE(xscale);
break;
case PMC_CLASS_ARMV7: case PMC_CLASS_ARMV7:
switch (cpu_info.pm_cputype) { switch (cpu_info.pm_cputype) {
default: default:
@ -1521,12 +1485,6 @@ pmc_init(void)
PMC_MDEP_INIT(generic); PMC_MDEP_INIT(generic);
break; break;
#if defined(__arm__) #if defined(__arm__)
#if defined(__XSCALE__)
case PMC_CPU_INTEL_XSCALE:
PMC_MDEP_INIT(xscale);
pmc_class_table[n] = &xscale_class_table_descr;
break;
#endif
case PMC_CPU_ARMV7_CORTEX_A8: case PMC_CPU_ARMV7_CORTEX_A8:
PMC_MDEP_INIT(cortex_a8); PMC_MDEP_INIT(cortex_a8);
pmc_class_table[n] = &cortex_a8_class_table_descr; pmc_class_table[n] = &cortex_a8_class_table_descr;
@ -1667,9 +1625,7 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
ev = k8_event_table; ev = k8_event_table;
evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
} else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) {
ev = xscale_event_table;
evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale);
} else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
switch (cpu) { switch (cpu) {
case PMC_CPU_ARMV7_CORTEX_A8: case PMC_CPU_ARMV7_CORTEX_A8:

View File

@ -23,7 +23,7 @@
.\" .\"
.\" $FreeBSD$ .\" $FreeBSD$
.\" .\"
.Dd April 6, 2017 .Dd December 12, 2020
.Dt PMC 3 .Dt PMC 3
.Os .Os
.Sh NAME .Sh NAME
@ -545,7 +545,6 @@ API is
.Xr pmc.tsc 3 , .Xr pmc.tsc 3 ,
.Xr pmc.westmere 3 , .Xr pmc.westmere 3 ,
.Xr pmc.westmereuc 3 , .Xr pmc.westmereuc 3 ,
.Xr pmc.xscale 3 ,
.Xr pmc_allocate 3 , .Xr pmc_allocate 3 ,
.Xr pmc_attach 3 , .Xr pmc_attach 3 ,
.Xr pmc_capabilities 3 , .Xr pmc_capabilities 3 ,

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@ -1,156 +0,0 @@
.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd December 23, 2009
.Dt PMC.XSCALE 3
.Os
.Sh NAME
.Nm pmc.xscale
.Nd measurement events for
.Tn Intel
.Tn XScale
family CPUs
.Sh LIBRARY
.Lb libpmc
.Sh SYNOPSIS
.In pmc.h
.Sh DESCRIPTION
.Tn Intel XScale
CPUs are ARM CPUs based on the ARMv5e core.
.Pp
Second generation cores have 2 counters, while third generation cores
have 4 counters.
Third generation cores also have an increased number of PMC events.
.Pp
.Tn Intel XScale
PMCs are documented in
.Rs
.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
.%D May 2007
.Re
.Ss Event Specifiers (Programmable PMCs)
.Tn Intel XScale
programmable PMCs support the following events:
.Bl -tag -width indent
.It Li IC_FETCH
External memory fetch due to L1 instruction cache miss.
.It Li IC_MISS
Instruction cache or TLB miss.
.It Li DATA_DEPENDENCY_STALLED
A data dependency stalled
.It Li ITLB_MISS
Instruction TLB miss.
.It Li DTLB_MISS
Data TLB miss.
.It Li BRANCH_RETIRED
Branch instruction retired (executed).
.It Li BRANCH_MISPRED
Branch mispredicted.
.It Li INSTR_RETIRED
Instructions retired (executed).
.It Li DC_FULL_CYCLE
L1 data cache buffer full stall.
Event occurs on every cycle the
condition is present.
.It Li DC_FULL_CONTIG
L1 data cache buffer full stall.
Event occurs once for each contiguous sequence of this type of stall.
.It Li DC_ACCESS
L1 data cache access, not including cache operations.
.It Li DC_MISS
L1 data cache miss, not including cache operations.
.It Li DC_WRITEBACK
L1 data cache write-back.
Occurs for each cache line that's written back from the cache.
.It Li PC_CHANGE
Software changed the program counter.
.It Li BRANCH_RETIRED_ALL
Branch instruction retired (executed).
This event counts all branch instructions, indirect or direct.
.It Li INSTR_CYCLE
Count the number of microarchitecture cycles each instruction requires
to issue.
.It Li CP_STALL
Coprocessor stalled the instruction pipeline.
.It Li PC_CHANGE_ALL
Software changed the program counter (includes exceptions).
.It Li PIPELINE_FLUSH
Pipeline flushes due to mispredictions or exceptions.
.It Li BACKEND_STALL
Backend stalled the instruction pipeline.
.It Li MULTIPLIER_USE
Multiplier used.
.It Li MULTIPLIER_STALLED
Multiplier stalled the instruction pipeline.
.It Li DATA_CACHE_STALLED
Data cache stalled the instruction pipeline.
.It Li L2_CACHE_REQ
L2 cache request, not including cache operations.
.It Li L2_CACHE_MISS
L2 cache miss, not including cache operations.
.It Li ADDRESS_BUS_TRANS
Address bus transaction.
.It Li SELF_ADDRESS_BUS_TRANS
Self initiated address bus transaction.
.It Li DATA_BUS_TRANS
Data bus transaction.
.El
.Ss Event Name Aliases
The following table shows the mapping between the PMC-independent
aliases supported by
.Lb libpmc
and the underlying hardware events used.
.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
.It Em Alias Ta Em Event
.It Li branches Ta Li BRANCH_RETIRED
.It Li branch-mispredicts Ta Li BRANCH_MISPRED
.It Li dc-misses Ta Li DC_MISS
.It Li ic-misses Ta Li IC_MISS
.It Li instructions Ta Li INSTR_RETIRED
.El
.Sh SEE ALSO
.Xr pmc 3 ,
.Xr pmc.soft 3 ,
.Xr pmc_cpuinfo 3 ,
.Xr pmclog 3 ,
.Xr hwpmc 4
.Sh HISTORY
The
.Nm pmc
library first appeared in
.Fx 6.0 .
Intel XScale support first appeared in
.Fx 9.0 .
.Sh AUTHORS
.An -nosplit
The
.Lb libpmc
library was written by
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
.Pp
Intel XScale support was added by
.An Rui Paulo Aq Mt rpaulo@FreeBSD.org .
.Sh CAVEATS
The Intel XScale code does not yet support sampling.

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@ -31,15 +31,12 @@
#ifndef _MACHINE_PMC_MDEP_H_ #ifndef _MACHINE_PMC_MDEP_H_
#define _MACHINE_PMC_MDEP_H_ #define _MACHINE_PMC_MDEP_H_
#define PMC_MDEP_CLASS_INDEX_XSCALE 1
#define PMC_MDEP_CLASS_INDEX_ARMV7 1 #define PMC_MDEP_CLASS_INDEX_ARMV7 1
/* /*
* On the ARM platform we support the following PMCs. * On the ARM platform we support the following PMCs.
* *
* XSCALE Intel XScale processors
* ARMV7 ARM Cortex-A processors * ARMV7 ARM Cortex-A processors
*/ */
#include <dev/hwpmc/hwpmc_xscale.h>
#include <dev/hwpmc/hwpmc_armv7.h> #include <dev/hwpmc/hwpmc_armv7.h>
union pmc_md_op_pmcallocate { union pmc_md_op_pmcallocate {
@ -52,7 +49,6 @@ union pmc_md_op_pmcallocate {
#ifdef _KERNEL #ifdef _KERNEL
union pmc_md_pmc { union pmc_md_pmc {
struct pmc_md_xscale_pmc pm_xscale;
struct pmc_md_armv7_pmc pm_armv7; struct pmc_md_armv7_pmc pm_armv7;
}; };
@ -80,8 +76,6 @@ union pmc_md_pmc {
/* /*
* Prototypes * Prototypes
*/ */
struct pmc_mdep *pmc_xscale_initialize(void);
void pmc_xscale_finalize(struct pmc_mdep *_md);
struct pmc_mdep *pmc_armv7_initialize(void); struct pmc_mdep *pmc_armv7_initialize(void);
void pmc_armv7_finalize(struct pmc_mdep *_md); void pmc_armv7_finalize(struct pmc_mdep *_md);
#endif /* _KERNEL */ #endif /* _KERNEL */

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@ -1,72 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DEV_HWPMC_XSCALE_H_
#define _DEV_HWPMC_XSCALE_H_
#define XSCALE_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
PMC_CAP_THRESHOLD | PMC_CAP_READ | \
PMC_CAP_WRITE | PMC_CAP_INVERT | \
PMC_CAP_QUALIFIER)
#define XSCALE_PMNC_ENABLE 0x01 /* Enable all Counters */
#define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */
#define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */
#define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */
#define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */
#define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */
#define XSCALE_INTEN_PMN1 0x04 /* Enable PMN1 Interrupts */
#define XSCALE_INTEN_PMN2 0x08 /* Enable PMN2 Interrupts */
#define XSCALE_INTEN_PMN3 0x10 /* Enable PMN3 Interrupts */
#define XSCALE_EVTSEL_EVT0_MASK 0x000000ff
#define XSCALE_EVTSEL_EVT1_MASK 0x0000ff00
#define XSCALE_EVTSEL_EVT2_MASK 0x00ff0000
#define XSCALE_EVTSEL_EVT3_MASK 0xff000000
#define XSCALE_FLAG_CCNT_OVERFLOW 0x01
#define XSCALE_FLAG_PMN0_OVERFLOW 0x02
#define XSCALE_FLAG_PMN1_OVERFLOW 0x04
#define XSCALE_FLAG_PMN2_OVERFLOW 0x08
#define XSCALE_FLAG_PMN3_OVERFLOW 0x10
#define XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R))
#define XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
#ifdef _KERNEL
/* MD extension for 'struct pmc' */
struct pmc_md_xscale_pmc {
uint32_t pm_xscale_evsel;
};
#endif /* _KERNEL */
#endif /* _DEV_HWPMC_XSCALE_H_ */

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@ -227,52 +227,6 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
__PMC_EV(UCP, EVENT_0CH_08H_M) \ __PMC_EV(UCP, EVENT_0CH_08H_M) \
__PMC_EV(UCP, EVENT_0CH_08H_S) \ __PMC_EV(UCP, EVENT_0CH_08H_S) \
/*
* Intel XScale events from:
*
* Intel XScale Core Developer's Manual
* January, 2004, #27347302
*
* 3rd Generation Intel XScale Microarchitecture
* Developer's Manual
* May 2007, #31628302
*
* First 14 events are for 1st and 2nd Generation Intel XScale cores. The
* remaining are available only on 3rd Generation Intel XScale cores.
*/
#define __PMC_EV_XSCALE() \
__PMC_EV(XSCALE, IC_FETCH) \
__PMC_EV(XSCALE, IC_MISS) \
__PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \
__PMC_EV(XSCALE, ITLB_MISS) \
__PMC_EV(XSCALE, DTLB_MISS) \
__PMC_EV(XSCALE, BRANCH_RETIRED) \
__PMC_EV(XSCALE, BRANCH_MISPRED) \
__PMC_EV(XSCALE, INSTR_RETIRED) \
__PMC_EV(XSCALE, DC_FULL_CYCLE) \
__PMC_EV(XSCALE, DC_FULL_CONTIG) \
__PMC_EV(XSCALE, DC_ACCESS) \
__PMC_EV(XSCALE, DC_MISS) \
__PMC_EV(XSCALE, DC_WRITEBACK) \
__PMC_EV(XSCALE, PC_CHANGE) \
__PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \
__PMC_EV(XSCALE, INSTR_CYCLE) \
__PMC_EV(XSCALE, CP_STALL) \
__PMC_EV(XSCALE, PC_CHANGE_ALL) \
__PMC_EV(XSCALE, PIPELINE_FLUSH) \
__PMC_EV(XSCALE, BACKEND_STALL) \
__PMC_EV(XSCALE, MULTIPLIER_USE) \
__PMC_EV(XSCALE, MULTIPLIER_STALLED) \
__PMC_EV(XSCALE, DATA_CACHE_STALLED) \
__PMC_EV(XSCALE, L2_CACHE_REQ) \
__PMC_EV(XSCALE, L2_CACHE_MISS) \
__PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \
__PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \
__PMC_EV(XSCALE, DATA_BUS_TRANS)
#define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH
#define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS
/* /*
* ARMv7 Events * ARMv7 Events
*/ */
@ -1899,7 +1853,7 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
* 0x11000 0x0080 INTEL Pentium 4 events * 0x11000 0x0080 INTEL Pentium 4 events
* 0x11080 0x0080 INTEL Pentium MMX events * 0x11080 0x0080 INTEL Pentium MMX events
* 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
* 0x11200 0x00FF INTEL XScale events * 0x11200 0x00FF free (was INTEL XScale events)
* 0x11300 0x00FF MIPS 24K events * 0x11300 0x00FF MIPS 24K events
* 0x11400 0x00FF Octeon events * 0x11400 0x00FF Octeon events
* 0x11500 0x00FF MIPS 74K events * 0x11500 0x00FF MIPS 74K events
@ -1921,8 +1875,6 @@ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
__PMC_EV_K7() \ __PMC_EV_K7() \
__PMC_EV_BLOCK(K8, 0x2080) \ __PMC_EV_BLOCK(K8, 0x2080) \
__PMC_EV_K8() \ __PMC_EV_K8() \
__PMC_EV_BLOCK(XSCALE, 0x11200) \
__PMC_EV_XSCALE() \
__PMC_EV_BLOCK(MIPS24K, 0x11300) \ __PMC_EV_BLOCK(MIPS24K, 0x11300) \
__PMC_EV_MIPS24K() \ __PMC_EV_MIPS24K() \
__PMC_EV_BLOCK(OCTEON, 0x11400) \ __PMC_EV_BLOCK(OCTEON, 0x11400) \