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Add some sysctl reporting for most pci_pci bridges. We now report

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domain, pribus (the primary bus, eg the bus that this chip is on),
secbus (the secondary bus, eg the bus immediately behind this chip)
and subbus (the number of the highest bus behind this chip).
Normally, this information is reported via bootverbose parameters, but
that's hard to use for debugging in some cases.

This adds reading of pribus to make this happen.  In addition, change
the narrow types to u_int to allow for easier reporting via sysctl for
domain, secbus and subbus.  This should have no effect, but if it
does, please let me know.
This commit is contained in:
Warner Losh 2008-08-16 20:18:40 +00:00
parent 9c95bc1c1c
commit abf07f13fd
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=181789
2 changed files with 21 additions and 3 deletions
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17
sys/dev/pci/pci_pci.c
View File

@ -139,6 +139,8 @@ pcib_attach_common(device_t dev)
{ {
struct pcib_softc *sc; struct pcib_softc *sc;
uint8_t iolow; uint8_t iolow;
struct sysctl_ctx_list *sctx;
struct sysctl_oid *soid;
sc = device_get_softc(dev); sc = device_get_softc(dev);
sc->dev = dev; sc->dev = dev;
@ -148,12 +150,27 @@ pcib_attach_common(device_t dev)
*/ */
sc->command = pci_read_config(dev, PCIR_COMMAND, 1); sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
sc->domain = pci_get_domain(dev); sc->domain = pci_get_domain(dev);
sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
/*
* Setup sysctl reporting nodes
*/
sctx = device_get_sysctl_ctx(dev);
soid = device_get_sysctl_tree(dev);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
CTLFLAG_RD, &sc->domain, 0, "Domain number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
/* /*
* Determine current I/O decode. * Determine current I/O decode.
*/ */

7
sys/dev/pci/pcib_private.h
View File

@ -48,9 +48,10 @@ struct pcib_softc
#define PCIB_SUBTRACTIVE 0x1 #define PCIB_SUBTRACTIVE 0x1
#define PCIB_DISABLE_MSI 0x2 #define PCIB_DISABLE_MSI 0x2
uint16_t command; /* command register */ uint16_t command; /* command register */
uint32_t domain; /* domain number */ u_int domain; /* domain number */
uint8_t secbus; /* secondary bus number */ u_int pribus; /* primary bus number */
uint8_t subbus; /* subordinate bus number */ u_int secbus; /* secondary bus number */
u_int subbus; /* subordinate bus number */
pci_addr_t pmembase; /* base address of prefetchable memory */ pci_addr_t pmembase; /* base address of prefetchable memory */
pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
pci_addr_t membase; /* base address of memory window */ pci_addr_t membase; /* base address of memory window */