bcm2838_pci.c: Respect DMA limits of controller.
Fixes for Raspberry Pi 4B PCIe / USB: - Pass through a DMA tag for the controller. - In theory the controller can access the lower 3 GB, but testing found that unreliable. OpenBSD also restricts DMA to the lowest 960 MiB. - Rename some constants to be a bit more meaningful. Submitted by: Robert Crowston, crowston at protonmail.com Reviewed by: mkarels, outside reviewers Differential Revision: https://reviews.freebsd.org/D26344
This commit is contained in:
Mike Karels
parent
33fa4ac54f
commit
ac89220b05
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=365677
@ -57,9 +57,6 @@ __FBSDID("$FreeBSD$");
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#include "pcib_if.h"
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#include "msi_if.h"
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extern struct bus_space memmap_bus;
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#define BUS_SPACE_3G_MAXADDR 0xc0000000
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#define PCI_ID_VAL3 0x43c
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#define CLASS_SHIFT 0x10
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#define SUBCLASS_SHIFT 0x8
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@ -69,18 +66,18 @@ extern struct bus_space memmap_bus;
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#define BRIDGE_DISABLE_FLAG 0x1
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#define BRIDGE_RESET_FLAG 0x2
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#define REG_BRIDGE_SERDES_MODE 0x4204
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#define REG_BRIDGE_CONFIG 0x4008
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#define REG_BRIDGE_MEM_WINDOW_LOW 0x4034
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#define REG_BRIDGE_MEM_WINDOW_HIGH 0x4038
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#define REG_BRIDGE_MEM_WINDOW_1 0x403c
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#define REG_DMA_CONFIG 0x4008
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#define REG_DMA_WINDOW_LOW 0x4034
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#define REG_DMA_WINDOW_HIGH 0x4038
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#define REG_DMA_WINDOW_1 0x403c
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#define REG_BRIDGE_GISB_WINDOW 0x402c
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#define REG_BRIDGE_STATE 0x4068
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#define REG_BRIDGE_LINK_STATE 0x00bc
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#define REG_BRIDGE_BUS_WINDOW_LOW 0x400c
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#define REG_BRIDGE_BUS_WINDOW_HIGH 0x4010
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#define REG_BRIDGE_CPU_WINDOW_LOW 0x4070
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#define REG_BRIDGE_CPU_WINDOW_START_HIGH 0x4080
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#define REG_BRIDGE_CPU_WINDOW_END_HIGH 0x4084
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#define REG_BUS_WINDOW_LOW 0x400c
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#define REG_BUS_WINDOW_HIGH 0x4010
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#define REG_CPU_WINDOW_LOW 0x4070
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#define REG_CPU_WINDOW_START_HIGH 0x4080
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#define REG_CPU_WINDOW_END_HIGH 0x4084
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#define REG_MSI_ADDR_LOW 0x4044
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#define REG_MSI_ADDR_HIGH 0x4048
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@ -95,12 +92,27 @@ extern struct bus_space memmap_bus;
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#define REG_EP_CONFIG_DATA 0x8000
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/*
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* These values were obtained from runtime inspection of a Linux system using a
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* JTAG. The very limited documentation I have obtained from Broadcom does not
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* explain how to compute them.
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* The system memory controller can address up to 16 GiB of physical memory
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* (although at time of writing the largest memory size available for purchase
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* is 8 GiB). However, the system DMA controller is capable of accessing only a
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* limited portion of the address space. Worse, the PCI-e controller has further
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* constraints for DMA, and those limitations are not wholly clear to the
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* author. NetBSD and Linux allow DMA on the lower 3 GiB of the physical memory,
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* but experimentation shows DMA performed above 960 MiB results in data
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* corruption with this driver. The limit of 960 MiB is taken from OpenBSD, but
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* apparently that value was chosen for satisfying a constraint of an unrelated
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* peripheral.
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*
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* Whatever the true maximum address, 960 MiB works.
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*/
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#define REG_VALUE_4GB_WINDOW 0x11
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#define REG_VALUE_4GB_CONFIG 0x88003000
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#define DMA_HIGH_LIMIT 0x3c000000
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#define MAX_MEMORY_LOG2 0x21
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#define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf)
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#define REG_VALUE_DMA_WINDOW_HIGH 0x0
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#define DMA_WINDOW_ENABLE 0x3000
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#define REG_VALUE_DMA_WINDOW_CONFIG \
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(((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE)
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#define REG_VALUE_MSI_CONFIG 0xffe06540
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struct bcm_pcib_irqsrc {
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@ -112,6 +124,7 @@ struct bcm_pcib_irqsrc {
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struct bcm_pcib_softc {
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struct generic_pcie_fdt_softc base;
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device_t dev;
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bus_dma_tag_t dmat;
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struct mtx config_mtx;
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struct mtx msi_mtx;
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struct resource *msi_irq_res;
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@ -142,6 +155,15 @@ bcm_pcib_probe(device_t dev)
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return (BUS_PROBE_DEFAULT);
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}
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static bus_dma_tag_t
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bcm_pcib_get_dma_tag(device_t dev, device_t child)
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{
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struct bcm_pcib_softc *sc;
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sc = device_get_softc(dev);
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return (sc->dmat);
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}
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static void
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bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val)
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{
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@ -614,6 +636,24 @@ bcm_pcib_attach(device_t dev)
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sc = device_get_softc(dev);
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sc->dev = dev;
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/*
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* This tag will be used in preference to the one created in
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* pci_host_generic.c.
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*/
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error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
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1, 0, /* alignment, bounds */
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DMA_HIGH_LIMIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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DMA_HIGH_LIMIT, /* maxsize */
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BUS_SPACE_UNRESTRICTED, /* nsegments */
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DMA_HIGH_LIMIT, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->dmat);
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if (error)
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return (error);
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error = pci_host_generic_setup_fdt(dev);
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if (error)
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return (error);
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@ -632,17 +672,14 @@ bcm_pcib_attach(device_t dev)
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/*
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* Set PCI->CPU memory window. This encodes the inbound window showing
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* up to 4 GiB of system memory to the controller, with zero offset.
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* Thus, from the perspective of a device on the PCI-E bus, there is a
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* 1:1 map from PCI-E bus addresses to system memory addresses. However,
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* a hardware limitation means that the controller can only perform DMA
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* on the lower 3 GiB of system memory.
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* the system memory to the controller.
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*/
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bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_LOW, REG_VALUE_4GB_WINDOW);
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bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_HIGH, 0);
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bcm_pcib_set_reg(sc, REG_BRIDGE_CONFIG, REG_VALUE_4GB_CONFIG);
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bcm_pcib_set_reg(sc, REG_DMA_WINDOW_LOW, REG_VALUE_DMA_WINDOW_LOW);
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bcm_pcib_set_reg(sc, REG_DMA_WINDOW_HIGH, REG_VALUE_DMA_WINDOW_HIGH);
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bcm_pcib_set_reg(sc, REG_DMA_CONFIG, REG_VALUE_DMA_WINDOW_CONFIG);
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bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0);
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bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_1, 0);
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bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0);
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bcm_pcib_enable_controller(sc);
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@ -682,14 +719,14 @@ bcm_pcib_attach(device_t dev)
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phys_base = sc->base.base.ranges[0].phys_base;
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size = sc->base.base.ranges[0].size;
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bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_LOW, pci_base & 0xffffffff);
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bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_HIGH, pci_base >> 32);
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bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff);
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bcm_pcib_set_reg(sc, REG_BUS_WINDOW_HIGH, pci_base >> 32);
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bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_LOW,
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bcm_pcib_set_reg(sc, REG_CPU_WINDOW_LOW,
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encode_cpu_window_low(phys_base, size));
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bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_START_HIGH,
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bcm_pcib_set_reg(sc, REG_CPU_WINDOW_START_HIGH,
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encode_cpu_window_start_high(phys_base));
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bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_END_HIGH,
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bcm_pcib_set_reg(sc, REG_CPU_WINDOW_END_HIGH,
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encode_cpu_window_end_high(phys_base, size));
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/*
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@ -718,6 +755,9 @@ bcm_pcib_attach(device_t dev)
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* Device method table.
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*/
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static device_method_t bcm_pcib_methods[] = {
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/* Bus interface. */
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DEVMETHOD(bus_get_dma_tag, bcm_pcib_get_dma_tag),
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/* Device interface. */
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DEVMETHOD(device_probe, bcm_pcib_probe),
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DEVMETHOD(device_attach, bcm_pcib_attach),
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@ -739,3 +779,4 @@ DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods,
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static devclass_t bcm_pcib_devclass;
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DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, bcm_pcib_devclass, 0, 0);
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