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Properly serialize the global shootdown with the instruction

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stream of the local processor. Also explicitly invalidate
the ALAT. This is done on the other CPUs in the coherence
domain by virtue of the ptc.ga instruction, but does not
apply to the local CPU.
This commit is contained in:
Marcel Moolenaar 2011-06-17 04:26:03 +00:00
parent ff13f23f84
commit acd1d4d28e
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=223170
2 changed files with 15 additions and 2 deletions
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4
sys/ia64/ia64/pmap.c
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@ -559,10 +559,14 @@ pmap_invalidate_page(vm_offset_t va)
} while (sem != tag);
ia64_ptc_ga(va, PAGE_SHIFT << 2);
ia64_mf();
ia64_srlz_i();
/* PTC.G leave exclusive */
atomic_store_rel_long(&pmap_ptc_g_sem, 0);
ia64_invala();
intr_restore(is);
critical_exit();
}

13
sys/ia64/include/ia64_cpu.h
View File

@ -266,7 +266,7 @@ ia64_ptc_e(uint64_t v)
static __inline void
ia64_ptc_g(uint64_t va, uint64_t log2size)
{
__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
__asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size));
}
/*
@ -275,7 +275,7 @@ ia64_ptc_g(uint64_t va, uint64_t log2size)
static __inline void
ia64_ptc_ga(uint64_t va, uint64_t log2size)
{
__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
__asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size));
}
/*
@ -287,6 +287,15 @@ ia64_ptc_l(uint64_t va, uint64_t log2size)
__asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
}
/*
* Invalidate the ALAT on the local processor.
*/
static __inline void
ia64_invala(void)
{
__asm __volatile("invala;;");
}
/*
* Unordered memory load.
*/