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Another overhaul of the CPSW driver for BeagleBone

Browse Source 
Major changes:
  * Finally tracked down the flow control setting that
    seems to have been causing TX stalls and watchdog timeouts
  * RX and TX paths now share a lot more code
  * TX interrupt is no longer used; we instead GC finished
    tx queue entries at the bottom of the start routine.
  * TX start now queues fragmented packets directly; it only
    invokes defrag() for occasional very fragmented packets.
  * "sysctl dev.cpsw" dumps controller statistics and queue counts
  * Host Error Interrupt will give extensive debugging information
    if the controller chokes on the queued data.
This commit is contained in:
Tim Kientzle 2013-02-03 01:08:01 +00:00
parent 7e7a9efdb5
commit ae6aefaf57
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=246276
3 changed files with 1782 additions and 1097 deletions
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2720
sys/arm/ti/cpsw/if_cpsw.c
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24
sys/arm/ti/cpsw/if_cpswreg.h
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@ -34,8 +34,11 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
#define CPSW_PORT_OFFSET 0x0100
#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
@ -84,10 +87,14 @@
#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
#define CPSW_SL_OFFSET 0x0D80
#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
#define MDIO_OFFSET 0x1000
@ -109,5 +116,22 @@
#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
#define CPSW_CPPI_RAM_OFFSET 0x2000
#define CPSW_CPPI_RAM_SIZE 0x2000
#define CPDMA_BD_SOP (1<<15)
#define CPDMA_BD_EOP (1<<14)
#define CPDMA_BD_OWNER (1<<13)
#define CPDMA_BD_EOQ (1<<12)
#define CPDMA_BD_TDOWNCMPLT (1<<11)
#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
struct cpsw_cpdma_bd {
volatile uint32_t next;
volatile uint32_t bufptr;
volatile uint16_t buflen;
volatile uint16_t bufoff;
volatile uint16_t pktlen;
volatile uint16_t flags;
};
#endif /*_IF_CPSWREG_H */

135
sys/arm/ti/cpsw/if_cpswvar.h
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@ -35,105 +35,90 @@
#define CPSW_MIIBUS_RETRIES 5
#define CPSW_MIIBUS_DELAY 1000
#define CPSW_MAX_TX_BUFFERS 128
#define CPSW_MAX_RX_BUFFERS 128
#define CPSW_MAX_ALE_ENTRIES 1024
#define CPSW_SYSCTL_COUNT 34
struct cpsw_slot {
uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
bus_dmamap_t dmamap;
struct mbuf *mbuf;
int index;
STAILQ_ENTRY(cpsw_slot) next;
};
STAILQ_HEAD(cpsw_queue, cpsw_slot);
STAILQ_HEAD(cpsw_slots, cpsw_slot);
struct cpsw_queue {
struct mtx lock;
int running;
struct cpsw_slots active;
struct cpsw_slots avail;
uint32_t queue_adds; /* total bufs added */
uint32_t queue_removes; /* total bufs removed */
uint32_t queue_removes_at_last_tick; /* Used by watchdog */
int queue_slots;
int active_queue_len;
int max_active_queue_len;
int avail_queue_len;
int max_avail_queue_len;
int longest_chain; /* Largest # segments in a single packet. */
int hdp_offset;
};
struct cpsw_softc {
struct ifnet *ifp;
phandle_t node;
device_t dev;
struct bintime attach_uptime; /* system uptime when attach happened. */
struct bintime init_uptime; /* system uptime when init happened. */
/* TODO: We should set up a child structure for each port;
store mac, phy information, etc, in that structure. */
uint8_t mac_addr[ETHER_ADDR_LEN];
device_t miibus;
struct mii_data *mii;
struct mtx tx_lock; /* transmitter lock */
struct mtx rx_lock; /* receiver lock */
struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
/* We expect 1 memory resource and 4 interrupts from the device tree. */
struct resource *res[1 + CPSW_INTR_COUNT];
/* Interrupts get recorded here as we initialize them. */
/* Interrupt teardown just walks this list. */
struct {
struct resource *res;
void *ih_cookie;
const char *description;
} interrupts[CPSW_INTR_COUNT];
int interrupt_count;
uint32_t cpsw_if_flags;
int cpsw_media_status;
struct callout wd_callout;
int tx_wd_timer;
struct {
int resets;
int timer;
struct callout callout;
} watchdog;
bus_dma_tag_t mbuf_dtag;
/* RX buffer tracking */
int rx_running;
struct cpsw_queue rx_active;
struct cpsw_queue rx_avail;
struct cpsw_slot _rx_slots[CPSW_MAX_RX_BUFFERS];
/* An mbuf full of nulls for TX padding. */
bus_dmamap_t null_mbuf_dmamap;
struct mbuf *null_mbuf;
bus_addr_t null_mbuf_paddr;
/* TX buffer tracking. */
int tx_running;
struct cpsw_queue tx_active;
struct cpsw_queue tx_avail;
struct cpsw_slot _tx_slots[CPSW_MAX_TX_BUFFERS];
/* RX and TX buffer tracking */
struct cpsw_queue rx, tx;
/* Statistics */
uint32_t tx_enqueues; /* total TX bufs added to queue */
uint32_t tx_retires; /* total TX bufs removed from queue */
uint32_t tx_retires_at_last_tick; /* used for watchdog */
/* Note: tx_queued != tx_enqueues - tx_retires
At driver reset, packets can be discarded
from TX queue without being retired. */
int tx_queued; /* Current bufs in TX queue */
int tx_max_queued;
/* 64-bit versions of 32-bit hardware statistics counters */
uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
/* CPPI STATERAM has 512 slots for building TX/RX queues. */
/* TODO: Size here supposedly varies with different versions
of the controller. Check DaVinci specs and find a good
way to adjust this. One option is to have a separate
Device Tree parameter for number slots; another option
is to calculate it from the memory size in the device tree. */
struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
struct cpsw_slots avail;
};
#define CPDMA_BD_SOP (1<<15)
#define CPDMA_BD_EOP (1<<14)
#define CPDMA_BD_OWNER (1<<13)
#define CPDMA_BD_EOQ (1<<12)
#define CPDMA_BD_TDOWNCMPLT (1<<11)
#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
struct cpsw_cpdma_bd {
volatile uint32_t next;
volatile uint32_t bufptr;
volatile uint16_t buflen;
volatile uint16_t bufoff;
volatile uint16_t pktlen;
volatile uint16_t flags;
};
/* Read/Write macros */
#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
#define cpsw_cpdma_txbd_offset(i) \
(CPSW_CPPI_RAM_OFFSET + ((i)*16))
#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
vtophys(rman_get_start(sc->res[0])))
#define cpsw_cpdma_read_txbd(i, val) \
bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
#define cpsw_cpdma_write_txbd(i, val) \
bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
#define cpsw_cpdma_write_txbd_next(i, val) \
bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
#define cpsw_cpdma_read_txbd_flags(i) \
bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
#define cpsw_cpdma_rxbd_offset(i) \
(CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
vtophys(rman_get_start(sc->res[0])))
#define cpsw_cpdma_read_rxbd(i, val) \
bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
#define cpsw_cpdma_write_rxbd(i, val) \
bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
#define cpsw_cpdma_write_rxbd_next(i, val) \
bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
#define cpsw_cpdma_read_rxbd_flags(i) \
bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
#endif /*_IF_CPSWVAR_H */