Another overhaul of the CPSW driver for BeagleBone
Major changes: * Finally tracked down the flow control setting that seems to have been causing TX stalls and watchdog timeouts * RX and TX paths now share a lot more code * TX interrupt is no longer used; we instead GC finished tx queue entries at the bottom of the start routine. * TX start now queues fragmented packets directly; it only invokes defrag() for occasional very fragmented packets. * "sysctl dev.cpsw" dumps controller statistics and queue counts * Host Error Interrupt will give extensive debugging information if the controller chokes on the queued data.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=246276
File diff suppressed because it is too large
Load Diff
@ -34,8 +34,11 @@
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#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
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#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
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#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
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#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
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#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
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#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
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#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
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#define CPSW_PORT_OFFSET 0x0100
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#define CPSW_PORT_OFFSET 0x0100
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#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
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#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
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#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
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#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
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#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
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#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
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#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
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#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
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@ -84,10 +87,14 @@
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#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
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#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
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#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
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#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
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/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
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#define CPSW_SL_OFFSET 0x0D80
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#define CPSW_SL_OFFSET 0x0D80
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#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
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#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
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#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
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#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
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#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
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#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
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#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
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#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
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#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
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#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
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#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
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#define MDIO_OFFSET 0x1000
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#define MDIO_OFFSET 0x1000
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@ -109,5 +116,22 @@
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#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
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#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
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#define CPSW_CPPI_RAM_OFFSET 0x2000
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#define CPSW_CPPI_RAM_OFFSET 0x2000
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#define CPSW_CPPI_RAM_SIZE 0x2000
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#define CPDMA_BD_SOP (1<<15)
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#define CPDMA_BD_EOP (1<<14)
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#define CPDMA_BD_OWNER (1<<13)
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#define CPDMA_BD_EOQ (1<<12)
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#define CPDMA_BD_TDOWNCMPLT (1<<11)
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#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
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struct cpsw_cpdma_bd {
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volatile uint32_t next;
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volatile uint32_t bufptr;
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volatile uint16_t buflen;
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volatile uint16_t bufoff;
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volatile uint16_t pktlen;
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volatile uint16_t flags;
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};
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#endif /*_IF_CPSWREG_H */
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#endif /*_IF_CPSWREG_H */
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@ -35,105 +35,90 @@
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#define CPSW_MIIBUS_RETRIES 5
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#define CPSW_MIIBUS_RETRIES 5
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#define CPSW_MIIBUS_DELAY 1000
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#define CPSW_MIIBUS_DELAY 1000
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#define CPSW_MAX_TX_BUFFERS 128
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#define CPSW_MAX_RX_BUFFERS 128
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#define CPSW_MAX_ALE_ENTRIES 1024
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#define CPSW_MAX_ALE_ENTRIES 1024
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#define CPSW_SYSCTL_COUNT 34
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struct cpsw_slot {
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struct cpsw_slot {
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uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
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bus_dmamap_t dmamap;
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bus_dmamap_t dmamap;
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struct mbuf *mbuf;
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struct mbuf *mbuf;
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int index;
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STAILQ_ENTRY(cpsw_slot) next;
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STAILQ_ENTRY(cpsw_slot) next;
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};
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};
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STAILQ_HEAD(cpsw_queue, cpsw_slot);
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STAILQ_HEAD(cpsw_slots, cpsw_slot);
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struct cpsw_queue {
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struct mtx lock;
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int running;
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struct cpsw_slots active;
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struct cpsw_slots avail;
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uint32_t queue_adds; /* total bufs added */
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uint32_t queue_removes; /* total bufs removed */
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uint32_t queue_removes_at_last_tick; /* Used by watchdog */
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int queue_slots;
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int active_queue_len;
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int max_active_queue_len;
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int avail_queue_len;
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int max_avail_queue_len;
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int longest_chain; /* Largest # segments in a single packet. */
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int hdp_offset;
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};
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struct cpsw_softc {
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struct cpsw_softc {
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struct ifnet *ifp;
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struct ifnet *ifp;
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phandle_t node;
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phandle_t node;
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device_t dev;
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device_t dev;
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struct bintime attach_uptime; /* system uptime when attach happened. */
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struct bintime init_uptime; /* system uptime when init happened. */
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/* TODO: We should set up a child structure for each port;
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store mac, phy information, etc, in that structure. */
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint8_t mac_addr[ETHER_ADDR_LEN];
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device_t miibus;
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device_t miibus;
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struct mii_data *mii;
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struct mii_data *mii;
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struct mtx tx_lock; /* transmitter lock */
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/* We expect 1 memory resource and 4 interrupts from the device tree. */
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struct mtx rx_lock; /* receiver lock */
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struct resource *res[1 + CPSW_INTR_COUNT];
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struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */
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void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */
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/* Interrupts get recorded here as we initialize them. */
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/* Interrupt teardown just walks this list. */
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struct {
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struct resource *res;
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void *ih_cookie;
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const char *description;
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} interrupts[CPSW_INTR_COUNT];
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int interrupt_count;
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uint32_t cpsw_if_flags;
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uint32_t cpsw_if_flags;
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int cpsw_media_status;
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int cpsw_media_status;
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struct callout wd_callout;
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struct {
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int tx_wd_timer;
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int resets;
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int timer;
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struct callout callout;
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} watchdog;
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bus_dma_tag_t mbuf_dtag;
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bus_dma_tag_t mbuf_dtag;
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/* RX buffer tracking */
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/* An mbuf full of nulls for TX padding. */
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int rx_running;
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bus_dmamap_t null_mbuf_dmamap;
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struct cpsw_queue rx_active;
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struct mbuf *null_mbuf;
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struct cpsw_queue rx_avail;
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bus_addr_t null_mbuf_paddr;
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struct cpsw_slot _rx_slots[CPSW_MAX_RX_BUFFERS];
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/* TX buffer tracking. */
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/* RX and TX buffer tracking */
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int tx_running;
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struct cpsw_queue rx, tx;
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struct cpsw_queue tx_active;
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struct cpsw_queue tx_avail;
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struct cpsw_slot _tx_slots[CPSW_MAX_TX_BUFFERS];
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/* Statistics */
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/* 64-bit versions of 32-bit hardware statistics counters */
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uint32_t tx_enqueues; /* total TX bufs added to queue */
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uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
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uint32_t tx_retires; /* total TX bufs removed from queue */
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uint32_t tx_retires_at_last_tick; /* used for watchdog */
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/* CPPI STATERAM has 512 slots for building TX/RX queues. */
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/* Note: tx_queued != tx_enqueues - tx_retires
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/* TODO: Size here supposedly varies with different versions
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At driver reset, packets can be discarded
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of the controller. Check DaVinci specs and find a good
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from TX queue without being retired. */
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way to adjust this. One option is to have a separate
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int tx_queued; /* Current bufs in TX queue */
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Device Tree parameter for number slots; another option
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int tx_max_queued;
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is to calculate it from the memory size in the device tree. */
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struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
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struct cpsw_slots avail;
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};
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};
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#define CPDMA_BD_SOP (1<<15)
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#define CPDMA_BD_EOP (1<<14)
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#define CPDMA_BD_OWNER (1<<13)
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#define CPDMA_BD_EOQ (1<<12)
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#define CPDMA_BD_TDOWNCMPLT (1<<11)
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#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
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struct cpsw_cpdma_bd {
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volatile uint32_t next;
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volatile uint32_t bufptr;
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volatile uint16_t buflen;
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volatile uint16_t bufoff;
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volatile uint16_t pktlen;
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volatile uint16_t flags;
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};
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/* Read/Write macros */
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#define cpsw_read_4(reg) bus_read_4(sc->res[0], reg)
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#define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val)
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#define cpsw_cpdma_txbd_offset(i) \
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(CPSW_CPPI_RAM_OFFSET + ((i)*16))
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#define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \
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vtophys(rman_get_start(sc->res[0])))
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#define cpsw_cpdma_read_txbd(i, val) \
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bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_txbd(i, val) \
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bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_txbd_next(i, val) \
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bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val)
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#define cpsw_cpdma_read_txbd_flags(i) \
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bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14)
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#define cpsw_cpdma_rxbd_offset(i) \
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(CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16))
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#define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \
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vtophys(rman_get_start(sc->res[0])))
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#define cpsw_cpdma_read_rxbd(i, val) \
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bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_rxbd(i, val) \
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bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4)
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#define cpsw_cpdma_write_rxbd_next(i, val) \
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bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val)
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#define cpsw_cpdma_read_rxbd_flags(i) \
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bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14)
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#endif /*_IF_CPSWVAR_H */
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#endif /*_IF_CPSWVAR_H */
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