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Fix cp15 PAR definition and function. While here, add cp15 ATS1CPW

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function which checks an address for privileged (PL1) write access.
The function is inlined so it does not bring any cost, but makes
function set for checking privileged access complete.

Approved by:	kib (mentor)
This commit is contained in:
Svatopluk Kraus 2015-11-10 13:20:21 +00:00
parent 765b884ede
commit aeef015ea1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=290656
2 changed files with 4 additions and 3 deletions
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5
sys/arm/include/cpu-v6.h
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@ -156,8 +156,9 @@ _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
_RF0(cp15_actlr_get, CP15_ACTLR(%0))
_WF1(cp15_actlr_set, CP15_ACTLR(%0))
#if __ARM_ARCH >= 6
_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0));
_RF0(cp15_par_get, CP15_PAR);
_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
_WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
_RF0(cp15_par_get, CP15_PAR(%0))
_RF0(cp15_sctlr_get, CP15_SCTLR(%0))
#endif

2
sys/arm/include/sysreg.h
View File

@ -130,7 +130,7 @@
#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */
#endif
#define CP15_PAR p15, 0, r0, c7, c4, 0 /* Physical Address Register */
#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */
#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */
#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */