Extend pmap to support e500mc and e5500.
As part of this, clean up tlb1_init(), since bootinfo is always NULL here just eliminate the loop altogether. Also, fix a bug in mmu_booke_mapdev_attr() where it's possible to map a larger immediately following a smaller page, causing the mappings to overlap. Instead, break up the new mapping into smaller chunks. The downside to this is that it uses more precious TLB1 entries, which, on smaller chips (e500v2) it could cause problems with TLB1 being out of space (e500v2 only has 16 TLB1 entries). Obtained from: Semihalf (partial) Sponsored by: Alex Perez/Inertial Computing
This commit is contained in:
Justin Hibbits
parent
d63180f2df
commit
afefc223b1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=287240
@ -178,15 +178,17 @@ static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
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uint32_t tlb0_entries;
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uint32_t tlb0_ways;
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uint32_t tlb0_entries_per_way;
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uint32_t tlb1_entries;
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#define TLB0_ENTRIES (tlb0_entries)
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#define TLB0_WAYS (tlb0_ways)
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#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
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#define TLB1_ENTRIES 16
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#define TLB1_ENTRIES (tlb1_entries)
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#define TLB1_MAXENTRIES 64
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/* In-ram copy of the TLB1 */
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static tlb_entry_t tlb1[TLB1_ENTRIES];
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static tlb_entry_t tlb1[TLB1_MAXENTRIES];
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/* Next free entry in the TLB1 */
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static unsigned int tlb1_idx;
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@ -495,6 +497,16 @@ tlb0_get_tlbconf(void)
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tlb0_entries_per_way = tlb0_entries / tlb0_ways;
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}
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/* Return number of entries in TLB1. */
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static __inline void
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tlb1_get_tlbconf(void)
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{
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uint32_t tlb1_cfg;
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tlb1_cfg = mfspr(SPR_TLB1CFG);
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tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
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}
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/* Initialize pool of kva ptbl buffers. */
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static void
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ptbl_init(void)
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@ -1224,7 +1236,7 @@ mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
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debugf("fill in phys_avail:\n");
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for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
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debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
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debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
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availmem_regions[i].mr_start,
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availmem_regions[i].mr_start +
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availmem_regions[i].mr_size,
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@ -2803,6 +2815,11 @@ mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
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do {
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sz = 1 << (ilog2(size) & ~1);
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if (va % sz != 0) {
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do {
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sz >>= 1;
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} while (va % sz != 0);
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}
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if (bootverbose)
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printf("Wiring VA=%x to PA=%llx (size=%x), "
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"using TLB1[%d]\n", va, pa, sz, tlb1_idx);
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@ -3042,8 +3059,21 @@ tlb1_write_entry(unsigned int idx)
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__asm __volatile("isync");
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mtspr(SPR_MAS3, tlb1[idx].mas3);
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__asm __volatile("isync");
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mtspr(SPR_MAS7, tlb1[idx].mas7);
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__asm __volatile("isync; tlbwe; isync; msync");
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switch ((mfpvr() >> 16) & 0xFFFF) {
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case FSL_E500mc:
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case FSL_E5500:
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mtspr(SPR_MAS8, 0);
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__asm __volatile("isync");
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/* FALLTHROUGH */
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case FSL_E500v2:
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mtspr(SPR_MAS7, tlb1[idx].mas7);
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__asm __volatile("isync");
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break;
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default:
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break;
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}
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__asm __volatile("tlbwe; isync; msync");
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//debugf("tlb1_write_entry: e\n");
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}
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@ -3210,42 +3240,34 @@ tlb1_init()
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{
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uint32_t mas0, mas1, mas2, mas3, mas7;
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uint32_t tsz;
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u_int i;
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int i;
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if (bootinfo != NULL && bootinfo[0] != 1) {
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tlb1_idx = *((uint16_t *)(bootinfo + 8));
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} else
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tlb1_idx = 1;
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tlb1_idx = 1;
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/* The first entry/entries are used to map the kernel. */
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for (i = 0; i < tlb1_idx; i++) {
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
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mtspr(SPR_MAS0, mas0);
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__asm __volatile("isync; tlbre");
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tlb1_get_tlbconf();
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mas1 = mfspr(SPR_MAS1);
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if ((mas1 & MAS1_VALID) == 0)
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continue;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
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mtspr(SPR_MAS0, mas0);
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__asm __volatile("isync; tlbre");
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mas2 = mfspr(SPR_MAS2);
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mas3 = mfspr(SPR_MAS3);
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mas7 = mfspr(SPR_MAS7);
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mas1 = mfspr(SPR_MAS1);
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mas2 = mfspr(SPR_MAS2);
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mas3 = mfspr(SPR_MAS3);
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mas7 = mfspr(SPR_MAS7);
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tlb1[i].mas1 = mas1;
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tlb1[i].mas2 = mfspr(SPR_MAS2);
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tlb1[i].mas3 = mas3;
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tlb1[i].mas7 = mas7;
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tlb1[i].virt = mas2 & MAS2_EPN_MASK;
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tlb1[i].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
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(mas3 & MAS3_RPN);
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tlb1[0].mas1 = mas1;
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tlb1[0].mas2 = mfspr(SPR_MAS2);
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tlb1[0].mas3 = mas3;
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tlb1[0].mas7 = mas7;
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tlb1[0].virt = mas2 & MAS2_EPN_MASK;
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tlb1[0].phys = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
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(mas3 & MAS3_RPN);
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if (i == 0)
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kernload = tlb1[i].phys;
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kernload = tlb1[0].phys;
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tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
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tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0;
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kernsize += tlb1[i].size;
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}
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tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
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tlb1[0].size = (tsz > 0) ? tsize2size(tsz) : 0;
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kernsize += tlb1[0].size;
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#ifdef SMP
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bp_ntlb1s = tlb1_idx;
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@ -605,6 +605,9 @@ search_failed:
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mtspr SPR_MAS3, %r23
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isync
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bl zero_mas7
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bl zero_mas8
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tlbwe
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msync
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isync
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@ -714,6 +717,10 @@ tlb_fill_entry:
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mtspr SPR_MAS7, %r23
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isync
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mflr %r21
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bl zero_mas8
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mtlr %r21
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tlbwe
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isync
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msync
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@ -34,7 +34,7 @@
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/* PowerPC E500 MAS registers */
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#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
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#define MAS0_ESEL(x) ((x << 16) & 0x000F0000)
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#define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
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#define MAS0_TLBSEL1 0x10000000
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#define MAS0_TLBSEL0 0x00000000
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