- The DELAY() should not be used in USB drivers.
- The usb_pause_mtx() function takes ticks and not milliseconds as last argument. MFC after: 3 days
This commit is contained in:
Hans Petter Selasky
parent
b41381aea9
commit
aff6e94558
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=266472
@ -271,6 +271,7 @@ static void urtwn_stop_locked(struct ifnet *);
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static void urtwn_abort_xfers(struct urtwn_softc *);
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static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
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const struct ieee80211_bpf_params *);
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static void urtwn_ms_delay(struct urtwn_softc *);
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/* Aliases. */
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#define urtwn_bb_write urtwn_write_4
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@ -1060,7 +1061,7 @@ urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
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for (ntries = 0; ntries < 100; ntries++) {
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if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
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break;
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DELAY(1);
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urtwn_ms_delay(sc);
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}
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if (ntries == 100) {
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device_printf(sc->sc_dev,
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@ -1120,16 +1121,16 @@ urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
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urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
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reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
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DELAY(1000);
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urtwn_ms_delay(sc);
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urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
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RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
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R92C_HSSI_PARAM2_READ_EDGE);
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DELAY(1000);
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urtwn_ms_delay(sc);
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urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
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reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
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DELAY(1000);
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urtwn_ms_delay(sc);
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if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
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val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
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@ -1152,7 +1153,7 @@ urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
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if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
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R92C_LLT_INIT_OP_NO_ACTIVE)
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return (0);
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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return (ETIMEDOUT);
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}
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@ -1172,7 +1173,7 @@ urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
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reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
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if (reg & R92C_EFUSE_CTRL_VALID)
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return (MS(reg, R92C_EFUSE_CTRL_DATA));
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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device_printf(sc->sc_dev,
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"could not read efuse byte at address 0x%x\n", addr);
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@ -2099,7 +2100,7 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
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for (ntries = 0; ntries < 1000; ntries++) {
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if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
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break;
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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if (ntries == 1000) {
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device_printf(sc->sc_dev,
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@ -2111,13 +2112,13 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
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urtwn_write_1(sc, R92C_RSV_CTRL, 0);
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/* Move SPS into PWM mode. */
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urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
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DELAY(100);
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urtwn_ms_delay(sc);
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reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
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if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
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urtwn_write_1(sc, R92C_LDOV12D_CTRL,
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reg | R92C_LDOV12D_CTRL_LDV12_EN);
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DELAY(100);
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urtwn_ms_delay(sc);
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urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
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urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
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~R92C_SYS_ISO_CTRL_MD2PP);
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@ -2130,7 +2131,7 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
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if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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if (ntries == 1000) {
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device_printf(sc->sc_dev,
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@ -2154,7 +2155,7 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
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if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
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R92C_APSD_CTRL_OFF_STATUS))
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break;
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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if (ntries == 200) {
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device_printf(sc->sc_dev,
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@ -2186,7 +2187,7 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
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val = urtwn_read_1(sc, 0x6) & 0x2;
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if (val == 0x2)
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break;
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DELAY(10);
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urtwn_ms_delay(sc);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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@ -2211,7 +2212,7 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(urtwn_read_1(sc, 0x5) & 0x1))
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break;
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DELAY(10);
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urtwn_ms_delay(sc);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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@ -2275,7 +2276,7 @@ urtwn_fw_reset(struct urtwn_softc *sc)
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reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
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if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
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return;
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DELAY(50);
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urtwn_ms_delay(sc);
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}
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/* Force 8051 reset. */
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urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
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@ -2409,7 +2410,7 @@ urtwn_load_firmware(struct urtwn_softc *sc)
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for (ntries = 0; ntries < 1000; ntries++) {
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if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
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break;
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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if (ntries == 1000) {
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device_printf(sc->sc_dev,
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@ -2427,7 +2428,7 @@ urtwn_load_firmware(struct urtwn_softc *sc)
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for (ntries = 0; ntries < 1000; ntries++) {
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if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
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break;
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DELAY(5);
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urtwn_ms_delay(sc);
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}
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if (ntries == 1000) {
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device_printf(sc->sc_dev,
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@ -2646,7 +2647,7 @@ urtwn_bb_init(struct urtwn_softc *sc)
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/* Write BB initialization values. */
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for (i = 0; i < prog->count; i++) {
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urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
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DELAY(1);
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urtwn_ms_delay(sc);
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}
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if (sc->chip & URTWN_CHIP_92C_1T2R) {
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@ -2692,14 +2693,14 @@ urtwn_bb_init(struct urtwn_softc *sc)
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for (i = 0; i < prog->agccount; i++) {
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urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
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prog->agcvals[i]);
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DELAY(1);
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urtwn_ms_delay(sc);
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}
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if (sc->chip & URTWN_CHIP_88E) {
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urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
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DELAY(1);
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urtwn_ms_delay(sc);
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urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
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DELAY(1);
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urtwn_ms_delay(sc);
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crystalcap = sc->r88e_rom[0xb9];
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if (crystalcap == 0xff)
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@ -2747,21 +2748,21 @@ urtwn_rf_init(struct urtwn_softc *sc)
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reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
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reg |= 0x100000;
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urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
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DELAY(1);
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urtwn_ms_delay(sc);
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/* Set RF_ENV output high. */
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reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
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reg |= 0x10;
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urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
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DELAY(1);
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urtwn_ms_delay(sc);
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/* Set address and data lengths of RF registers. */
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reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
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reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
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urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
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DELAY(1);
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urtwn_ms_delay(sc);
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reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
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reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
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urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
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DELAY(1);
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urtwn_ms_delay(sc);
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/* Write RF initialization values for this chain. */
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for (j = 0; j < prog[i].count; j++) {
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@ -2771,12 +2772,12 @@ urtwn_rf_init(struct urtwn_softc *sc)
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* These are fake RF registers offsets that
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* indicate a delay is required.
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*/
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usb_pause_mtx(&sc->sc_mtx, 50);
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usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */
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continue;
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}
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urtwn_rf_write(sc, i, prog[i].regs[j],
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prog[i].vals[j]);
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DELAY(1);
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urtwn_ms_delay(sc);
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}
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/* Restore RF_ENV control type. */
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@ -3250,7 +3251,7 @@ urtwn_lc_calib(struct urtwn_softc *sc)
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urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
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/* Give calibration the time to complete. */
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usb_pause_mtx(&sc->sc_mtx, 100);
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usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */
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/* Restore configuration. */
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if ((txmode & 0x70) != 0) {
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@ -3533,6 +3534,12 @@ urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
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return (0);
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}
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static void
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urtwn_ms_delay(struct urtwn_softc *sc)
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{
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usb_pause_mtx(&sc->sc_mtx, hz / 1000);
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}
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static device_method_t urtwn_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, urtwn_match),
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