Add more values for PCI capabilities, PCIe extended capabilities, and subclasses.
Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 1 week
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=358174
@ -151,6 +151,7 @@
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#define PCIY_SATA 0x12 /* SATA */
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#define PCIY_SATA 0x12 /* SATA */
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#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
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#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
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#define PCIY_EA 0x14 /* PCI Extended Allocation */
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#define PCIY_EA 0x14 /* PCI Extended Allocation */
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#define PCIY_FPB 0x15 /* Flattening Portal Bridge */
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/* Extended Capability Register Fields */
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/* Extended Capability Register Fields */
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@ -194,6 +195,20 @@
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#define PCIZ_LN_REQ 0x001c /* LN Requester */
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#define PCIZ_LN_REQ 0x001c /* LN Requester */
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#define PCIZ_DPC 0x001d /* Downstream Port Containment */
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#define PCIZ_DPC 0x001d /* Downstream Port Containment */
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#define PCIZ_L1PM 0x001e /* L1 PM Substates */
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#define PCIZ_L1PM 0x001e /* L1 PM Substates */
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#define PCIZ_PTM 0x001f /* Precision Time Measurement */
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#define PCIZ_M_PCIE 0x0020 /* PCIe over M-PHY */
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#define PCIZ_FRS 0x0021 /* FRS Queuing */
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#define PCIZ_RTR 0x0022 /* Readiness Time Reporting */
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#define PCIZ_DVSEC 0x0023 /* Designated Vendor-Specific */
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#define PCIZ_VF_REBAR 0x0024 /* VF Resizable BAR */
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#define PCIZ_DLNK 0x0025 /* Data Link Feature */
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#define PCIZ_16GT 0x0026 /* Physical Layer 16.0 GT/s */
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#define PCIZ_LMR 0x0027 /* Lane Margining at Receiver */
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#define PCIZ_HIER_ID 0x0028 /* Hierarchy ID */
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#define PCIZ_NPEM 0x0029 /* Native PCIe Enclosure Management */
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#define PCIZ_PL32 0x002a /* Physical Layer 32.0 GT/s */
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#define PCIZ_AP 0x002b /* Alternate Protocol */
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#define PCIZ_SFI 0x002c /* System Firmware Intermediary */
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/* config registers for header type 0 devices */
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/* config registers for header type 0 devices */
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@ -334,6 +349,8 @@
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#define PCIS_STORAGE_NVM 0x08
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#define PCIS_STORAGE_NVM 0x08
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#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01
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#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01
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#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02
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#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02
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#define PCIS_STORAGE_UFS 0x09
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#define PCIP_STORAGE_UFS_UFSHCI_1_0 0x01
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#define PCIS_STORAGE_OTHER 0x80
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#define PCIS_STORAGE_OTHER 0x80
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#define PCIC_NETWORK 0x02
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#define PCIC_NETWORK 0x02
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@ -344,6 +361,8 @@
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#define PCIS_NETWORK_ISDN 0x04
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#define PCIS_NETWORK_ISDN 0x04
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#define PCIS_NETWORK_WORLDFIP 0x05
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#define PCIS_NETWORK_WORLDFIP 0x05
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#define PCIS_NETWORK_PICMG 0x06
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#define PCIS_NETWORK_PICMG 0x06
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#define PCIS_NETWORK_INFINIBAND 0x07
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#define PCIS_NETWORK_HFC 0x08
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#define PCIS_NETWORK_OTHER 0x80
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#define PCIS_NETWORK_OTHER 0x80
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#define PCIC_DISPLAY 0x03
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#define PCIC_DISPLAY 0x03
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@ -357,6 +376,7 @@
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#define PCIS_MULTIMEDIA_AUDIO 0x01
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#define PCIS_MULTIMEDIA_AUDIO 0x01
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#define PCIS_MULTIMEDIA_TELE 0x02
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#define PCIS_MULTIMEDIA_TELE 0x02
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#define PCIS_MULTIMEDIA_HDA 0x03
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#define PCIS_MULTIMEDIA_HDA 0x03
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#define PCIP_MULTIMEDIA_HDA_VENDOR 0x01
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#define PCIS_MULTIMEDIA_OTHER 0x80
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#define PCIS_MULTIMEDIA_OTHER 0x80
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#define PCIC_MEMORY 0x05
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#define PCIC_MEMORY 0x05
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@ -377,6 +397,8 @@
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#define PCIS_BRIDGE_RACEWAY 0x08
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#define PCIS_BRIDGE_RACEWAY 0x08
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#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
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#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
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#define PCIS_BRIDGE_INFINIBAND 0x0a
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#define PCIS_BRIDGE_INFINIBAND 0x0a
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#define PCIS_BRIDGE_AS_PCI 0x0b
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#define PCIS_BRIDGE_AS_PCI_ASI_SIG 0x01
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#define PCIS_BRIDGE_OTHER 0x80
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#define PCIS_BRIDGE_OTHER 0x80
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#define PCIC_SIMPLECOMM 0x07
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#define PCIC_SIMPLECOMM 0x07
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@ -408,6 +430,7 @@
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#define PCIS_BASEPERIPH_PCIHOT 0x04
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#define PCIS_BASEPERIPH_PCIHOT 0x04
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#define PCIS_BASEPERIPH_SDHC 0x05
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#define PCIS_BASEPERIPH_SDHC 0x05
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#define PCIS_BASEPERIPH_IOMMU 0x06
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#define PCIS_BASEPERIPH_IOMMU 0x06
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#define PCIS_BASEPERIPH_RCEC 0x07
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#define PCIS_BASEPERIPH_OTHER 0x80
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#define PCIS_BASEPERIPH_OTHER 0x80
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#define PCIC_INPUTDEV 0x09
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#define PCIC_INPUTDEV 0x09
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@ -450,6 +473,7 @@
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#define PCIP_SERIALBUS_IPMI_BT 0x02
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#define PCIP_SERIALBUS_IPMI_BT 0x02
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#define PCIS_SERIALBUS_SERCOS 0x08
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#define PCIS_SERIALBUS_SERCOS 0x08
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#define PCIS_SERIALBUS_CANBUS 0x09
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#define PCIS_SERIALBUS_CANBUS 0x09
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#define PCIS_SERIALBUS_MIPI_I3C 0x0a
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#define PCIC_WIRELESS 0x0d
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#define PCIC_WIRELESS 0x0d
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#define PCIS_WIRELESS_IRDA 0x00
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#define PCIS_WIRELESS_IRDA 0x00
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@ -459,6 +483,8 @@
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#define PCIS_WIRELESS_BROADBAND 0x12
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#define PCIS_WIRELESS_BROADBAND 0x12
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#define PCIS_WIRELESS_80211A 0x20
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#define PCIS_WIRELESS_80211A 0x20
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#define PCIS_WIRELESS_80211B 0x21
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#define PCIS_WIRELESS_80211B 0x21
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#define PCIS_WIRELESS_CELL 0x40
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#define PCIS_WIRELESS_CELL_E 0x41
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#define PCIS_WIRELESS_OTHER 0x80
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#define PCIS_WIRELESS_OTHER 0x80
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#define PCIC_INTELLIIO 0x0e
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#define PCIC_INTELLIIO 0x0e
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