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sfxge: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:29:01 +00:00
parent 378503af2e
commit b138e49c66
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=365086
63 changed files with 0 additions and 843 deletions
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5
sys/dev/sfxge/common/ef10_ev.c
View File

@ -91,7 +91,6 @@ ef10_ev_mcdi(
__in const efx_ev_callbacks_t *eecp,
__in_opt void *arg);
static __checkReturn efx_rc_t
efx_mcdi_set_evq_tmr(
__in efx_nic_t *enp,
@ -273,7 +272,6 @@ efx_mcdi_init_evq(
return (rc);
}
static __checkReturn efx_rc_t
efx_mcdi_init_evq_v2(
__in efx_nic_t *enp,
@ -440,8 +438,6 @@ efx_mcdi_fini_evq(
return (rc);
}
__checkReturn efx_rc_t
ef10_ev_init(
__in efx_nic_t *enp)
@ -754,7 +750,6 @@ ef10_ev_qmoderate(
return (rc);
}
#if EFSYS_OPT_QSTATS
void
ef10_ev_qstats_update(

8
sys/dev/sfxge/common/ef10_filter.c
View File

@ -577,7 +577,6 @@ ef10_filter_restore(
enp->en_family == EFX_FAMILY_MEDFORD2);
for (tbl_id = 0; tbl_id < EFX_EF10_FILTER_TBL_ROWS; tbl_id++) {
EFSYS_LOCK(enp->en_eslp, state);
spec = ef10_filter_entry_spec(eftp, tbl_id);
@ -729,7 +728,6 @@ ef10_filter_add_internal(
/* This is a filter we are refreshing */
ef10_filter_set_entry_not_auto_old(eftp, ins_index);
goto out_unlock;
}
replacing = B_TRUE;
} else {
@ -835,7 +833,6 @@ ef10_filter_add(
return (rc);
}
static __checkReturn efx_rc_t
ef10_filter_delete_internal(
__in efx_nic_t *enp,
@ -1288,7 +1285,6 @@ ef10_filter_insert_multicast_list(
/* Only stop upon failure if told to rollback */
goto rollback;
}
}
if (brdcst == B_TRUE) {
@ -1493,7 +1489,6 @@ ef10_filter_remove_old(
}
}
static __checkReturn efx_rc_t
ef10_filter_get_workarounds(
__in efx_nic_t *enp)
@ -1529,7 +1524,6 @@ ef10_filter_get_workarounds(
}
/*
* Reconfigure all filters.
* If all_unicst and/or all mulcst filters cannot be applied then
@ -1767,7 +1761,6 @@ ef10_filter_get_default_rxq(
*using_rss = table->eft_using_rss;
}
void
ef10_filter_default_rxq_set(
__in efx_nic_t *enp,
@ -1797,7 +1790,6 @@ ef10_filter_default_rxq_clear(
table->eft_using_rss = B_FALSE;
}
#endif /* EFSYS_OPT_FILTER */
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */

5
sys/dev/sfxge/common/ef10_image.c
View File

@ -67,7 +67,6 @@ typedef struct efx_asn1_cursor_s {
uint32_t val_size;
} efx_asn1_cursor_t;
/* Parse header of DER encoded ASN.1 TLV and match tag */
static __checkReturn efx_rc_t
efx_asn1_parse_header_match_tag(
@ -305,7 +304,6 @@ efx_asn1_get_tag_value(
return (rc);
}
/*
* Utility routines for parsing CMS headers (see RFC2315, PKCS#7)
*/
@ -538,7 +536,6 @@ efx_check_reflash_image(
void *imagep;
efx_rc_t rc;
EFSYS_ASSERT(infop != NULL);
if (infop == NULL) {
rc = EINVAL;
@ -908,8 +905,6 @@ efx_build_signed_image_write_buffer(
return (rc);
}
#endif /* EFSYS_OPT_IMAGE_LAYOUT */
#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */

13
sys/dev/sfxge/common/ef10_impl.h
View File

@ -37,7 +37,6 @@
extern "C" {
#endif
/* Number of hardware PIO buffers (for compile-time resource dimensions) */
#define EF10_MAX_PIOBUF_NBUFS (16)
@ -57,8 +56,6 @@ extern "C" {
# endif
#endif /* EFSYS_OPT_MEDFORD2 */
/*
* FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
* possibly be increased, or the write size reported by newer firmware used
@ -81,7 +78,6 @@ extern "C" {
/* Invalid RSS context handle */
#define EF10_RSS_CONTEXT_INVALID (0xffffffff)
/* EV */
__checkReturn efx_rc_t
@ -240,7 +236,6 @@ extern void
ef10_nic_unprobe(
__in efx_nic_t *enp);
/* MAC */
extern __checkReturn efx_rc_t
@ -311,7 +306,6 @@ ef10_mac_stats_update(
#endif /* EFSYS_OPT_MAC_STATS */
/* MCDI */
#if EFSYS_OPT_MCDI
@ -615,7 +609,6 @@ ef10_nvram_buffer_finish(
#endif /* EFSYS_OPT_NVRAM */
/* PHY */
typedef struct ef10_link_state_s {
@ -876,7 +869,6 @@ ef10_nic_pio_unlink(
__inout efx_nic_t *enp,
__in uint32_t vi_index);
/* VPD */
#if EFSYS_OPT_VPD
@ -942,7 +934,6 @@ ef10_vpd_fini(
#endif /* EFSYS_OPT_VPD */
/* RX */
extern __checkReturn efx_rc_t
@ -956,7 +947,6 @@ ef10_rx_scatter_enable(
__in unsigned int buf_size);
#endif /* EFSYS_OPT_RX_SCATTER */
#if EFSYS_OPT_RX_SCALE
extern __checkReturn efx_rc_t
@ -1166,7 +1156,6 @@ extern void
ef10_filter_default_rxq_clear(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_FILTER */
extern __checkReturn efx_rc_t
@ -1215,7 +1204,6 @@ efx_mcdi_get_clock(
__out uint32_t *sys_freqp,
__out uint32_t *dpcpu_freqp);
extern __checkReturn efx_rc_t
efx_mcdi_get_rxdp_config(
__in efx_nic_t *enp,
@ -1249,7 +1237,6 @@ efx_mcdi_set_nic_global(
#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
#if EFSYS_OPT_RX_PACKED_STREAM
/* Data space per credit in packed stream mode */

5
sys/dev/sfxge/common/ef10_intr.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
__checkReturn efx_rc_t
@ -47,7 +46,6 @@ ef10_intr_init(
return (0);
}
void
ef10_intr_enable(
__in efx_nic_t *enp)
@ -55,7 +53,6 @@ ef10_intr_enable(
_NOTE(ARGUNUSED(enp))
}
void
ef10_intr_disable(
__in efx_nic_t *enp)
@ -63,7 +60,6 @@ ef10_intr_disable(
_NOTE(ARGUNUSED(enp))
}
void
ef10_intr_disable_unlocked(
__in efx_nic_t *enp)
@ -71,7 +67,6 @@ ef10_intr_disable_unlocked(
_NOTE(ARGUNUSED(enp))
}
static __checkReturn efx_rc_t
efx_mcdi_trigger_interrupt(
__in efx_nic_t *enp,

5
sys/dev/sfxge/common/ef10_mac.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
__checkReturn efx_rc_t
@ -442,7 +441,6 @@ ef10_mac_filter_default_rxq_clear(
epp->ep_mulcst_addr_count);
}
#if EFSYS_OPT_LOOPBACK
__checkReturn efx_rc_t
@ -603,7 +601,6 @@ ef10_mac_stats_get_mask(
#define EF10_MAC_STAT_READ(_esmp, _field, _eqp) \
EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
__checkReturn efx_rc_t
ef10_mac_stats_update(
__in efx_nic_t *enp,
@ -856,7 +853,6 @@ ef10_mac_stats_update(
EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);
EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);
/* VADAPTER RX */
EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,
&value);
@ -939,7 +935,6 @@ ef10_mac_stats_update(
EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2)
goto done;

2
sys/dev/sfxge/common/ef10_mcdi.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
#if EFSYS_OPT_MCDI
@ -43,7 +42,6 @@ __FBSDID("$FreeBSD$");
#error "WITH_MCDI_V2 required for EF10 MCDIv2 commands."
#endif
__checkReturn efx_rc_t
ef10_mcdi_init(
__in efx_nic_t *enp,

9
sys/dev/sfxge/common/ef10_nic.c
View File

@ -669,7 +669,6 @@ efx_mcdi_alloc_vis(
return (rc);
}
static __checkReturn efx_rc_t
efx_mcdi_free_vis(
__in efx_nic_t *enp)
@ -702,7 +701,6 @@ efx_mcdi_free_vis(
return (rc);
}
static __checkReturn efx_rc_t
efx_mcdi_alloc_piobuf(
__in efx_nic_t *enp,
@ -886,7 +884,6 @@ ef10_nic_alloc_piobufs(
enp->en_arch.ef10.ena_piobuf_count = 0;
}
static void
ef10_nic_free_piobufs(
__in efx_nic_t *enp)
@ -1075,7 +1072,6 @@ ef10_get_datapath_caps(
if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
goto fail1;
req.emr_cmd = MC_CMD_GET_CAPABILITIES;
req.emr_in_buf = payload;
req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
@ -1416,7 +1412,6 @@ ef10_get_datapath_caps(
return (rc);
}
#define EF10_LEGACY_PF_PRIVILEGE_MASK \
(MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
@ -1432,7 +1427,6 @@ ef10_get_datapath_caps(
#define EF10_LEGACY_VF_PRIVILEGE_MASK 0
__checkReturn efx_rc_t
ef10_get_privilege_mask(
__in efx_nic_t *enp,
@ -1467,7 +1461,6 @@ ef10_get_privilege_mask(
return (rc);
}
#define EFX_EXT_PORT_MAX 4
#define EFX_EXT_PORT_NA 0xFF
@ -2137,7 +2130,6 @@ ef10_nic_set_drv_limits(
return (rc);
}
__checkReturn efx_rc_t
ef10_nic_reset(
__in efx_nic_t *enp)
@ -2446,7 +2438,6 @@ ef10_nic_set_hw_unavailable(
enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
}
void
ef10_nic_fini(
__in efx_nic_t *enp)

7
sys/dev/sfxge/common/ef10_nvram.c
View File

@ -63,12 +63,10 @@ typedef struct nvram_partition_s {
tlv_cursor_t tlv_cursor;
} nvram_partition_t;
static __checkReturn efx_rc_t
tlv_validate_state(
__inout tlv_cursor_t *cursor);
static void
tlv_init_block(
__out uint32_t *block)
@ -130,7 +128,6 @@ tlv_item(
#define TLV_DWORD_COUNT(length) \
(1 + 1 + (((length) + sizeof (uint32_t) - 1) / sizeof (uint32_t)))
static uint32_t *
tlv_next_item_ptr(
__in tlv_cursor_t *cursor)
@ -375,7 +372,6 @@ tlv_last_segment_end(
return (last_segment_end);
}
static uint32_t *
tlv_write(
__in tlv_cursor_t *cursor,
@ -1168,7 +1164,6 @@ ef10_nvram_buffer_modify_item(
return (rc);
}
__checkReturn efx_rc_t
ef10_nvram_buffer_delete_item(
__in_bcount(buffer_size)
@ -1234,8 +1229,6 @@ ef10_nvram_buffer_finish(
return (rc);
}
/*
* Read and validate a segment from a partition. A segment is a complete
* tlv chain between PARTITION_HEADER and PARTITION_END tags. There may

3
sys/dev/sfxge/common/ef10_phy.c
View File

@ -188,7 +188,6 @@ mcdi_phy_decode_link_mode(
}
}
void
ef10_phy_link_ev(
__in efx_nic_t *enp,
@ -335,7 +334,6 @@ ef10_phy_get_link(
&elsp->epls.epls_ld_cap_mask);
}
#if EFSYS_OPT_LOOPBACK
/*
* MC_CMD_LOOPBACK and EFX_LOOPBACK names are equivalent, so use the
@ -599,7 +597,6 @@ ef10_phy_link_state_get(
return (rc);
}
#if EFSYS_OPT_PHY_STATS
__checkReturn efx_rc_t

6
sys/dev/sfxge/common/ef10_rx.c
View File

@ -34,10 +34,8 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
static __checkReturn efx_rc_t
efx_mcdi_init_rxq(
__in efx_nic_t *enp,
@ -539,7 +537,6 @@ efx_mcdi_rss_context_set_table(
}
#endif /* EFSYS_OPT_RX_SCALE */
__checkReturn efx_rc_t
ef10_rx_init(
__in efx_nic_t *enp)
@ -712,7 +709,6 @@ ef10_rx_scale_tbl_set(
{
efx_rc_t rc;
if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
rc = ENOTSUP;
@ -736,7 +732,6 @@ ef10_rx_scale_tbl_set(
}
#endif /* EFSYS_OPT_RX_SCALE */
/*
* EF10 RX pseudo-header
* ---------------------
@ -973,7 +968,6 @@ ef10_rx_qps_packet_info(
return (pkt_start);
}
#endif
__checkReturn efx_rc_t

21
sys/dev/sfxge/common/ef10_tlv_layout.h
View File

@ -85,17 +85,14 @@
* well enough.)
*/
#ifndef CI_MGMT_TLV_LAYOUT_H
#define CI_MGMT_TLV_LAYOUT_H
/* ----------------------------------------------------------------------------
* General structure (defined by SF-108797-SW)
* ----------------------------------------------------------------------------
*/
/* The "end" tag.
*
* (Note that this is *not* followed by length or value fields: anything after
@ -104,14 +101,12 @@
#define TLV_TAG_END (0xEEEEEEEE)
/* Other special reserved tag values.
*/
#define TLV_TAG_SKIP (0x00000000)
#define TLV_TAG_INVALID (0xFFFFFFFF)
/* TLV partition header.
*
* In a TLV partition, this must be the first item in the sequence, at offset
@ -133,7 +128,6 @@ struct tlv_partition_header {
uint32_t total_length;
};
/* TLV partition trailer.
*
* In a TLV partition, this must be the last item in the sequence, immediately
@ -149,7 +143,6 @@ struct tlv_partition_trailer {
uint32_t checksum;
};
/* Appendable TLV partition header.
*
* In an appendable TLV partition, this must be the first item in the sequence,
@ -166,13 +159,11 @@ struct tlv_appendable_partition_header {
uint16_t reserved;
};
/* ----------------------------------------------------------------------------
* Configuration items
* ----------------------------------------------------------------------------
*/
/* NIC global capabilities.
*/
@ -184,7 +175,6 @@ struct tlv_global_capabilities {
uint32_t flags;
};
/* Siena-style per-port MAC address allocation.
*
* There are <count> addresses, starting at <base_address> and incrementing
@ -205,7 +195,6 @@ struct tlv_port_mac {
uint16_t stride;
};
/* Static VPD.
*
* This is the portion of VPD which is set at manufacturing time and not
@ -230,7 +219,6 @@ struct tlv_global_static_vpd {
uint8_t bytes[];
};
/* Dynamic VPD.
*
* This is the portion of VPD which may be changed (e.g. by firmware updates).
@ -255,7 +243,6 @@ struct tlv_global_dynamic_vpd {
uint8_t bytes[];
};
/* "DBI" PCI config space changes.
*
* This is a set of edits made to the default PCI config space values before
@ -276,7 +263,6 @@ struct tlv_pf_dbi {
} items[];
};
#define TLV_TAG_GLOBAL_DBI (0x00210000)
struct tlv_global_dbi {
@ -289,7 +275,6 @@ struct tlv_global_dbi {
} items[];
};
/* Partition subtype codes.
*
* A subtype may optionally be stored for each type of partition present in
@ -310,7 +295,6 @@ struct tlv_partition_subtype {
uint8_t description[];
};
/* Partition version codes.
*
* A version may optionally be stored for each type of partition present in
@ -366,7 +350,6 @@ struct tlv_per_pf_pcie_config {
uint16_t msix_vec_base;
};
/* Development ONLY. This is a single TLV tag for all the gubbins
* that can be set through the MC command-line other than the PCIe
* settings. This is a temporary measure. */
@ -411,7 +394,6 @@ struct tlv_global_port_config {
uint32_t max_port_speed;
};
/* Firmware options.
*
* This is intended for user-configurable selection of optional firmware
@ -468,7 +450,6 @@ struct tlv_0v9_settings {
uint16_t panic_high; /* In millivolts */
};
/* Clock configuration */
#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
@ -496,7 +477,6 @@ struct tlv_clock_config_medford {
uint16_t clk_pcs; /* MHz */
};
/* EF10-style global pool of MAC addresses.
*
* There are <count> addresses, starting at <base_address>, which are
@ -537,7 +517,6 @@ struct tlv_pcie_tx_amp_config {
uint8_t lane_amp[16];
};
/* Global PCIe configuration, second revision. This represents the visible PFs
* by a bitmap rather than having the number of the highest visible one. As such
* it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG

3
sys/dev/sfxge/common/ef10_tx.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
#if EFSYS_OPT_QSTATS
@ -393,7 +392,6 @@ ef10_tx_qpio_post(
unsigned int added = *addedp;
efx_rc_t rc;
if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
rc = ENOSPC;
goto fail1;
@ -717,7 +715,6 @@ ef10_tx_qdesc_checksum_create(
(flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
}
__checkReturn efx_rc_t
ef10_tx_qpace(
__in efx_txq_t *etp,

1
sys/dev/sfxge/common/ef10_vpd.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_VPD
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2

2
sys/dev/sfxge/common/efsys.h
View File

@ -159,7 +159,6 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
/* Code inclusion options */
#define EFSYS_OPT_NAMES 1
#define EFSYS_OPT_SIENA 1
@ -333,7 +332,6 @@ typedef struct efsys_mem_s {
#define EFSYS_MEM_IS_NULL(_esmp) \
((_esmp)->esm_base == NULL)
#define EFSYS_MEM_ZERO(_esmp, _size) \
do { \
(void) memset((_esmp)->esm_base, 0, (_size)); \

22
sys/dev/sfxge/common/efx.h
View File

@ -72,7 +72,6 @@ extern "C" {
typedef __success(return == 0) int efx_rc_t;
/* Chip families */
typedef enum efx_family_e {
@ -92,7 +91,6 @@ efx_family(
__out efx_family_t *efp,
__out unsigned int *membarp);
#define EFX_PCI_VENID_SFC 0x1924
#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
@ -116,7 +114,6 @@ efx_family(
#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
#define EFX_MEM_BAR_SIENA 2
#define EFX_MEM_BAR_HUNTINGTON_PF 2
@ -127,7 +124,6 @@ efx_family(
#define EFX_MEM_BAR_MEDFORD2 0
/* Error codes */
enum {
@ -153,7 +149,6 @@ efx_crc32_calculate(
__in_ecount(length) uint8_t const *input,
__in int length);
/* Type prototypes */
typedef struct efx_rxq_s efx_rxq_t;
@ -609,7 +604,6 @@ efx_mac_fcntl_get(
__out unsigned int *fcntl_wantedp,
__out unsigned int *fcntl_linkp);
#if EFSYS_OPT_MAC_STATS
#if EFSYS_OPT_NAMES
@ -645,7 +639,6 @@ efx_mac_stats_get_mask(
((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
(1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
extern __checkReturn efx_rc_t
efx_mac_stats_clear(
__in efx_nic_t *enp);
@ -1022,7 +1015,6 @@ typedef enum efx_phy_cap_type_e {
EFX_PHY_CAP_NTYPES
} efx_phy_cap_type_t;
#define EFX_PHY_CAP_CURRENT 0x00000000
#define EFX_PHY_CAP_DEFAULT 0x00000001
#define EFX_PHY_CAP_PERM 0x00000002
@ -1097,7 +1089,6 @@ efx_phy_media_type_get(
*/
#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
extern __checkReturn efx_rc_t
efx_phy_module_get_info(
__in efx_nic_t *enp,
@ -1180,7 +1171,6 @@ efx_phy_stats_update(
#endif /* EFSYS_OPT_PHY_STATS */
#if EFSYS_OPT_BIST
typedef enum efx_bist_type_e {
@ -1512,7 +1502,6 @@ efx_nic_get_vi_pool(
__out uint32_t *rxq_countp,
__out uint32_t *txq_countp);
#if EFSYS_OPT_VPD
typedef enum efx_vpd_tag_e {
@ -1531,7 +1520,6 @@ typedef struct efx_vpd_value_s {
uint8_t evv_value[0x100];
} efx_vpd_value_t;
#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
extern __checkReturn efx_rc_t
@ -1742,7 +1730,6 @@ efx_bootcfg_write(
__in_bcount(size) uint8_t *data,
__in size_t size);
/*
* Processing routines for buffers arranged in the DHCP/BOOTP option format
* (see https://tools.ietf.org/html/rfc1533)
@ -1798,7 +1785,6 @@ efx_dhcp_find_end(
__in size_t buffer_length,
__deref_out uint8_t **endpp);
extern __checkReturn efx_rc_t
efx_dhcp_delete_tag(
__inout_bcount(buffer_length) uint8_t *bufferp,
@ -1822,7 +1808,6 @@ efx_dhcp_update_tag(
__in_bcount_opt(value_length) uint8_t *valuep,
__in size_t value_length);
#endif /* EFSYS_OPT_BOOTCFG */
#if EFSYS_OPT_IMAGE_LAYOUT
@ -1875,7 +1860,6 @@ typedef struct efx_image_header_s {
#define EFX_IMAGE_HEADER_VERSION (4)
#define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
typedef struct efx_image_trailer_s {
uint32_t eit_crc;
} efx_image_trailer_t;
@ -2076,7 +2060,6 @@ typedef __checkReturn boolean_t
#define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
#define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
#define EFX_EV_RX_NLABELS 32
#define EFX_EV_TX_NLABELS 32
@ -2448,7 +2431,6 @@ efx_rx_hash_default_support_get(
__in efx_nic_t *enp,
__out efx_rx_hash_support_t *supportp);
extern __checkReturn efx_rc_t
efx_rx_scale_default_support_get(
__in efx_nic_t *enp,
@ -2818,7 +2800,6 @@ extern void
efx_tx_qdestroy(
__in efx_txq_t *etp);
/* FILTER */
#if EFSYS_OPT_FILTER
@ -2937,7 +2918,6 @@ typedef struct efx_filter_spec_s {
uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
} efx_filter_spec_t;
/* Default values for use in filter specifications */
#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
@ -3124,7 +3104,6 @@ efx_lic_get_id(
__out size_t *lengthp,
__out_opt uint8_t *bufferp);
extern __checkReturn efx_rc_t
efx_lic_find_start(
__in efx_nic_t *enp,
@ -3314,7 +3293,6 @@ efx_phy_link_state_get(
__in efx_nic_t *enp,
__out efx_phy_link_state_t *eplsp);
#ifdef __cplusplus
}
#endif

4
sys/dev/sfxge/common/efx_bootcfg.c
View File

@ -76,7 +76,6 @@ typedef struct efx_dhcp_tag_hdr_s {
#define DHCP_CALC_TAG_LENGTH(payload_len) \
((payload_len) + sizeof (efx_dhcp_tag_hdr_t))
/* Report the layout of bootcfg sectors in NVRAM partition. */
__checkReturn efx_rc_t
efx_bootcfg_sector_info(
@ -163,7 +162,6 @@ efx_bootcfg_sector_info(
return (rc);
}
__checkReturn uint8_t
efx_dhcp_csum(
__in_bcount(size) uint8_t const *data,
@ -399,7 +397,6 @@ efx_dhcp_find_end(
return (rc);
}
/*
* Delete the given tag from anywhere in the buffer. Copes with
* encapsulated tags, and updates or deletes the encapsulating opt as
@ -751,7 +748,6 @@ efx_dhcp_update_tag(
return (rc);
}
/*
* Copy bootcfg sector data to a target buffer which may differ in size.
* Optionally corrects format errors in source buffer.

5
sys/dev/sfxge/common/efx_ev.c
View File

@ -53,8 +53,6 @@ __FBSDID("$FreeBSD$");
(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
#if EFSYS_OPT_SIENA
static __checkReturn efx_rc_t
@ -135,7 +133,6 @@ static const efx_ev_ops_t __efx_ev_ef10_ops = {
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
efx_ev_init(
__in efx_nic_t *enp)
@ -221,7 +218,6 @@ efx_ev_fini(
enp->en_mod_flags &= ~EFX_MOD_EV;
}
__checkReturn efx_rc_t
efx_ev_qcreate(
__in efx_nic_t *enp,
@ -903,7 +899,6 @@ siena_ev_tx(
EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);

7
sys/dev/sfxge/common/efx_filter.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_FILTER
#if EFSYS_OPT_SIENA
@ -348,7 +347,6 @@ efx_filter_spec_init_tx(
spec->efs_dmaq_id = (uint16_t)etp->et_index;
}
/*
* Specify IPv4 host, transport protocol and port in a filter specification
*/
@ -461,7 +459,6 @@ efx_filter_spec_set_mc_def(
return (0);
}
__checkReturn efx_rc_t
efx_filter_spec_set_encap_type(
__inout efx_filter_spec_t *spec,
@ -888,7 +885,6 @@ siena_filter_clear_used(
EFSYS_ASSERT3U(sftp->sft_used, >=, 0);
}
static siena_filter_tbl_id_t
siena_filter_tbl_id(
__in siena_filter_type_t type)
@ -1176,7 +1172,6 @@ siena_filter_push_entry(
return (rc);
}
static __checkReturn boolean_t
siena_filter_equal(
__in const siena_filter_spec_t *left,
@ -1186,7 +1181,6 @@ siena_filter_equal(
tbl_id = siena_filter_tbl_id(left->sfs_type);
if (left->sfs_type != right->sfs_type)
return (B_FALSE);
@ -1480,7 +1474,6 @@ siena_filter_add(
efsys_lock_state_t state;
uint32_t key;
EFSYS_ASSERT3P(spec, !=, NULL);
if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)

1
sys/dev/sfxge/common/efx_hash.c
View File

@ -110,7 +110,6 @@ __FBSDID("$FreeBSD$");
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
/* Produce a 32-bit hash from 32-bit aligned input */
__checkReturn uint32_t
efx_hash_dwords(

3
sys/dev/sfxge/common/efx_impl.h
View File

@ -44,7 +44,6 @@
#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
#endif
#if EFSYS_OPT_SIENA
#include "siena_impl.h"
#endif /* EFSYS_OPT_SIENA */
@ -402,7 +401,6 @@ typedef struct efx_nic_ops_s {
#define EFX_RXQ_LIMIT_TARGET 512
#endif
#if EFSYS_OPT_FILTER
#if EFSYS_OPT_SIENA
@ -768,7 +766,6 @@ struct efx_nic_s {
#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
};
#define EFX_NIC_MAGIC 0x02121996
typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,

6
sys/dev/sfxge/common/efx_intr.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_SIENA
static __checkReturn efx_rc_t
@ -86,10 +85,8 @@ static __checkReturn boolean_t
siena_intr_check_fatal(
__in efx_nic_t *enp);
#endif /* EFSYS_OPT_SIENA */
#if EFSYS_OPT_SIENA
static const efx_intr_ops_t __efx_intr_siena_ops = {
siena_intr_init, /* eio_init */
@ -245,7 +242,6 @@ efx_intr_disable_unlocked(
eiop->eio_disable_unlocked(enp);
}
__checkReturn efx_rc_t
efx_intr_trigger(
__in efx_nic_t *enp,
@ -303,7 +299,6 @@ efx_intr_fatal(
eiop->eio_fatal(enp);
}
/* ************************************************************************* */
/* ************************************************************************* */
/* ************************************************************************* */
@ -523,7 +518,6 @@ siena_intr_status_message(
*fatalp = B_FALSE;
}
static void
siena_intr_fatal(
__in efx_nic_t *enp)

10
sys/dev/sfxge/common/efx_lic.c
View File

@ -127,7 +127,6 @@ efx_lic_v1v2_finish_partition(
#endif /* EFSYS_OPT_HUNTINGTON | EFSYS_OPT_SIENA */
#if EFSYS_OPT_SIENA
static __checkReturn efx_rc_t
@ -318,7 +317,6 @@ static const efx_lic_ops_t __efx_lic_v3_ops = {
#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
/* V1 Licensing - used in Siena Modena only */
#if EFSYS_OPT_SIENA
@ -549,7 +547,6 @@ efx_lic_v1v2_validate_key(
return (B_FALSE);
}
__checkReturn efx_rc_t
efx_lic_v1v2_read_key(
__in efx_nic_t *enp,
@ -661,7 +658,6 @@ efx_lic_v1v2_create_partition(
return (0);
}
__checkReturn efx_rc_t
efx_lic_v1v2_finish_partition(
__in efx_nic_t *enp,
@ -676,7 +672,6 @@ efx_lic_v1v2_finish_partition(
#endif /* EFSYS_OPT_HUNTINGTON | EFSYS_OPT_SIENA */
/* V2 Licensing - used by Huntington family only. See SF-113611-TC */
#if EFSYS_OPT_HUNTINGTON
@ -1271,7 +1266,6 @@ efx_lic_v3_finish_partition(
return (rc);
}
#endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
@ -1287,7 +1281,6 @@ efx_lic_init(
EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_LIC));
switch (enp->en_family) {
#if EFSYS_OPT_SIENA
case EFX_FAMILY_SIENA:
elop = &__efx_lic_v1_ops;
@ -1359,7 +1352,6 @@ efx_lic_fini(
enp->en_mod_flags &= ~EFX_MOD_LIC;
}
__checkReturn efx_rc_t
efx_lic_update_licenses(
__in efx_nic_t *enp)
@ -1538,7 +1530,6 @@ efx_lic_find_key(
startp, lengthp));
}
/*
* Validate that the buffer contains a single key in a recognised format.
* An empty or terminator buffer is not accepted as a valid key.
@ -1679,7 +1670,6 @@ efx_lic_create_partition(
return (rc);
}
__checkReturn efx_rc_t
efx_lic_finish_partition(
__in efx_nic_t *enp,

3
sys/dev/sfxge/common/efx_mac.c
View File

@ -516,7 +516,6 @@ efx_mac_filter_default_rxq_clear(
emop->emo_filter_default_rxq_clear(enp);
}
#if EFSYS_OPT_MAC_STATS
#if EFSYS_OPT_NAMES
@ -826,7 +825,6 @@ efx_mac_stats_periodic(
return (rc);
}
__checkReturn efx_rc_t
efx_mac_stats_update(
__in efx_nic_t *enp,
@ -907,7 +905,6 @@ efx_mac_select(
return (rc);
}
#if EFSYS_OPT_SIENA
#define EFX_MAC_HASH_BITS (1 << 8)

10
sys/dev/sfxge/common/efx_mcdi.c
View File

@ -57,8 +57,6 @@ __FBSDID("$FreeBSD$");
* response with ERROR=1 and DATALEN=0 until a request is seen with NOT_EPOCH=0.
*/
#if EFSYS_OPT_SIENA
static const efx_mcdi_ops_t __efx_mcdi_siena_ops = {
@ -89,8 +87,6 @@ static const efx_mcdi_ops_t __efx_mcdi_ef10_ops = {
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
efx_mcdi_init(
__in efx_nic_t *enp,
@ -344,7 +340,6 @@ efx_mcdi_request_start(
emrp->emr_in_buf, emrp->emr_in_length);
}
static void
efx_mcdi_read_response_header(
__in efx_nic_t *enp,
@ -504,7 +499,6 @@ efx_mcdi_finish_response(
#endif /* EFSYS_OPT_MCDI_LOGGING */
}
__checkReturn boolean_t
efx_mcdi_request_poll(
__in efx_nic_t *enp)
@ -1274,7 +1268,6 @@ efx_mcdi_read_assertion(
return (rc);
}
/*
* Internal routines for for specific MCDI requests.
*/
@ -1770,7 +1763,6 @@ efx_mcdi_bist_start(
#endif /* EFSYS_OPT_BIST */
/* Enable logging of some events (e.g. link state changes) */
__checkReturn efx_rc_t
efx_mcdi_log_ctrl(
@ -1806,7 +1798,6 @@ efx_mcdi_log_ctrl(
return (rc);
}
#if EFSYS_OPT_MAC_STATS
typedef enum efx_stats_action_e {
@ -2132,7 +2123,6 @@ efx_mcdi_set_workaround(
return (rc);
}
__checkReturn efx_rc_t
efx_mcdi_get_workarounds(
__in efx_nic_t *enp,

2
sys/dev/sfxge/common/efx_mcdi.h
View File

@ -196,7 +196,6 @@ efx_mcdi_mac_spoofing_supported(
__in efx_nic_t *enp,
__out boolean_t *supportedp);
#if EFSYS_OPT_BIST
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
extern __checkReturn efx_rc_t
@ -236,7 +235,6 @@ efx_mcdi_mac_stats_periodic(
__in uint16_t period_ms,
__in boolean_t events);
#if EFSYS_OPT_LOOPBACK
extern __checkReturn efx_rc_t
efx_mcdi_get_loopback_modes(

1
sys/dev/sfxge/common/efx_mon.c
View File

@ -73,7 +73,6 @@ static const efx_mon_ops_t __efx_mon_mcdi_ops = {
};
#endif
__checkReturn efx_rc_t
efx_mon_init(
__in efx_nic_t *enp)

6
sys/dev/sfxge/common/efx_nic.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
__checkReturn efx_rc_t
efx_family(
__in uint16_t venid,
@ -118,7 +117,6 @@ efx_family(
return (ENOTSUP);
}
#if EFSYS_OPT_SIENA
static const efx_nic_ops_t __efx_nic_siena_ops = {
@ -203,7 +201,6 @@ static const efx_nic_ops_t __efx_nic_medford2_ops = {
#endif /* EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
efx_nic_create(
__in efx_family_t family,
@ -442,7 +439,6 @@ efx_nic_get_bar_region(
return (rc);
}
__checkReturn efx_rc_t
efx_nic_get_vi_pool(
__in efx_nic_t *enp,
@ -482,7 +478,6 @@ efx_nic_get_vi_pool(
return (rc);
}
__checkReturn efx_rc_t
efx_nic_init(
__in efx_nic_t *enp)
@ -725,7 +720,6 @@ efx_nic_set_hw_unavailable(
enop->eno_set_hw_unavailable(enp);
}
#if EFSYS_OPT_DIAG
__checkReturn efx_rc_t

4
sys/dev/sfxge/common/efx_nvram.c
View File

@ -512,7 +512,6 @@ efx_nvram_validate(
return (rc);
}
void
efx_nvram_fini(
__in efx_nic_t *enp)
@ -948,7 +947,6 @@ efx_mcdi_nvram_write(
return (rc);
}
/*
* MC_CMD_NVRAM_UPDATE_FINISH_V2 must be used to support firmware-verified
* NVRAM updates. Older firmware will ignore the flags field in the request.
@ -1059,7 +1057,6 @@ efx_mcdi_nvram_test(
result = MCDI_OUT_DWORD(req, NVRAM_TEST_OUT_RESULT);
if (result == MC_CMD_NVRAM_TEST_FAIL) {
EFSYS_PROBE1(nvram_test_failure, int, partn);
rc = (EINVAL);
@ -1080,5 +1077,4 @@ efx_mcdi_nvram_test(
#endif /* EFSYS_OPT_DIAG */
#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */

2
sys/dev/sfxge/common/efx_phy.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_SIENA
static const efx_phy_ops_t __efx_phy_siena_ops = {
siena_phy_power, /* epo_power */
@ -484,7 +483,6 @@ efx_phy_stats_update(
#endif /* EFSYS_OPT_PHY_STATS */
#if EFSYS_OPT_BIST
__checkReturn efx_rc_t

1
sys/dev/sfxge/common/efx_phy_ids.h
View File

@ -49,5 +49,4 @@ typedef enum efx_phy_type_e { /* GENERATED BY scripts/genfwdef */
EFX_PHY_XFI_FARMI = 19,
} efx_phy_type_t;
#endif /* _SYS_EFX_PHY_IDS_H */

155
sys/dev/sfxge/common/efx_regs.h
View File

File diff suppressed because it is too large Load Diff

47
sys/dev/sfxge/common/efx_regs_ef10.h
View File

@ -55,11 +55,9 @@ extern "C" {
/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
#define ERF_DZ_HW_REV_ID_LBN 0
#define ERF_DZ_HW_REV_ID_WIDTH 32
/*
* BIU_MC_SFT_STATUS_REG(32bit):
*
@ -71,11 +69,9 @@ extern "C" {
#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
#define ERF_DZ_MC_SFT_STATUS_LBN 0
#define ERF_DZ_MC_SFT_STATUS_WIDTH 32
/*
* BIU_INT_ISR_REG(32bit):
*
@ -85,11 +81,9 @@ extern "C" {
/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0
#define ERF_DZ_ISR_REG_LBN 0
#define ERF_DZ_ISR_REG_WIDTH 32
/*
* MC_DB_LWRD_REG(32bit):
*
@ -99,11 +93,9 @@ extern "C" {
/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0
#define ERF_DZ_MC_DOORBELL_L_LBN 0
#define ERF_DZ_MC_DOORBELL_L_WIDTH 32
/*
* MC_DB_HWRD_REG(32bit):
*
@ -113,11 +105,9 @@ extern "C" {
/* hunta0,medforda0,medford2a0=pf_dbell_bar */
#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0
#define ERF_DZ_MC_DOORBELL_H_LBN 0
#define ERF_DZ_MC_DOORBELL_H_WIDTH 32
/*
* EVQ_RPTR_REG(32bit):
*
@ -129,13 +119,11 @@ extern "C" {
#define ER_DZ_EVQ_RPTR_REG_ROWS 2048
#define ER_DZ_EVQ_RPTR_REG_RESET 0x0
#define ERF_DZ_EVQ_RPTR_VLD_LBN 15
#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
#define ERF_DZ_EVQ_RPTR_LBN 0
#define ERF_DZ_EVQ_RPTR_WIDTH 15
/*
* EVQ_RPTR_REG_64K(32bit):
*
@ -147,13 +135,11 @@ extern "C" {
#define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048
#define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0
#define ERF_FZ_EVQ_RPTR_VLD_LBN 15
#define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1
#define ERF_FZ_EVQ_RPTR_LBN 0
#define ERF_FZ_EVQ_RPTR_WIDTH 15
/*
* EVQ_RPTR_REG_16K(32bit):
*
@ -165,13 +151,11 @@ extern "C" {
#define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048
#define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0
/* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */
/* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */
/* defined as ERF_FZ_EVQ_RPTR_LBN 0; */
/* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */
/*
* EVQ_TMR_REG_64K(32bit):
*
@ -183,7 +167,6 @@ extern "C" {
#define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048
#define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
#define ERF_FZ_TC_TMR_REL_VAL_LBN 16
#define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14
#define ERF_FZ_TC_TIMER_MODE_LBN 14
@ -191,7 +174,6 @@ extern "C" {
#define ERF_FZ_TC_TIMER_VAL_LBN 0
#define ERF_FZ_TC_TIMER_VAL_WIDTH 14
/*
* EVQ_TMR_REG_16K(32bit):
*
@ -203,7 +185,6 @@ extern "C" {
#define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048
#define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
/* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
@ -211,7 +192,6 @@ extern "C" {
/* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
/* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */
/*
* EVQ_TMR_REG(32bit):
*
@ -223,7 +203,6 @@ extern "C" {
#define ER_DZ_EVQ_TMR_REG_ROWS 2048
#define ER_DZ_EVQ_TMR_REG_RESET 0x0
/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
#define ERF_DZ_TC_TIMER_MODE_LBN 14
@ -231,7 +210,6 @@ extern "C" {
#define ERF_DZ_TC_TIMER_VAL_LBN 0
#define ERF_DZ_TC_TIMER_VAL_WIDTH 14
/*
* RX_DESC_UPD_REG_16K(32bit):
*
@ -243,11 +221,9 @@ extern "C" {
#define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048
#define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0
#define ERF_FZ_RX_DESC_WPTR_LBN 0
#define ERF_FZ_RX_DESC_WPTR_WIDTH 12
/*
* RX_DESC_UPD_REG(32bit):
*
@ -259,11 +235,9 @@ extern "C" {
#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048
#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0
#define ERF_DZ_RX_DESC_WPTR_LBN 0
#define ERF_DZ_RX_DESC_WPTR_WIDTH 12
/*
* RX_DESC_UPD_REG_64K(32bit):
*
@ -275,11 +249,9 @@ extern "C" {
#define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048
#define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0
/* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */
/* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */
/*
* TX_DESC_UPD_REG_64K(96bit):
*
@ -291,7 +263,6 @@ extern "C" {
#define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048
#define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0
#define ERF_FZ_RSVD_LBN 76
#define ERF_FZ_RSVD_WIDTH 20
#define ERF_FZ_TX_DESC_WPTR_LBN 64
@ -301,7 +272,6 @@ extern "C" {
#define ERF_FZ_TX_DESC_LWORD_LBN 0
#define ERF_FZ_TX_DESC_LWORD_WIDTH 32
/*
* TX_DESC_UPD_REG_16K(96bit):
*
@ -313,7 +283,6 @@ extern "C" {
#define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048
#define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0
/* defined as ERF_FZ_RSVD_LBN 76; */
/* defined as ERF_FZ_RSVD_WIDTH 20 */
/* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */
@ -323,7 +292,6 @@ extern "C" {
/* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */
/* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */
/*
* TX_DESC_UPD_REG(96bit):
*
@ -335,7 +303,6 @@ extern "C" {
#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048
#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0
#define ERF_DZ_RSVD_LBN 76
#define ERF_DZ_RSVD_WIDTH 20
#define ERF_DZ_TX_DESC_WPTR_LBN 64
@ -345,7 +312,6 @@ extern "C" {
#define ERF_DZ_TX_DESC_LWORD_LBN 0
#define ERF_DZ_TX_DESC_LWORD_WIDTH 32
/* ES_DRIVER_EV */
#define ESF_DZ_DRV_CODE_LBN 60
#define ESF_DZ_DRV_CODE_WIDTH 4
@ -365,7 +331,6 @@ extern "C" {
#define ESF_DZ_DRV_TMR_ID_LBN 0
#define ESF_DZ_DRV_TMR_ID_WIDTH 14
/* ES_EVENT_ENTRY */
#define ESF_DZ_EV_CODE_LBN 60
#define ESF_DZ_EV_CODE_WIDTH 4
@ -381,7 +346,6 @@ extern "C" {
#define ESF_DZ_EV_DATA_LBN 0
#define ESF_DZ_EV_DATA_WIDTH 60
/* ES_MC_EVENT */
#define ESF_DZ_MC_CODE_LBN 60
#define ESF_DZ_MC_CODE_WIDTH 4
@ -396,7 +360,6 @@ extern "C" {
#define ESF_DZ_MC_SOFT_LBN 0
#define ESF_DZ_MC_SOFT_WIDTH 58
/* ES_RX_EVENT */
#define ESF_DZ_RX_CODE_LBN 60
#define ESF_DZ_RX_CODE_WIDTH 4
@ -501,7 +464,6 @@ extern "C" {
#define ESF_DZ_RX_BYTES_LBN 0
#define ESF_DZ_RX_BYTES_WIDTH 14
/* ES_RX_KER_DESC */
#define ESF_DZ_RX_KER_RESERVED_LBN 62
#define ESF_DZ_RX_KER_RESERVED_WIDTH 2
@ -514,7 +476,6 @@ extern "C" {
#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
/* ES_TX_CSUM_TSTAMP_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
@ -544,7 +505,6 @@ extern "C" {
#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
/* ES_TX_EVENT */
#define ESF_DZ_TX_CODE_LBN 60
#define ESF_DZ_TX_CODE_WIDTH 4
@ -573,7 +533,6 @@ extern "C" {
#define ESF_DZ_TX_DESCR_INDX_LBN 0
#define ESF_DZ_TX_DESCR_INDX_WIDTH 16
/* ES_TX_KER_DESC */
#define ESF_DZ_TX_KER_TYPE_LBN 63
#define ESF_DZ_TX_KER_TYPE_WIDTH 1
@ -588,7 +547,6 @@ extern "C" {
#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
/* ES_TX_PIO_DESC */
#define ESF_DZ_TX_PIO_TYPE_LBN 63
#define ESF_DZ_TX_PIO_TYPE_WIDTH 1
@ -601,7 +559,6 @@ extern "C" {
#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
/* ES_TX_TSO_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
@ -623,7 +580,6 @@ extern "C" {
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
/* ES_TX_TSO_V2_DESC_A */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
@ -643,7 +599,6 @@ extern "C" {
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
/* ES_TX_TSO_V2_DESC_B */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
@ -663,7 +618,6 @@ extern "C" {
#define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
#define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
/* ES_TX_VLAN_DESC */
#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
@ -679,7 +633,6 @@ extern "C" {
#define ESF_DZ_TX_VLAN_TAG1_LBN 0
#define ESF_DZ_TX_VLAN_TAG1_WIDTH 16
/*************************************************************************
* NOTE: the comment line above marks the end of the autogenerated section
*/

254
sys/dev/sfxge/common/efx_regs_mcdi.h
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File diff suppressed because it is too large Load Diff

3
sys/dev/sfxge/common/efx_regs_mcdi_aoe.h
View File

@ -30,8 +30,6 @@
#ifndef _SYS_EFX_REGS_MCDI_AOE_H
#define _SYS_EFX_REGS_MCDI_AOE_H
/***********************************/
/* MC_CMD_FC
* Perform an FC operation
@ -2204,7 +2202,6 @@
/* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */
#define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0
/***********************************/
/* MC_CMD_AOE
* AOE operations on MC

134
sys/dev/sfxge/common/efx_regs_pci.h
View File

@ -50,7 +50,6 @@ extern "C" {
#define PCRF_AZ_VEND_ID_LBN 0
#define PCRF_AZ_VEND_ID_WIDTH 16
/*
* PC_DEV_ID_REG(16bit):
* Device ID register
@ -62,7 +61,6 @@ extern "C" {
#define PCRF_AZ_DEV_ID_LBN 0
#define PCRF_AZ_DEV_ID_WIDTH 16
/*
* PC_CMD_REG(16bit):
* Command register
@ -94,7 +92,6 @@ extern "C" {
#define PCRF_AZ_IO_EN_LBN 0
#define PCRF_AZ_IO_EN_WIDTH 1
/*
* PC_STAT_REG(16bit):
* Status register
@ -126,7 +123,6 @@ extern "C" {
#define PCRF_AZ_INTX_STAT_LBN 3
#define PCRF_AZ_INTX_STAT_WIDTH 1
/*
* PC_REV_ID_REG(8bit):
* Class code & revision ID register
@ -138,7 +134,6 @@ extern "C" {
#define PCRF_AZ_REV_ID_LBN 0
#define PCRF_AZ_REV_ID_WIDTH 8
/*
* PC_CC_REG(24bit):
* Class code register
@ -154,7 +149,6 @@ extern "C" {
#define PCRF_AZ_PROG_IF_LBN 0
#define PCRF_AZ_PROG_IF_WIDTH 8
/*
* PC_CACHE_LSIZE_REG(8bit):
* Cache line size
@ -166,7 +160,6 @@ extern "C" {
#define PCRF_AZ_CACHE_LSIZE_LBN 0
#define PCRF_AZ_CACHE_LSIZE_WIDTH 8
/*
* PC_MST_LAT_REG(8bit):
* Master latency timer register
@ -178,7 +171,6 @@ extern "C" {
#define PCRF_AZ_MST_LAT_LBN 0
#define PCRF_AZ_MST_LAT_WIDTH 8
/*
* PC_HDR_TYPE_REG(8bit):
* Header type register
@ -192,7 +184,6 @@ extern "C" {
#define PCRF_AZ_TYPE_LBN 0
#define PCRF_AZ_TYPE_WIDTH 7
/*
* PC_BIST_REG(8bit):
* BIST register
@ -204,7 +195,6 @@ extern "C" {
#define PCRF_AZ_BIST_LBN 0
#define PCRF_AZ_BIST_WIDTH 8
/*
* PC_BAR0_REG(32bit):
* Primary function base address register 0
@ -222,7 +212,6 @@ extern "C" {
#define PCRF_AZ_BAR0_IOM_LBN 0
#define PCRF_AZ_BAR0_IOM_WIDTH 1
/*
* PC_BAR1_REG(32bit):
* Primary function base address register 1, BAR1 is not implemented so read only.
@ -234,7 +223,6 @@ extern "C" {
#define PCRF_DZ_BAR1_LBN 0
#define PCRF_DZ_BAR1_WIDTH 32
/*
* PC_BAR2_LO_REG(32bit):
* Primary function base address register 2 low bits
@ -252,7 +240,6 @@ extern "C" {
#define PCRF_AZ_BAR2_IOM_LBN 0
#define PCRF_AZ_BAR2_IOM_WIDTH 1
/*
* PC_BAR2_HI_REG(32bit):
* Primary function base address register 2 high bits
@ -264,7 +251,6 @@ extern "C" {
#define PCRF_AZ_BAR2_HI_LBN 0
#define PCRF_AZ_BAR2_HI_WIDTH 32
/*
* PC_BAR4_LO_REG(32bit):
* Primary function base address register 2 low bits
@ -282,7 +268,6 @@ extern "C" {
#define PCRF_CZ_BAR4_IOM_LBN 0
#define PCRF_CZ_BAR4_IOM_WIDTH 1
/*
* PC_BAR4_HI_REG(32bit):
* Primary function base address register 2 high bits
@ -294,7 +279,6 @@ extern "C" {
#define PCRF_CZ_BAR4_HI_LBN 0
#define PCRF_CZ_BAR4_HI_WIDTH 32
/*
* PC_SS_VEND_ID_REG(16bit):
* Sub-system vendor ID register
@ -306,7 +290,6 @@ extern "C" {
#define PCRF_AZ_SS_VEND_ID_LBN 0
#define PCRF_AZ_SS_VEND_ID_WIDTH 16
/*
* PC_SS_ID_REG(16bit):
* Sub-system ID register
@ -318,7 +301,6 @@ extern "C" {
#define PCRF_AZ_SS_ID_LBN 0
#define PCRF_AZ_SS_ID_WIDTH 16
/*
* PC_EXPROM_BAR_REG(32bit):
* Expansion ROM base address register
@ -338,7 +320,6 @@ extern "C" {
#define PCRF_AZ_EXPROM_EN_LBN 0
#define PCRF_AZ_EXPROM_EN_WIDTH 1
/*
* PC_CAP_PTR_REG(8bit):
* Capability pointer register
@ -350,7 +331,6 @@ extern "C" {
#define PCRF_AZ_CAP_PTR_LBN 0
#define PCRF_AZ_CAP_PTR_WIDTH 8
/*
* PC_INT_LINE_REG(8bit):
* Interrupt line register
@ -362,7 +342,6 @@ extern "C" {
#define PCRF_AZ_INT_LINE_LBN 0
#define PCRF_AZ_INT_LINE_WIDTH 8
/*
* PC_INT_PIN_REG(8bit):
* Interrupt pin register
@ -378,7 +357,6 @@ extern "C" {
#define PCFE_DZ_INTPIN_INTB 2
#define PCFE_DZ_INTPIN_INTA 1
/*
* PC_PM_CAP_ID_REG(8bit):
* Power management capability ID
@ -390,7 +368,6 @@ extern "C" {
#define PCRF_AZ_PM_CAP_ID_LBN 0
#define PCRF_AZ_PM_CAP_ID_WIDTH 8
/*
* PC_PM_NXT_PTR_REG(8bit):
* Power management next item pointer
@ -402,7 +379,6 @@ extern "C" {
#define PCRF_AZ_PM_NXT_PTR_LBN 0
#define PCRF_AZ_PM_NXT_PTR_WIDTH 8
/*
* PC_PM_CAP_REG(16bit):
* Power management capabilities register
@ -426,7 +402,6 @@ extern "C" {
#define PCRF_AZ_PM_PME_VER_LBN 0
#define PCRF_AZ_PM_PME_VER_WIDTH 3
/*
* PC_PM_CS_REG(16bit):
* Power management control & status register
@ -448,7 +423,6 @@ extern "C" {
#define PCRF_AZ_PM_PWR_ST_LBN 0
#define PCRF_AZ_PM_PWR_ST_WIDTH 2
/*
* PC_MSI_CAP_ID_REG(8bit):
* MSI capability ID
@ -460,7 +434,6 @@ extern "C" {
#define PCRF_AZ_MSI_CAP_ID_LBN 0
#define PCRF_AZ_MSI_CAP_ID_WIDTH 8
/*
* PC_MSI_NXT_PTR_REG(8bit):
* MSI next item pointer
@ -472,7 +445,6 @@ extern "C" {
#define PCRF_AZ_MSI_NXT_PTR_LBN 0
#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8
/*
* PC_MSI_CTL_REG(16bit):
* MSI control register
@ -490,7 +462,6 @@ extern "C" {
#define PCRF_AZ_MSI_EN_LBN 0
#define PCRF_AZ_MSI_EN_WIDTH 1
/*
* PC_MSI_ADR_LO_REG(32bit):
* MSI low 32 bits address register
@ -502,7 +473,6 @@ extern "C" {
#define PCRF_AZ_MSI_ADR_LO_LBN 2
#define PCRF_AZ_MSI_ADR_LO_WIDTH 30
/*
* PC_MSI_ADR_HI_REG(32bit):
* MSI high 32 bits address register
@ -514,7 +484,6 @@ extern "C" {
#define PCRF_AZ_MSI_ADR_HI_LBN 0
#define PCRF_AZ_MSI_ADR_HI_WIDTH 32
/*
* PC_MSI_DAT_REG(16bit):
* MSI data register
@ -526,7 +495,6 @@ extern "C" {
#define PCRF_AZ_MSI_DAT_LBN 0
#define PCRF_AZ_MSI_DAT_WIDTH 16
/*
* PC_PCIE_CAP_LIST_REG(16bit):
* PCIe capability list register
@ -543,7 +511,6 @@ extern "C" {
#define PCRF_AZ_PCIE_CAP_ID_LBN 0
#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8
/*
* PC_PCIE_CAP_REG(16bit):
* PCIe capability register
@ -564,7 +531,6 @@ extern "C" {
#define PCRF_AZ_PCIE_CAP_VER_LBN 0
#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4
/*
* PC_DEV_CAP_REG(32bit):
* PCIe device capabilities register
@ -601,7 +567,6 @@ extern "C" {
#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
/*
* PC_DEV_CTL_REG(16bit):
* PCIe device control register
@ -652,7 +617,6 @@ extern "C" {
#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
/*
* PC_DEV_STAT_REG(16bit):
* PCIe device status register
@ -677,7 +641,6 @@ extern "C" {
#define PCRF_AZ_CORR_ERR_DET_LBN 0
#define PCRF_AZ_CORR_ERR_DET_WIDTH 1
/*
* PC_LNK_CAP_REG(32bit):
* PCIe link capabilities register
@ -712,7 +675,6 @@ extern "C" {
#define PCRF_AZ_MAX_LNK_SP_LBN 0
#define PCRF_AZ_MAX_LNK_SP_WIDTH 4
/*
* PC_LNK_CTL_REG(16bit):
* PCIe link control register
@ -739,7 +701,6 @@ extern "C" {
#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
/*
* PC_LNK_STAT_REG(16bit):
* PCIe link status register
@ -762,7 +723,6 @@ extern "C" {
#define PCRF_AZ_LNK_SP_LBN 0
#define PCRF_AZ_LNK_SP_WIDTH 4
/*
* PC_SLOT_CAP_REG(32bit):
* PCIe slot capabilities register
@ -792,7 +752,6 @@ extern "C" {
#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
/*
* PC_SLOT_CTL_REG(16bit):
* PCIe slot control register
@ -820,7 +779,6 @@ extern "C" {
#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
/*
* PC_SLOT_STAT_REG(16bit):
* PCIe slot status register
@ -844,7 +802,6 @@ extern "C" {
#define PCRF_AB_ATTN_BUTDET_LBN 0
#define PCRF_AB_ATTN_BUTDET_WIDTH 1
/*
* PC_MSIX_CAP_ID_REG(8bit):
* MSIX Capability ID
@ -859,7 +816,6 @@ extern "C" {
#define PCRF_BZ_MSIX_CAP_ID_LBN 0
#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8
/*
* PC_MSIX_NXT_PTR_REG(8bit):
* MSIX Capability Next Capability Ptr
@ -874,7 +830,6 @@ extern "C" {
#define PCRF_BZ_MSIX_NXT_PTR_LBN 0
#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
/*
* PC_MSIX_CTL_REG(16bit):
* MSIX control register
@ -893,7 +848,6 @@ extern "C" {
#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0
#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
/*
* PC_MSIX_TBL_BASE_REG(32bit):
* MSIX Capability Vector Table Base
@ -910,7 +864,6 @@ extern "C" {
#define PCRF_BZ_MSIX_TBL_BIR_LBN 0
#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
/*
* PC_DEV_CAP2_REG(32bit):
* PCIe Device Capabilities 2
@ -941,7 +894,6 @@ extern "C" {
#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
/*
* PC_DEV_CTL2_REG(16bit):
* PCIe Device Control 2
@ -963,7 +915,6 @@ extern "C" {
#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
/*
* PC_MSIX_PBA_BASE_REG(32bit):
* MSIX Capability PBA Base
@ -980,7 +931,6 @@ extern "C" {
#define PCRF_BZ_MSIX_PBA_BIR_LBN 0
#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
/*
* PC_LNK_CAP2_REG(32bit):
* PCIe Link Capability 2
@ -992,7 +942,6 @@ extern "C" {
#define PCRF_DZ_LNK_SPEED_SUP_LBN 1
#define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
/*
* PC_LNK_CTL2_REG(16bit):
* PCIe Link Control 2
@ -1021,7 +970,6 @@ extern "C" {
#define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
#define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
/*
* PC_LNK_STAT2_REG(16bit):
* PCIe Link Status 2
@ -1033,7 +981,6 @@ extern "C" {
#define PCRF_CZ_CURRENT_DEEMPH_LBN 0
#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
/*
* PC_VPD_CAP_ID_REG(8bit):
* VPD data register
@ -1045,7 +992,6 @@ extern "C" {
#define PCRF_AB_VPD_CAP_ID_LBN 0
#define PCRF_AB_VPD_CAP_ID_WIDTH 8
/*
* PC_VPD_NXT_PTR_REG(8bit):
* VPD next item pointer
@ -1057,7 +1003,6 @@ extern "C" {
#define PCRF_AB_VPD_NXT_PTR_LBN 0
#define PCRF_AB_VPD_NXT_PTR_WIDTH 8
/*
* PC_VPD_ADDR_REG(16bit):
* VPD address register
@ -1071,7 +1016,6 @@ extern "C" {
#define PCRF_AB_VPD_ADDR_LBN 0
#define PCRF_AB_VPD_ADDR_WIDTH 15
/*
* PC_VPD_CAP_DATA_REG(32bit):
* documentation to be written for sum_PC_VPD_CAP_DATA_REG
@ -1086,7 +1030,6 @@ extern "C" {
#define PCRF_AZ_VPD_DATA_LBN 0
#define PCRF_AZ_VPD_DATA_WIDTH 32
/*
* PC_VPD_CAP_CTL_REG(8bit):
* VPD control and capabilities register
@ -1104,7 +1047,6 @@ extern "C" {
#define PCRF_CZ_VPD_CAP_ID_LBN 0
#define PCRF_CZ_VPD_CAP_ID_WIDTH 8
/*
* PC_AER_CAP_HDR_REG(32bit):
* AER capability header register
@ -1120,7 +1062,6 @@ extern "C" {
#define PCRF_AZ_AERCAPHDR_ID_LBN 0
#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16
/*
* PC_AER_UNCORR_ERR_STAT_REG(32bit):
* AER Uncorrectable error status register
@ -1152,7 +1093,6 @@ extern "C" {
#define PCRF_AB_TRAIN_ERR_STAT_LBN 0
#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
/*
* PC_AER_UNCORR_ERR_MASK_REG(32bit):
* AER Uncorrectable error mask register
@ -1188,7 +1128,6 @@ extern "C" {
#define PCRF_AB_TRAIN_ERR_MASK_LBN 0
#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
/*
* PC_AER_UNCORR_ERR_SEV_REG(32bit):
* AER Uncorrectable error severity register
@ -1220,7 +1159,6 @@ extern "C" {
#define PCRF_AB_TRAIN_ERR_SEV_LBN 0
#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
/*
* PC_AER_CORR_ERR_STAT_REG(32bit):
* AER Correctable error status register
@ -1242,7 +1180,6 @@ extern "C" {
#define PCRF_AZ_RX_ERR_STAT_LBN 0
#define PCRF_AZ_RX_ERR_STAT_WIDTH 1
/*
* PC_AER_CORR_ERR_MASK_REG(32bit):
* AER Correctable error status register
@ -1264,7 +1201,6 @@ extern "C" {
#define PCRF_AZ_RX_ERR_MASK_LBN 0
#define PCRF_AZ_RX_ERR_MASK_WIDTH 1
/*
* PC_AER_CAP_CTL_REG(32bit):
* AER capability and control register
@ -1284,7 +1220,6 @@ extern "C" {
#define PCRF_AZ_1ST_ERR_PTR_LBN 0
#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5
/*
* PC_AER_HDR_LOG_REG(128bit):
* AER Header log register
@ -1296,7 +1231,6 @@ extern "C" {
#define PCRF_AZ_HDR_LOG_LBN 0
#define PCRF_AZ_HDR_LOG_WIDTH 128
/*
* PC_DEVSN_CAP_HDR_REG(32bit):
* Device serial number capability header register
@ -1312,7 +1246,6 @@ extern "C" {
#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
/*
* PC_DEVSN_DWORD0_REG(32bit):
* Device serial number DWORD0
@ -1324,7 +1257,6 @@ extern "C" {
#define PCRF_CZ_DEVSN_DWORD0_LBN 0
#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32
/*
* PC_DEVSN_DWORD1_REG(32bit):
* Device serial number DWORD0
@ -1336,7 +1268,6 @@ extern "C" {
#define PCRF_CZ_DEVSN_DWORD1_LBN 0
#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32
/*
* PC_ARI_CAP_HDR_REG(32bit):
* ARI capability header register
@ -1352,7 +1283,6 @@ extern "C" {
#define PCRF_CZ_ARICAPHDR_ID_LBN 0
#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16
/*
* PC_ARI_CAP_REG(16bit):
* ARI Capabilities
@ -1368,7 +1298,6 @@ extern "C" {
#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
/*
* PC_ARI_CTL_REG(16bit):
* ARI Control
@ -1384,7 +1313,6 @@ extern "C" {
#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
/*
* PC_SEC_PCIE_CAP_REG(32bit):
* Secondary PCIE Capability Register
@ -1400,7 +1328,6 @@ extern "C" {
#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
/*
* PC_SRIOV_CAP_HDR_REG(32bit):
* SRIOV capability header register
@ -1419,7 +1346,6 @@ extern "C" {
#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
/*
* PC_SRIOV_CAP_REG(32bit):
* SRIOV Capabilities
@ -1438,7 +1364,6 @@ extern "C" {
#define PCRF_CZ_VF_MIGR_CAP_LBN 0
#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1
/*
* PC_LINK_CONTROL3_REG(32bit):
* Link Control 3.
@ -1452,7 +1377,6 @@ extern "C" {
#define PCRF_DZ_PERFORM_EQL_LBN 0
#define PCRF_DZ_PERFORM_EQL_WIDTH 1
/*
* PC_LANE_ERROR_STAT_REG(32bit):
* Lane Error Status Register.
@ -1464,7 +1388,6 @@ extern "C" {
#define PCRF_DZ_LANE_STATUS_LBN 0
#define PCRF_DZ_LANE_STATUS_WIDTH 8
/*
* PC_SRIOV_CTL_REG(16bit):
* SRIOV Control
@ -1487,7 +1410,6 @@ extern "C" {
#define PCRF_CZ_VF_EN_LBN 0
#define PCRF_CZ_VF_EN_WIDTH 1
/*
* PC_SRIOV_STAT_REG(16bit):
* SRIOV Status
@ -1502,7 +1424,6 @@ extern "C" {
#define PCRF_CZ_VF_MIGR_STAT_LBN 0
#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1
/*
* PC_LANE01_EQU_CONTROL_REG(32bit):
* Lanes 0,1 Equalization Control Register.
@ -1516,7 +1437,6 @@ extern "C" {
#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
/*
* PC_SRIOV_INITIALVFS_REG(16bit):
* SRIOV Initial VFs
@ -1531,7 +1451,6 @@ extern "C" {
#define PCRF_CZ_VF_INITIALVFS_LBN 0
#define PCRF_CZ_VF_INITIALVFS_WIDTH 16
/*
* PC_SRIOV_TOTALVFS_REG(10bit):
* SRIOV Total VFs
@ -1546,7 +1465,6 @@ extern "C" {
#define PCRF_CZ_VF_TOTALVFS_LBN 0
#define PCRF_CZ_VF_TOTALVFS_WIDTH 16
/*
* PC_SRIOV_NUMVFS_REG(16bit):
* SRIOV Number of VFs
@ -1561,7 +1479,6 @@ extern "C" {
#define PCRF_CZ_VF_NUMVFS_LBN 0
#define PCRF_CZ_VF_NUMVFS_WIDTH 16
/*
* PC_LANE23_EQU_CONTROL_REG(32bit):
* Lanes 2,3 Equalization Control Register.
@ -1575,7 +1492,6 @@ extern "C" {
#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
/*
* PC_SRIOV_FN_DPND_LNK_REG(16bit):
* SRIOV Function dependency link
@ -1590,7 +1506,6 @@ extern "C" {
#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
/*
* PC_SRIOV_1STVF_OFFSET_REG(16bit):
* SRIOV First VF Offset
@ -1605,7 +1520,6 @@ extern "C" {
#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0
#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
/*
* PC_LANE45_EQU_CONTROL_REG(32bit):
* Lanes 4,5 Equalization Control Register.
@ -1619,7 +1533,6 @@ extern "C" {
#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
/*
* PC_SRIOV_VFSTRIDE_REG(16bit):
* SRIOV VF Stride
@ -1634,7 +1547,6 @@ extern "C" {
#define PCRF_CZ_VF_VFSTRIDE_LBN 0
#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16
/*
* PC_LANE67_EQU_CONTROL_REG(32bit):
* Lanes 6,7 Equalization Control Register.
@ -1648,7 +1560,6 @@ extern "C" {
#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
/*
* PC_SRIOV_DEVID_REG(16bit):
* SRIOV VF Device ID
@ -1663,7 +1574,6 @@ extern "C" {
#define PCRF_CZ_VF_DEVID_LBN 0
#define PCRF_CZ_VF_DEVID_WIDTH 16
/*
* PC_SRIOV_SUP_PAGESZ_REG(16bit):
* SRIOV Supported Page Sizes
@ -1678,7 +1588,6 @@ extern "C" {
#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0
#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
/*
* PC_SRIOV_SYS_PAGESZ_REG(32bit):
* SRIOV System Page Size
@ -1693,7 +1602,6 @@ extern "C" {
#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0
#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
/*
* PC_SRIOV_BAR0_REG(32bit):
* SRIOV VF Bar0
@ -1716,7 +1624,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR0_IOM_LBN 0
#define PCRF_DZ_VF_BAR0_IOM_WIDTH 1
/*
* PC_SRIOV_BAR1_REG(32bit):
* SRIOV Bar1
@ -1733,7 +1640,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0
#define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32
/*
* PC_SRIOV_BAR2_REG(32bit):
* SRIOV Bar2
@ -1756,7 +1662,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR2_IOM_LBN 0
#define PCRF_DZ_VF_BAR2_IOM_WIDTH 1
/*
* PC_SRIOV_BAR3_REG(32bit):
* SRIOV Bar3
@ -1773,7 +1678,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0
#define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32
/*
* PC_SRIOV_BAR4_REG(32bit):
* SRIOV Bar4
@ -1790,7 +1694,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0
#define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32
/*
* PC_SRIOV_BAR5_REG(32bit):
* SRIOV Bar5
@ -1807,7 +1710,6 @@ extern "C" {
#define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0
#define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32
/*
* PC_SRIOV_RSVD_REG(16bit):
* Reserved register
@ -1819,7 +1721,6 @@ extern "C" {
#define PCRF_DZ_VF_RSVD_LBN 0
#define PCRF_DZ_VF_RSVD_WIDTH 16
/*
* PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
* SRIOV VF Migration State Array Offset
@ -1836,7 +1737,6 @@ extern "C" {
#define PCRF_CZ_VF_MIGR_BIR_LBN 0
#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3
/*
* PC_TPH_CAP_HDR_REG(32bit):
* TPH Capability Header Register
@ -1852,7 +1752,6 @@ extern "C" {
#define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0
#define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16
/*
* PC_TPH_REQ_CAP_REG(32bit):
* TPH Requester Capability Register
@ -1874,7 +1773,6 @@ extern "C" {
#define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0
#define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1
/*
* PC_TPH_REQ_CTL_REG(32bit):
* TPH Requester Control Register
@ -1888,7 +1786,6 @@ extern "C" {
#define PCRF_DZ_TPH_ST_MODE_LBN 0
#define PCRF_DZ_TPH_ST_MODE_WIDTH 3
/*
* PC_LTR_CAP_HDR_REG(32bit):
* Latency Tolerance Reporting Cap Header Reg
@ -1904,7 +1801,6 @@ extern "C" {
#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
/*
* PC_LTR_MAX_SNOOP_REG(32bit):
* LTR Maximum Snoop/No Snoop Register
@ -1922,7 +1818,6 @@ extern "C" {
#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
/*
* PC_ACK_LAT_TMR_REG(32bit):
* ACK latency timer & replay timer register
@ -1936,7 +1831,6 @@ extern "C" {
#define PCRF_AC_ALT_LBN 0
#define PCRF_AC_ALT_WIDTH 16
/*
* PC_OTHER_MSG_REG(32bit):
* Other message register
@ -1954,7 +1848,6 @@ extern "C" {
#define PCRF_AC_OM_CRPT0_LBN 0
#define PCRF_AC_OM_CRPT0_WIDTH 8
/*
* PC_FORCE_LNK_REG(24bit):
* Port force link register
@ -1970,7 +1863,6 @@ extern "C" {
#define PCRF_AC_LN_LBN 0
#define PCRF_AC_LN_WIDTH 8
/*
* PC_ACK_FREQ_REG(32bit):
* ACK frequency register
@ -1994,7 +1886,6 @@ extern "C" {
#define PCRF_AC_ACK_FREQ_LBN 0
#define PCRF_AC_ACK_FREQ_WIDTH 8
/*
* PC_PORT_LNK_CTL_REG(32bit):
* Port link control register
@ -2032,7 +1923,6 @@ extern "C" {
#define PCRF_AC_OMR_LBN 0
#define PCRF_AC_OMR_WIDTH 1
/*
* PC_LN_SKEW_REG(32bit):
* Lane skew register
@ -2056,7 +1946,6 @@ extern "C" {
#define PCRF_AC_LS0_LBN 0
#define PCRF_AC_LS0_WIDTH 8
/*
* PC_SYM_NUM_REG(16bit):
* Symbol number register
@ -2084,7 +1973,6 @@ extern "C" {
#define PCRF_AC_TS1_LBN 0
#define PCRF_AC_TS1_WIDTH 4
/*
* PC_SYM_TMR_FLT_MSK_REG(16bit):
* Symbol timer and Filter Mask Register
@ -2104,7 +1992,6 @@ extern "C" {
#define PCRF_CC_SI0_LBN 0
#define PCRF_CC_SI0_WIDTH 8
/*
* PC_SYM_TMR_REG(16bit):
* Symbol timer register
@ -2120,7 +2007,6 @@ extern "C" {
#define PCRF_AB_SI0_LBN 0
#define PCRF_AB_SI0_WIDTH 8
/*
* PC_FLT_MSK_REG(32bit):
* Filter Mask Register 2
@ -2132,7 +2018,6 @@ extern "C" {
#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
/*
* PC_PHY_STAT_REG(32bit):
* PHY status register
@ -2153,7 +2038,6 @@ extern "C" {
#define PCRF_AC_SSCD_LBN 0
#define PCRF_AC_SSCD_WIDTH 1
/*
* PC_PHY_CTL_REG(32bit):
* PHY control register
@ -2182,7 +2066,6 @@ extern "C" {
#define PCRF_AC_FORCE_LOS_EN_LBN 0
#define PCRF_AC_FORCE_LOS_EN_WIDTH 1
/*
* PC_DEBUG0_REG(32bit):
* Debug register 0
@ -2202,7 +2085,6 @@ extern "C" {
#define PCRF_AC_CDI00_LBN 0
#define PCRF_AC_CDI00_WIDTH 8
/*
* PC_DEBUG1_REG(32bit):
* Debug register 1
@ -2222,7 +2104,6 @@ extern "C" {
#define PCRF_AC_CDI10_LBN 0
#define PCRF_AC_CDI10_WIDTH 8
/*
* PC_XPFCC_STAT_REG(24bit):
* documentation to be written for sum_PC_XPFCC_STAT_REG
@ -2236,7 +2117,6 @@ extern "C" {
#define PCRF_AC_XPHC_LBN 0
#define PCRF_AC_XPHC_WIDTH 12
/*
* PC_XNPFCC_STAT_REG(24bit):
* documentation to be written for sum_PC_XNPFCC_STAT_REG
@ -2250,7 +2130,6 @@ extern "C" {
#define PCRF_AC_XNPHC_LBN 0
#define PCRF_AC_XNPHC_WIDTH 12
/*
* PC_XCFCC_STAT_REG(24bit):
* documentation to be written for sum_PC_XCFCC_STAT_REG
@ -2264,7 +2143,6 @@ extern "C" {
#define PCRF_AC_XCHC_LBN 0
#define PCRF_AC_XCHC_WIDTH 12
/*
* PC_Q_STAT_REG(8bit):
* documentation to be written for sum_PC_Q_STAT_REG
@ -2280,7 +2158,6 @@ extern "C" {
#define PCRF_AC_RCNR_LBN 0
#define PCRF_AC_RCNR_WIDTH 1
/*
* PC_VC_XMIT_ARB1_REG(32bit):
* VC Transmit Arbitration Register 1
@ -2289,8 +2166,6 @@ extern "C" {
#define PCR_CC_VC_XMIT_ARB1_REG 0x00000740
/* sienaa0=pci_f0_config */
/*
* PC_VC_XMIT_ARB2_REG(32bit):
* VC Transmit Arbitration Register 2
@ -2299,8 +2174,6 @@ extern "C" {
#define PCR_CC_VC_XMIT_ARB2_REG 0x00000744
/* sienaa0=pci_f0_config */
/*
* PC_VC0_P_RQ_CTL_REG(32bit):
* VC0 Posted Receive Queue Control
@ -2309,8 +2182,6 @@ extern "C" {
#define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748
/* sienaa0=pci_f0_config */
/*
* PC_VC0_NP_RQ_CTL_REG(32bit):
* VC0 Non-Posted Receive Queue Control
@ -2319,8 +2190,6 @@ extern "C" {
#define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c
/* sienaa0=pci_f0_config */
/*
* PC_VC0_C_RQ_CTL_REG(32bit):
* VC0 Completion Receive Queue Control
@ -2329,8 +2198,6 @@ extern "C" {
#define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750
/* sienaa0=pci_f0_config */
/*
* PC_GEN2_REG(32bit):
* Gen2 Register
@ -2352,7 +2219,6 @@ extern "C" {
#define PCRF_CC_NUM_FTS_LBN 0
#define PCRF_CC_NUM_FTS_WIDTH 8
#ifdef __cplusplus
}
#endif

7
sys/dev/sfxge/common/efx_rx.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_SIENA
static __checkReturn efx_rc_t
@ -150,7 +149,6 @@ siena_rx_qdestroy(
#endif /* EFSYS_OPT_SIENA */
#if EFSYS_OPT_SIENA
static const efx_rx_ops_t __efx_rx_siena_ops = {
siena_rx_init, /* erxo_init */
@ -209,7 +207,6 @@ static const efx_rx_ops_t __efx_rx_ef10_ops = {
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
efx_rx_init(
__inout efx_nic_t *enp)
@ -955,7 +952,6 @@ efx_rx_qcreate_es_super_buffer(
#endif
void
efx_rx_qdestroy(
__in efx_rxq_t *erp)
@ -1081,7 +1077,6 @@ siena_rx_scatter_enable(
}
#endif /* EFSYS_OPT_RX_SCATTER */
#define EFX_RX_LFSR_HASH(_enp, _insert) \
do { \
efx_oword_t oword; \
@ -1141,7 +1136,6 @@ siena_rx_scatter_enable(
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
#if EFSYS_OPT_RX_SCALE
static __checkReturn efx_rc_t
@ -1456,7 +1450,6 @@ siena_rx_prefix_pktlen(
return (ENOTSUP);
}
static void
siena_rx_qpost(
__in efx_rxq_t *erp,

1
sys/dev/sfxge/common/efx_sram.c
View File

@ -204,7 +204,6 @@ efx_sram_buf_tbl_clear(
EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword);
}
#if EFSYS_OPT_DIAG
static void

1
sys/dev/sfxge/common/efx_tunnel.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_TUNNEL
#if EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON

4
sys/dev/sfxge/common/efx_tx.c
View File

@ -125,7 +125,6 @@ siena_tx_qstats_update(
#endif /* EFSYS_OPT_SIENA */
#if EFSYS_OPT_SIENA
static const efx_tx_ops_t __efx_tx_siena_ops = {
siena_tx_init, /* etxo_init */
@ -234,7 +233,6 @@ static const efx_tx_ops_t __efx_tx_medford2_ops = {
};
#endif /* EFSYS_OPT_MEDFORD2 */
__checkReturn efx_rc_t
efx_tx_init(
__in efx_nic_t *enp)
@ -691,7 +689,6 @@ efx_tx_qdesc_checksum_create(
etxop->etxo_qdesc_checksum_create(etp, flags, edp);
}
#if EFSYS_OPT_QSTATS
void
efx_tx_qstats_update(
@ -707,7 +704,6 @@ efx_tx_qstats_update(
}
#endif
#if EFSYS_OPT_SIENA
static __checkReturn efx_rc_t

9
sys/dev/sfxge/common/efx_types.h
View File

@ -454,7 +454,6 @@ extern int fix_lint;
(EFX_EXTRACT8((_byte).eb_u8[0], FIX_LINT(0), FIX_LINT(7), \
_low, _high))
#define EFX_OWORD_FIELD64(_oword, _field) \
((uint32_t)EFX_EXTRACT_OWORD64(_oword, EFX_LOW_BIT(_field), \
EFX_HIGH_BIT(_field)) & EFX_MASK32(_field))
@ -483,7 +482,6 @@ extern int fix_lint;
(EFX_EXTRACT_BYTE(_byte, EFX_LOW_BIT(_field), \
EFX_HIGH_BIT(_field)) & EFX_MASK8(_field))
#define EFX_OWORD_IS_EQUAL64(_oword_a, _oword_b) \
((_oword_a).eo_u64[0] == (_oword_b).eo_u64[0] && \
(_oword_a).eo_u64[1] == (_oword_b).eo_u64[1])
@ -510,7 +508,6 @@ extern int fix_lint;
#define EFX_BYTE_IS_EQUAL(_byte_a, _byte_b) \
((_byte_a).eb_u8[0] == (_byte_b).eb_u8[0])
#define EFX_OWORD_IS_ZERO64(_oword) \
(((_oword).eo_u64[0] | \
(_oword).eo_u64[1]) == 0)
@ -537,7 +534,6 @@ extern int fix_lint;
#define EFX_BYTE_IS_ZERO(_byte) \
(((_byte).eb_u8[0]) == 0)
#define EFX_OWORD_IS_SET64(_oword) \
(((_oword).eo_u64[0] & \
(_oword).eo_u64[1]) == ~((uint64_t)0))
@ -1408,7 +1404,6 @@ extern int fix_lint;
((_oword).eo_u32[3] & \
__CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96)))))
#define EFX_SET_QWORD_BIT64(_qword, _bit) \
do { \
_NOTE(CONSTANTCONDITION) \
@ -1455,7 +1450,6 @@ extern int fix_lint;
((_qword).eq_u32[1] & \
__CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32)))))
#define EFX_SET_DWORD_BIT(_dword, _bit) \
do { \
(_dword).ed_u32[0] |= \
@ -1474,7 +1468,6 @@ extern int fix_lint;
(((_dword).ed_u32[0] & \
__CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) != 0)
#define EFX_SET_WORD_BIT(_word, _bit) \
do { \
(_word).ew_u16[0] |= \
@ -1493,7 +1486,6 @@ extern int fix_lint;
(((_word).ew_u16[0] & \
__CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0)))) != 0)
#define EFX_SET_BYTE_BIT(_byte, _bit) \
do { \
(_byte).eb_u8[0] |= \
@ -1512,7 +1504,6 @@ extern int fix_lint;
(((_byte).eb_u8[0] & \
__NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0)))) != 0)
#define EFX_OR_OWORD64(_oword1, _oword2) \
do { \
(_oword1).eo_u64[0] |= (_oword2).eo_u64[0]; \

1
sys/dev/sfxge/common/hunt_impl.h
View File

@ -62,7 +62,6 @@ extern "C" {
#define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
/* NIC */
extern __checkReturn efx_rc_t

1
sys/dev/sfxge/common/hunt_nic.c
View File

@ -251,5 +251,4 @@ hunt_board_cfg(
return (rc);
}
#endif /* EFSYS_OPT_HUNTINGTON */

3
sys/dev/sfxge/common/mcdi_mon.c
View File

@ -210,7 +210,6 @@ mcdi_mon_ev(
return (rc);
}
static __checkReturn efx_rc_t
efx_mcdi_read_sensors(
__in efx_nic_t *enp,
@ -408,7 +407,6 @@ efx_mcdi_sensor_info_page(
/* Copy an entry for all but the highest bit set. */
while (mask_copy) {
if (mask_copy == (1U << MC_CMD_SENSOR_PAGE0_NEXT)) {
/* Only next page bit set. */
mask_copy = 0;
@ -656,7 +654,6 @@ mcdi_mon_cfg_free(
}
}
#endif /* EFSYS_OPT_MON_STATS */
#endif /* EFSYS_OPT_MON_MCDI */

1
sys/dev/sfxge/common/mcdi_mon.h
View File

@ -51,7 +51,6 @@ mcdi_mon_cfg_build(
mcdi_mon_cfg_free(
__in efx_nic_t *enp);
extern __checkReturn efx_rc_t
mcdi_mon_ev(
__in efx_nic_t *enp,

4
sys/dev/sfxge/common/medford2_impl.h
View File

@ -39,23 +39,19 @@
extern "C" {
#endif
#ifndef ER_EZ_TX_PIOBUF_SIZE
#define ER_EZ_TX_PIOBUF_SIZE 4096
#endif
#define MEDFORD2_PIOBUF_NBUFS (16)
#define MEDFORD2_PIOBUF_SIZE (ER_EZ_TX_PIOBUF_SIZE)
#define MEDFORD2_MIN_PIO_ALLOC_SIZE (MEDFORD2_PIOBUF_SIZE / 32)
extern __checkReturn efx_rc_t
medford2_board_cfg(
__in efx_nic_t *enp);
#ifdef __cplusplus
}
#endif

2
sys/dev/sfxge/common/medford2_nic.c
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_MEDFORD2
static __checkReturn efx_rc_t
@ -89,7 +88,6 @@ medford2_board_cfg(
* See efx_mcdi_request_errcode() for MCDI error translations.
*/
if (EFX_PCI_FUNCTION_IS_VF(encp)) {
/*
* Interrupt testing does not work for VFs on Medford2.

4
sys/dev/sfxge/common/medford_impl.h
View File

@ -37,23 +37,19 @@
extern "C" {
#endif
#ifndef ER_EZ_TX_PIOBUF_SIZE
#define ER_EZ_TX_PIOBUF_SIZE 4096
#endif
#define MEDFORD_PIOBUF_NBUFS (16)
#define MEDFORD_PIOBUF_SIZE (ER_EZ_TX_PIOBUF_SIZE)
#define MEDFORD_MIN_PIO_ALLOC_SIZE (MEDFORD_PIOBUF_SIZE / 32)
extern __checkReturn efx_rc_t
medford_board_cfg(
__in efx_nic_t *enp);
#ifdef __cplusplus
}
#endif

2
sys/dev/sfxge/common/medford_nic.c
View File

@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
#include "efx.h"
#include "efx_impl.h"
#if EFSYS_OPT_MEDFORD
static __checkReturn efx_rc_t
@ -85,7 +84,6 @@ medford_board_cfg(
* See efx_mcdi_request_errcode() for MCDI error translations.
*/
if (EFX_PCI_FUNCTION_IS_VF(encp)) {
/*
* Interrupt testing does not work for VFs. See bug50084 and

1
sys/dev/sfxge/common/siena_flash.h
View File

@ -55,7 +55,6 @@
#define SIENA_MC_BOOT_MAGIC (0x51E4A001)
#define SIENA_MC_BOOT_VERSION (1)
/*Structures supporting an arbitrary number of binary blobs in the flash image
intended to house code and tables for the satellite cpus*/
/*thanks to random.org for:*/

1
sys/dev/sfxge/common/siena_impl.h
View File

@ -54,7 +54,6 @@ extern "C" {
#define SIENA_NVRAM_CHUNK 0x80
extern __checkReturn efx_rc_t
siena_nic_probe(
__in efx_nic_t *enp);

2
sys/dev/sfxge/common/siena_mcdi.c
View File

@ -51,7 +51,6 @@ __FBSDID("$FreeBSD$");
? MC_SMEM_P0_STATUS_OFST >> 2 \
: MC_SMEM_P1_STATUS_OFST >> 2)
void
siena_mcdi_send_request(
__in efx_nic_t *enp,
@ -265,5 +264,4 @@ siena_mcdi_get_timeout(
*timeoutp = SIENA_MCDI_CMD_TIMEOUT_US;
}
#endif /* EFSYS_OPT_SIENA && EFSYS_OPT_MCDI */

1
sys/dev/sfxge/common/siena_nic.c
View File

@ -749,7 +749,6 @@ siena_nic_test_tables(
return (rc);
}
__checkReturn efx_rc_t
siena_nic_register_test(
__in efx_nic_t *enp)

2
sys/dev/sfxge/common/siena_nvram.c
View File

@ -261,7 +261,6 @@ siena_nvram_type_to_partn(
return (ENOTSUP);
}
#if EFSYS_OPT_DIAG
__checkReturn efx_rc_t
@ -299,7 +298,6 @@ siena_nvram_test(
#endif /* EFSYS_OPT_DIAG */
#define SIENA_DYNAMIC_CFG_SIZE(_nitems) \
(sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \
sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0])))

3
sys/dev/sfxge/sfxge.c
View File

@ -85,7 +85,6 @@ __FBSDID("$FreeBSD$");
MALLOC_DEFINE(M_SFXGE, "sfxge", "Solarflare 10GigE driver");
SYSCTL_NODE(_hw, OID_AUTO, sfxge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
"SFXGE driver parameters");
@ -325,7 +324,6 @@ sfxge_stop(struct sfxge_softc *sc)
sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
}
static int
sfxge_vpd_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc)
{
@ -385,7 +383,6 @@ sfxge_private_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc)
}
}
static int
sfxge_if_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data)
{

1
sys/dev/sfxge/sfxge.h
View File

@ -110,7 +110,6 @@
#define SFXGE_ETHERTYPE_LOOPBACK 0x9000 /* Xerox loopback */
#define SFXGE_MAGIC_RESERVED 0x8000
#define SFXGE_MAGIC_DMAQ_LABEL_WIDTH 6

1
sys/dev/sfxge/sfxge_ev.c
View File

@ -675,7 +675,6 @@ static const efx_ev_callbacks_t sfxge_ev_callbacks = {
.eec_link_change = sfxge_ev_link_change,
};
int
sfxge_ev_qpoll(struct sfxge_evq *evq)
{

1
sys/dev/sfxge/sfxge_intr.c
View File

@ -204,7 +204,6 @@ sfxge_intr_bus_enable(struct sfxge_softc *sc)
#else
bus_bind_intr(sc->dev, table[index].eih_res, index);
#endif
}
return (0);

2
sys/dev/sfxge/sfxge_mcdi.c
View File

@ -280,7 +280,6 @@ sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip)
* Both ports will see ->emt_exception callbacks on the next MCDI poll
*/
if (ip->u.mcdi.cmd == MC_CMD_REBOOT) {
EFSYS_PROBE(mcdi_ioctl_mc_reboot);
/* sfxge_t->s_state_lock held */
(void) sfxge_schedule_reset(sc);
@ -299,7 +298,6 @@ sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip)
return (rc);
}
int
sfxge_mcdi_init(struct sfxge_softc *sc)
{

2
sys/dev/sfxge/sfxge_nvram.c
View File

@ -30,7 +30,6 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/types.h>
#include <sys/malloc.h>
@ -109,7 +108,6 @@ sfxge_nvram_rw(struct sfxge_softc *sc, sfxge_ioc_t *ip, efx_nvram_type_t type,
return (rc);
}
static int
sfxge_nvram_erase(struct sfxge_softc *sc, efx_nvram_type_t type)
{

1
sys/dev/sfxge/sfxge_rx.c
View File

@ -65,7 +65,6 @@ __FBSDID("$FreeBSD$");
#include "common/efx.h"
#include "sfxge.h"
#include "sfxge_rx.h"

8
sys/dev/sfxge/sfxge_tx.c
View File

@ -92,7 +92,6 @@ __FBSDID("$FreeBSD$");
#include "sfxge.h"
#include "sfxge_tx.h"
#define SFXGE_PARAM_TX_DPL_GET_MAX SFXGE_PARAM(tx_dpl_get_max)
static int sfxge_tx_dpl_get_max = SFXGE_TX_DPL_GET_PKT_LIMIT_DEFAULT;
TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_MAX, &sfxge_tx_dpl_get_max);
@ -123,7 +122,6 @@ SYSCTL_INT(_hw_sfxge, OID_AUTO, tso_fw_assisted, CTLFLAG_RDTUN,
&sfxge_tso_fw_assisted, 0,
"Bitmask of FW-assisted TSO allowed to use if supported by NIC firmware");
static const struct {
const char *name;
size_t offset;
@ -143,7 +141,6 @@ static const struct {
SFXGE_TX_STAT(tx_netdown_drops, netdown_drops),
};
/* Forward declarations. */
static void sfxge_tx_qdpl_service(struct sfxge_txq *txq);
static void sfxge_tx_qlist_post(struct sfxge_txq *txq);
@ -802,7 +799,6 @@ sfxge_if_qflush(struct ifnet *ifp)
* The fields are 8-bit, but it's ok, no header may be longer than 255 bytes.
*/
#define TSO_MBUF_PROTO(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[0])
/* We abuse l5hlen here because PH_loc can hold only 64 bits of data */
#define TSO_MBUF_FLAGS(_mbuf) ((_mbuf)->m_pkthdr.l5hlen)
@ -991,7 +987,6 @@ static const struct tcphdr *tso_tcph(const struct sfxge_tso_state *tso)
}
#endif
/* Size of preallocated TSO header buffers. Larger blocks must be
* allocated from the heap.
*/
@ -1092,14 +1087,12 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso,
}
#endif
if (tso->fw_assisted &&
__predict_false(tso->tcph_off >
encp->enc_tx_tso_tcp_header_offset_limit)) {
tso->fw_assisted = 0;
}
#if !SFXGE_TX_PARSE_EARLY
KASSERT(mbuf->m_len >= tso->tcph_off,
("network header is fragmented in mbuf"));
@ -2007,7 +2000,6 @@ sfxge_tx_fini(struct sfxge_softc *sc)
sc->txq_count = 0;
}
int
sfxge_tx_init(struct sfxge_softc *sc)
{

2
sys/dev/sfxge/sfxge_tx.h
View File

@ -121,7 +121,6 @@ struct sfxge_tx_dpl {
* high watermark */
};
#define SFXGE_TX_BUFFER_SIZE 0x400
#define SFXGE_TX_HEADER_SIZE 0x100
#define SFXGE_TX_COPY_THRESHOLD 0x200
@ -170,7 +169,6 @@ enum sfxge_txq_type {
#define SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(_txq) \
mtx_assert(&(_txq)->lock, MA_NOTOWNED)
struct sfxge_txq {
/* The following fields should be written very rarely */
struct sfxge_softc *sc;