Add support for UART found in the Ingenic XBurst system on chips.
These CPUs has non-standard UART enable bit hidden in the UART FIFO Control Register. Sponsored by: DARPA, AFRL
This commit is contained in:
parent
310dc5a403
commit
b192bae67e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308750
@ -156,6 +156,9 @@
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#define FIFO_XMT_RST FCR_XMT_RST
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#define FCR_DMA 0x08
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#define FIFO_DMA_MODE FCR_DMA
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#ifdef CPU_XBURST
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#define FCR_UART_ON 0x10
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#endif
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#define FCR_RX_LOW 0x00
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#define FIFO_RX_LOW FCR_RX_LOW
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#define FCR_RX_MEDL 0x40
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@ -198,6 +198,9 @@ ns8250_flush(struct uart_bas *bas, int what)
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uint8_t fcr;
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fcr = FCR_ENABLE;
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#ifdef CPU_XBURST
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fcr |= FCR_UART_ON;
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#endif
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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@ -268,6 +271,10 @@ ns8250_probe(struct uart_bas *bas)
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{
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u_char val;
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#ifdef CPU_XBURST
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uart_setreg(bas, REG_FCR, FCR_UART_ON);
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#endif
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/* Check known 0 bits that don't depend on DLAB. */
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val = uart_getreg(bas, REG_IIR);
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if (val & 0x30)
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@ -289,7 +296,7 @@ static void
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ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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u_char ier;
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u_char ier, val;
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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@ -306,7 +313,11 @@ ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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uart_barrier(bas);
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/* Disable the FIFO (if present). */
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uart_setreg(bas, REG_FCR, 0);
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val = 0;
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#ifdef CPU_XBURST
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val = FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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/* Set RTS & DTR. */
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@ -461,6 +472,9 @@ ns8250_bus_attach(struct uart_softc *sc)
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ns8250->mcr = uart_getreg(bas, REG_MCR);
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ns8250->fcr = FCR_ENABLE;
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#ifdef CPU_XBURST
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ns8250->fcr |= FCR_UART_ON;
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#endif
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if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
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&ivar)) {
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if (UART_FLAGS_FCR_RX_LOW(ivar))
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@ -753,6 +767,7 @@ ns8250_bus_probe(struct uart_softc *sc)
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struct uart_bas *bas;
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int count, delay, error, limit;
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uint8_t lsr, mcr, ier;
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uint8_t val;
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ns8250 = (struct ns8250_softc *)sc;
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bas = &sc->sc_bas;
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@ -786,7 +801,11 @@ ns8250_bus_probe(struct uart_softc *sc)
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* done. Since this is the first time we enable the FIFOs, we reset
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* them.
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*/
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uart_setreg(bas, REG_FCR, FCR_ENABLE);
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val = FCR_ENABLE;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
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/*
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@ -800,7 +819,11 @@ ns8250_bus_probe(struct uart_softc *sc)
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return (0);
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}
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uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
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val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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count = 0;
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@ -810,7 +833,11 @@ ns8250_bus_probe(struct uart_softc *sc)
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error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
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if (error) {
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uart_setreg(bas, REG_MCR, mcr);
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uart_setreg(bas, REG_FCR, 0);
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val = 0;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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goto describe;
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}
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@ -840,7 +867,11 @@ ns8250_bus_probe(struct uart_softc *sc)
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ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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uart_setreg(bas, REG_IER, ier);
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uart_setreg(bas, REG_MCR, mcr);
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uart_setreg(bas, REG_FCR, 0);
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val = 0;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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count = 0;
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goto describe;
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