- Move bus dependent defines to {isa,cbus}_dmareg.h.
- Use isa/isareg.h rather than <arch>/isa/isa.h. Tested on: i386, pc98
This commit is contained in:
Yoshihiro Takahashi
parent
8253c060cf
commit
b22bf66063
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=146214
@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/pmap.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <dev/ic/i8237.h>
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#include <isa/isa_dmareg.h>
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#include <machine/bus.h>
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static bus_dma_tag_t dma_tag[8];
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@ -49,15 +49,12 @@
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#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
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/* CPU Board */
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#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
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#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
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#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */
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#define IO_KBD 0x060 /* 8042 Keyboard */
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#define IO_RTC 0x070 /* RTC */
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#define IO_NMI IO_RTC /* NMI Control */
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#define IO_DMAPG 0x080 /* DMA Page Registers */
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#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
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#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
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/* Cards */
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#define IO_VGA 0x3C0 /* E/VGA Ports */
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@ -57,9 +57,9 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <amd64/isa/isa.h>
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#include <dev/ic/i8237.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <isa/isa_dmareg.h>
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#define ISARAM_END 0x1000000
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@ -9,26 +9,3 @@
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#define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */
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#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */
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#define DMA37MD_READ 0x08 /* write the device, read memory operation */
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#ifndef PC98
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/*
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
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/*
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** Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
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#endif
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@ -53,15 +53,12 @@
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#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
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/* CPU Board */
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#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
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#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
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#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */
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#define IO_KBD 0x060 /* 8042 Keyboard */
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#define IO_RTC 0x070 /* RTC */
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#define IO_NMI IO_RTC /* NMI Control */
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#define IO_DMAPG 0x080 /* DMA Page Registers */
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#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
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#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
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/* Cards */
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#define IO_VGA 0x3C0 /* E/VGA Ports */
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@ -57,9 +57,9 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <i386/isa/isa.h>
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#include <dev/ic/i8237.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <isa/isa_dmareg.h>
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static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
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@ -55,7 +55,7 @@
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#include <vm/pmap.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <dev/ic/i8237.h>
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#include <isa/isa_dmareg.h>
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#include <machine/bus.h>
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static bus_dma_tag_t dma_tag[8];
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56
sys/isa/isa_dmareg.h
Normal file
56
sys/isa/isa_dmareg.h
Normal file
@ -0,0 +1,56 @@
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/*-
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* Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ISA_ISA_DMAREG_H_
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#define _ISA_ISA_DMAREG_H_
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#include <dev/ic/i8237.h>
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#define IO_DMA1 0x00 /* 8237A DMA Controller #1 */
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#define IO_DMA2 0xC0 /* 8237A DMA Controller #2 */
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/*
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* Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
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/*
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* Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
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#endif /* _ISA_ISA_DMAREG_H_ */
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@ -53,15 +53,12 @@
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#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
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/* CPU Board */
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#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
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#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
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#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */
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#define IO_KBD 0x060 /* 8042 Keyboard */
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#define IO_RTC 0x070 /* RTC */
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#define IO_NMI IO_RTC /* NMI Control */
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#define IO_DMAPG 0x080 /* DMA Page Registers */
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#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
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#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
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/* Cards */
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/* 0x100 - 0x16F Open */
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@ -140,8 +137,6 @@
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#define IO_ASCSIZE 5 /* AmiScan GI1904-based hand scanner */
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#define IO_CGASIZE 12 /* CGA controllers */
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#define IO_DMASIZE 16 /* 8237 DMA controllers */
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#define IO_DPGSIZE 32 /* 74LS612 DMA page registers */
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#define IO_EISASIZE 256 /* EISA controllers */
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#define IO_FDCSIZE 8 /* Nec765 floppy controllers */
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#define IO_GAMSIZE 16 /* AT compatible game controllers */
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@ -53,7 +53,6 @@
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/* PC98 IO address ... very dirty (^_^; */
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#define IO_ICU1 0x000 /* 8259A Interrupt Controller #1 */
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#define IO_DMA 0x001 /* 8237A DMA Controller */
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#define IO_ICU2 0x008 /* 8259A Interrupt Controller #2 */
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#define IO_RTC 0x020 /* 4990A RTC */
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#define IO_SYSPORT 0x031 /* 8255A System Port */
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@ -60,18 +60,9 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <dev/ic/i8237.h>
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#include <isa/isavar.h>
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#include <pc98/cbus/cbus.h>
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/*
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */
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#define DMA1_STATUS (IO_DMA + 0x10) /* status register */
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#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */
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#define DMA1_MODE (IO_DMA + 0x16) /* mode register */
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#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */
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#include <pc98/cbus/cbus_dmareg.h>
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static int isa_dmarangecheck(caddr_t va, u_int length, int chan);
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44
sys/pc98/cbus/cbus_dmareg.h
Normal file
44
sys/pc98/cbus/cbus_dmareg.h
Normal file
@ -0,0 +1,44 @@
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/*-
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* Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PC98_CBUS_CBUS_DMAREG_H_
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#define _PC98_CBUS_CBUS_DMAREG_H_
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#include <dev/ic/i8237.h>
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#define IO_DMA 0x01 /* 8237A DMA Controller */
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/*
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* Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */
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#define DMA1_STATUS (IO_DMA + 0x10) /* status register */
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#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */
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#define DMA1_MODE (IO_DMA + 0x16) /* mode register */
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#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */
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#endif /* _PC98_CBUS_CBUS_DMAREG_H_ */
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