Add emmc support for Rockchip RK3399 SoC.
Tested on NanoPC-T4 board. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D20156
This commit is contained in:
Ganbold Tsagaankhuu
parent
ea01660f1c
commit
b24594e544
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=350162
@ -52,6 +52,14 @@ __FBSDID("$FreeBSD$");
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef EXT_RESOURCES
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/extres/phy/phy.h>
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#endif
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#include <dev/mmc/bridge.h>
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#include <dev/sdhci/sdhci.h>
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@ -61,16 +69,37 @@ __FBSDID("$FreeBSD$");
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#include "opt_mmccam.h"
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#ifdef EXT_RESOURCES
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#include "clkdev_if.h"
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#include "syscon_if.h"
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#endif
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#define MAX_SLOTS 6
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#define SDHCI_FDT_ARMADA38X 1
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#define SDHCI_FDT_GENERIC 2
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#define SDHCI_FDT_XLNX_ZY7 3
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#define SDHCI_FDT_QUALCOMM 4
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#define SDHCI_FDT_RK3399 5
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#ifdef EXT_RESOURCES
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#define RK3399_GRF_EMMCCORE_CON0 0xf000
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#define RK3399_CORECFG_BASECLKFREQ 0xff00
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#define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7)
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#define RK3399_CORECFG_TUNINGCOUNT 0x3f
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#define RK3399_GRF_EMMCCORE_CON11 0xf02c
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#define RK3399_CORECFG_CLOCKMULTIPLIER 0xff
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#define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
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#define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask))
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#define EMMCCARDCLK_ID 1000
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#endif
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X },
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{ "sdhci_generic", SDHCI_FDT_GENERIC },
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{ "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM },
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{ "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 },
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{ "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 },
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{ NULL, 0 }
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};
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@ -90,8 +119,209 @@ struct sdhci_fdt_softc {
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bool wp_inverted; /* WP pin is inverted */
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bool no_18v; /* No 1.8V support */
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#ifdef EXT_RESOURCES
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clk_t clk_xin; /* xin24m fixed clock */
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clk_t clk_ahb; /* ahb clock */
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phy_t phy; /* phy to be used */
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#endif
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};
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#ifdef EXT_RESOURCES
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struct rk3399_emmccardclk_sc {
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device_t clkdev;
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bus_addr_t reg;
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};
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static int
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rk3399_emmccardclk_init(struct clknode *clk, device_t dev)
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{
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static clknode_method_t rk3399_emmccardclk_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, rk3399_emmccardclk_init),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class,
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rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc),
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clknode_class);
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static int
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rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells,
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phandle_t *cells, struct clknode **clk)
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{
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if (ncells == 0)
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*clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID);
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else
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return (ERANGE);
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if (*clk == NULL)
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return (ENXIO);
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return (0);
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}
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static void
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sdhci_init_rk3399_emmccardclk(device_t dev)
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{
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struct clknode_init_def def;
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struct rk3399_emmccardclk_sc *sc;
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struct clkdom *clkdom;
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struct clknode *clk;
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clk_t clk_parent;
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bus_addr_t paddr;
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bus_size_t psize;
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const char **clknames;
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phandle_t node;
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int i, nclocks, ncells, error;
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node = ofw_bus_get_node(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return;
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}
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0 || ncells != 2) {
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device_printf(dev, "couldn't find parent clocks\n");
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return;
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}
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nclocks = ofw_bus_string_list_to_array(node, "clock-output-names",
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&clknames);
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/* No clocks to export */
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if (nclocks <= 0)
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return;
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if (nclocks != 1) {
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device_printf(dev, "Having %d clock instead of 1, aborting\n",
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nclocks);
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return;
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}
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clkdom = clkdom_create(dev);
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clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map);
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memset(&def, 0, sizeof(def));
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def.id = EMMCCARDCLK_ID;
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def.name = clknames[0];
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def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
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for (i = 0; i < ncells; i++) {
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error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", error);
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return;
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}
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def.parent_names[i] = clk_get_name(clk_parent);
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if (bootverbose)
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device_printf(dev, "clk parent: %s\n",
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def.parent_names[i]);
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clk_release(clk_parent);
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}
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def.parent_cnt = ncells;
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clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def);
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if (clk == NULL) {
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device_printf(dev, "cannot create clknode\n");
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return;
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}
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sc = clknode_get_softc(clk);
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sc->reg = paddr;
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sc->clkdev = device_get_parent(dev);
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clknode_register(clkdom, clk);
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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return;
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}
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if (bootverbose)
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clkdom_dump(clkdom);
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}
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static int
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sdhci_init_rk3399(device_t dev)
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{
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struct sdhci_fdt_softc *sc = device_get_softc(dev);
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struct syscon *grf = NULL;
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phandle_t node;
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uint64_t freq;
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uint32_t mask, val;
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int error;
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/* Get and activate clocks */
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error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin);
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if (error != 0) {
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device_printf(dev, "cannot get xin clock\n");
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return (ENXIO);
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}
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error = clk_enable(sc->clk_xin);
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if (error != 0) {
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device_printf(dev, "cannot enable xin clock\n");
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return (ENXIO);
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}
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error = clk_get_freq(sc->clk_xin, &freq);
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if (error != 0) {
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device_printf(dev, "cannot get xin clock frequency\n");
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return (ENXIO);
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}
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error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot get ahb clock\n");
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return (ENXIO);
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}
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error = clk_enable(sc->clk_ahb);
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if (error != 0) {
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device_printf(dev, "cannot enable ahb clock\n");
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return (ENXIO);
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}
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/* Register clock */
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sdhci_init_rk3399_emmccardclk(dev);
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/* Enable PHY */
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error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy);
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if (error != 0) {
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device_printf(dev, "Could not get phy\n");
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return (ENXIO);
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}
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error = phy_enable(sc->phy);
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if (error != 0) {
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device_printf(dev, "Could not enable phy\n");
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return (ENXIO);
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}
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/* Get syscon */
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node = ofw_bus_get_node(dev);
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if (OF_hasprop(node, "arasan,soc-ctl-syscon") &&
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syscon_get_by_ofw_property(dev, node,
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"arasan,soc-ctl-syscon", &grf) != 0) {
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device_printf(dev, "cannot get grf driver handle\n");
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return (ENXIO);
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}
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/* Disable clock multiplier */
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mask = RK3399_CORECFG_CLOCKMULTIPLIER;
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val = 0;
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SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val);
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/* Set base clock frequency */
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mask = RK3399_CORECFG_BASECLKFREQ;
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val = SHIFTIN((freq + (1000000 / 2)) / 1000000,
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RK3399_CORECFG_BASECLKFREQ);
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SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val);
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return (0);
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}
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#endif
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static uint8_t
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sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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@ -212,6 +442,9 @@ sdhci_fdt_probe(device_t dev)
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sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
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device_set_desc(dev, "Qualcomm FDT SDHCI controller");
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break;
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case SDHCI_FDT_RK3399:
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device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller");
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break;
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case SDHCI_FDT_XLNX_ZY7:
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sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
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device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
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@ -255,6 +488,18 @@ sdhci_fdt_attach(device_t dev)
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return (ENOMEM);
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}
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#ifdef EXT_RESOURCES
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
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SDHCI_FDT_RK3399) {
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/* Initialize SDHCI */
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err = sdhci_init_rk3399(dev);
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if (err != 0) {
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device_printf(dev, "Cannot init RK3399 SDHCI\n");
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return (err);
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}
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}
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#endif
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/* Scan all slots. */
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slots = sc->num_slots; /* number of slots determined in probe(). */
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sc->num_slots = 0;
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