- Added support for 5709S/5716S PHYs.
Submitted by: pyunyh MFC after: 2 weeks
This commit is contained in:
David Christensen
parent
6b4391d786
commit
b249ff39a4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=205299
@ -75,6 +75,7 @@ struct brgphy_softc {
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#define BRGPHY_5706S 0x0001
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#define BRGPHY_5708S 0x0002
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#define BRGPHY_NOANWAIT 0x0004
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#define BRGPHY_5709S 0x0008
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int bce_phy_flags; /* PHY flags transferred from the MAC driver */
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};
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@ -139,6 +140,7 @@ static const struct mii_phydesc brgphys[] = {
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
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MII_PHY_DESC(BROADCOM2, BCM5906),
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MII_PHY_END
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};
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@ -216,30 +218,34 @@ brgphy_attach(device_t dev)
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break;
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case MII_OUI_xxBROADCOM:
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_BCM5706:
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case MII_MODEL_xxBROADCOM_BCM5714:
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/*
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* The 5464 PHY used in the 5706 supports both copper
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* and fiber interfaces over GMII. Need to check the
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* shadow registers to see which mode is actually
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* in effect, and therefore whether we have 5706C or
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* 5706S.
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*/
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PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_MODE_CTRL);
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if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
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BRGPHY_SHADOW_1C_ENA_1000X) {
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bsc->serdes_flags |= BRGPHY_5706S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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}
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break;
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case MII_MODEL_xxBROADCOM_BCM5706:
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case MII_MODEL_xxBROADCOM_BCM5714:
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/*
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* The 5464 PHY used in the 5706 supports both copper
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* and fiber interfaces over GMII. Need to check the
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* shadow registers to see which mode is actually
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* in effect, and therefore whether we have 5706C or
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* 5706S.
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*/
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PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_MODE_CTRL);
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if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
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BRGPHY_SHADOW_1C_ENA_1000X) {
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bsc->serdes_flags |= BRGPHY_5706S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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}
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break;
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} break;
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case MII_OUI_xxBROADCOM_ALT1:
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switch (bsc->mii_model) {
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case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
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bsc->serdes_flags |= BRGPHY_5708S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
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bsc->serdes_flags |= BRGPHY_5708S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
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bsc->serdes_flags |= BRGPHY_5709S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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} break;
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default:
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device_printf(dev, "Unrecognized OUI for PHY!\n");
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@ -631,6 +637,7 @@ brgphy_status(struct mii_softc *sc)
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
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xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
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/* Check for MRBE auto-negotiated speed results. */
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switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
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case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
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mii->mii_media_active |= IFM_10_FL; break;
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@ -642,11 +649,40 @@ brgphy_status(struct mii_softc *sc)
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mii->mii_media_active |= IFM_2500_SX; break;
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}
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/* Check for MRBE auto-negotiated duplex results. */
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if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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}
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} else if (bsc->serdes_flags & BRGPHY_5709S) {
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/* Select GP Status Block of the AN MMD, get autoneg results. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
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xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
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/* Restore IEEE0 block (assumed in all brgphy(4) code). */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
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/* Check for MRBE auto-negotiated speed results. */
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switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
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case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
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mii->mii_media_active |= IFM_10_FL; break;
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case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
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mii->mii_media_active |= IFM_100_FX; break;
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case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
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mii->mii_media_active |= IFM_1000_SX; break;
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case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
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mii->mii_media_active |= IFM_2500_SX; break;
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}
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/* Check for MRBE auto-negotiated duplex results. */
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if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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}
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}
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#if 0
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@ -967,6 +1003,7 @@ brgphy_reset(struct mii_softc *sc)
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struct bge_softc *bge_sc = NULL;
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struct bce_softc *bce_sc = NULL;
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struct ifnet *ifp;
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int val;
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/* Perform a standard PHY reset. */
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mii_phy_reset(sc);
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@ -1089,7 +1126,49 @@ brgphy_reset(struct mii_softc *sc)
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PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
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BRGPHY_5708S_DIG_PG0);
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}
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} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
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} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
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(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
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/* Select the SerDes Digital block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
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val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
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val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
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val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
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PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
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/* Select the Over 1G block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
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/* Enable autoneg "Next Page" to advertise 2.5G support. */
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val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
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if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
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val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
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else
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val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
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PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
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/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
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/* Enable MRBE speed autoneg. */
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val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
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val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
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BRGPHY_MRBE_MSG_PG5_NP_T2;
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PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
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/* Select the Clause 73 User B0 block of the AN MMD. */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
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/* Enable MRBE speed autoneg. */
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PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
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BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
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BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
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/* Restore IEEE0 block (assumed in all brgphy(4) code). */
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PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
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} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
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if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
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(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
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brgphy_fixup_disable_early_dac(sc);
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@ -359,6 +359,61 @@
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/* End: PHY register values for the 5708S SerDes PHY */
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/*******************************************************/
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/*******************************************************/
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/* Begin: PHY register values for the 5709S SerDes PHY */
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/*******************************************************/
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/* 5709S SerDes "General Purpose Status" Registers */
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#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120
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#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300
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#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00
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#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008
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#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004
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#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001
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/* 5709S SerDes "SerDes Digital" Registers */
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#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300
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#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010
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#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010
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#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001
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/* 5709S SerDes "Over 1G" Registers */
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#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320
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#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19
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/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */
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#define BRGPHY_BLOCK_ADDR_MRBE 0x8350
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#define BRGPHY_MRBE_MSG_PG5_NP 0x10
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#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001
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#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0001
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/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
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#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370
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#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12
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#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000
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#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000
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#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000
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/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
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#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0
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/* 5709S SerDes "Combo IEEE 0" Registers */
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#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0
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#define BRGPHY_ADDR_EXT 0x1E
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#define BRGPHY_BLOCK_ADDR 0x1F
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#define BRGPHY_ADDR_EXT_AN_MMD 0x3800
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/*******************************************************/
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/* End: PHY register values for the 5709S SerDes PHY */
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/*******************************************************/
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#define BRGPHY_INTRS \
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~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
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@ -150,6 +150,7 @@ model xxBROADCOM_ALT1 BCM5722 0x002d BCM5722 10/100/1000baseTX PHY
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model xxBROADCOM_ALT1 BCM5784 0x003a BCM5784 10/100/1000baseTX PHY
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model xxBROADCOM_ALT1 BCM5709C 0x003c BCM5709C 10/100/1000baseTX PHY
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model xxBROADCOM_ALT1 BCM5761 0x003d BCM5761 10/100/1000baseTX PHY
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model xxBROADCOM_ALT1 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY
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model BROADCOM2 BCM5906 0x0004 BCM5906 10/100baseTX PHY
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/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
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