Pull in r175962 from upstream llvm trunk:
X86: Disable cmov-memory patterns on subtargets without cmov. Fixes PR15115. For the i386 arch, this should enable cmov instructions only on -march=pentiumpro and higher. Since our default CPU is i486, cmov instructions will now be disabled by default. MFC after: 1 week
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=247205
@ -1076,12 +1076,14 @@ def : Pat<(X86cmp GR64:$src1, 0),
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// inverted.
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multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
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Instruction Inst64> {
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def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
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(Inst16 GR16:$src2, addr:$src1)>;
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def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
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(Inst32 GR32:$src2, addr:$src1)>;
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def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
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(Inst64 GR64:$src2, addr:$src1)>;
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let Predicates = [HasCMov] in {
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def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
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(Inst16 GR16:$src2, addr:$src1)>;
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def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
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(Inst32 GR32:$src2, addr:$src1)>;
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def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
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(Inst64 GR64:$src2, addr:$src1)>;
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}
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}
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defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
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