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Yet another fix for configuration mechanism 1 register accesses:

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Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).
This commit is contained in:
Stefan Eßer 1997-05-26 21:52:41 +00:00
parent 64039d403f
commit b3daa02e72
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=26174
6 changed files with 30 additions and 24 deletions
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9
sys/amd64/pci/pci_bus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));

9
sys/amd64/pci/pci_cfgreg.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));

9
sys/i386/isa/pcibus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));

9
sys/i386/pci/pci_bus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));

9
sys/i386/pci/pci_cfgreg.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));

9
sys/i386/pci/pci_pir.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
* $Id: pcibus.c,v 1.38 1997/05/26 21:25:24 se Exp $
*
*/
@ -59,9 +59,10 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, (1 << 31) |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
outl(CONF1_ADDR_PORT, (1 << 31)
| (bus << 16) | (slot << 11)
| (func << 8) | (reg & ~0x03));
dataport = CONF1_DATA_PORT + (reg & 0x03);
break;
case 2:
outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));