bge: clean up empty lines in .c and .h files
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3a1ecfe33d
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=365122
@ -240,7 +240,6 @@ static const struct bge_type {
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{ FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
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{ FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
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{ FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
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{ 0, 0 }
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};
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@ -255,7 +254,6 @@ static const struct bge_vendor {
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{ SK_VENDORID, "SysKonnect" },
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{ TC_VENDORID, "3Com" },
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{ FJTSU_VENDORID, "Fujitsu" },
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{ 0, NULL }
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};
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@ -330,7 +328,6 @@ static const struct bge_revision {
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{ BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
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{ BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
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{ BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
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{ 0, NULL }
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};
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@ -363,7 +360,6 @@ static const struct bge_revision bge_majorrevs[] = {
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{ BGE_ASICREV_BCM5719, "unknown BCM5719" },
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{ BGE_ASICREV_BCM5720, "unknown BCM5720" },
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{ BGE_ASICREV_BCM5762, "unknown BCM5762" },
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{ 0, NULL }
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};
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@ -145,7 +145,6 @@
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#define BGE_EXT_SSRAM 0x00020000
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#define BGE_EXT_SSRAM_END 0x000FFFFF
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/*
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* BCM570x register offsets. These are memory mapped registers
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* which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
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@ -462,7 +461,6 @@
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#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
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#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
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#ifndef PCIM_CMD_MWIEN
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#define PCIM_CMD_MWIEN 0x0010
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#endif
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@ -902,7 +900,6 @@
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#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
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#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
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/* MI communication register */
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#define BGE_MICOMM_DATA 0x0000FFFF
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#define BGE_MICOMM_REG 0x001F0000
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@ -927,7 +924,6 @@
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#define BGE_MIMODE_500KHZ_CONST 0x00008000
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#define BGE_MIMODE_BASE 0x000C0000
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/*
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* Send data initiator control registers.
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*/
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@ -1157,7 +1153,6 @@
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#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
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#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
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/* Receive List Placement mode register */
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#define BGE_RXLPMODE_RESET 0x00000001
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#define BGE_RXLPMODE_ENABLE 0x00000002
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@ -1208,7 +1203,6 @@
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#define BGE_RDBDI_RETURN_PROD15 0x24BC
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#define BGE_RDBDI_HWDIAG 0x24C0
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/* Receive Data and Receive BD Initiator Mode register */
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#define BGE_RDBDIMODE_RESET 0x00000001
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#define BGE_RDBDIMODE_ENABLE 0x00000002
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@ -1221,7 +1215,6 @@
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#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
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#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
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/*
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* Receive Data Completion Control registers
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*/
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@ -1410,7 +1403,6 @@
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#define BGE_HCC_TX_BD_CONS14 0x3CF8
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#define BGE_HCC_TX_BD_CONS15 0x3CFC
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/* Host coalescing mode register */
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#define BGE_HCCMODE_RESET 0x00000001
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#define BGE_HCCMODE_ENABLE 0x00000002
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@ -1544,7 +1536,6 @@
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#define BGE_BMANSTAT_ERRO 0x00000004
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#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
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/*
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* Read DMA Control registers
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*/
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@ -1652,7 +1643,6 @@
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#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
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/*
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* RX CPU registers
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*/
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@ -1748,7 +1738,6 @@
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#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
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#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
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/*
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* Low priority mailbox registers
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*/
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@ -1924,7 +1913,6 @@
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#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
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#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
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/*
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* DMA Completion registers
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*/
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@ -1934,7 +1922,6 @@
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#define BGE_DMACMODE_RESET 0x00000001
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#define BGE_DMACMODE_ENABLE 0x00000002
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/*
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* General control registers.
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*/
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@ -2427,7 +2414,6 @@ struct bge_status_block {
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#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
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#define BGE_STATFLAG_ERROR 0x00000004
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/*
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* Broadcom Vendor ID
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* (Note: the BCM570x still defaults to the Alteon PCI vendor ID
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@ -2666,7 +2652,6 @@ struct bge_rx_mac_stats {
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bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
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};
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/* Statistics maintained MAC Transmit block. */
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struct bge_tx_mac_stats {
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bge_hostaddr ifHCOutOctets;
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