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Fix an off-by-one bug for the number of slots on a PCI/PCI-X bus.

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We failed to setup PCI devices on slot 31 and that's where the
SATA controller is for the P2020 eval board.
This commit is contained in:
Marcel Moolenaar 2010-03-23 23:46:28 +00:00
parent b266b96af9
commit b41169fdce
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=205569
1 changed files with 8 additions and 7 deletions
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15
sys/powerpc/mpc85xx/pci_ocp.c
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@ -264,7 +264,7 @@ pci_ocp_maxslots(device_t dev)
{ {
struct pci_ocp_softc *sc = device_get_softc(dev); struct pci_ocp_softc *sc = device_get_softc(dev);
return ((sc->sc_pcie_cap) ? 0 : 30); return ((sc->sc_pcie_cap) ? 0 : 31);
} }
static uint32_t static uint32_t
@ -328,6 +328,7 @@ pci_ocp_probe(device_t dev)
return (ENXIO); return (ENXIO);
sc = device_get_softc(dev); sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_rid = 0; sc->sc_rid = 0;
sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
@ -492,7 +493,7 @@ pci_ocp_route_int(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
} }
static int static int
pci_ocp_init(struct pci_ocp_softc *sc, int bus, int maxslot) pci_ocp_init(struct pci_ocp_softc *sc, int bus, int nslots)
{ {
int secbus, slot; int secbus, slot;
int func, maxfunc; int func, maxfunc;
@ -502,7 +503,7 @@ pci_ocp_init(struct pci_ocp_softc *sc, int bus, int maxslot)
uint8_t intline, intpin; uint8_t intline, intpin;
secbus = bus; secbus = bus;
for (slot = 0; slot < maxslot; slot++) { for (slot = 0; slot < nslots; slot++) {
maxfunc = 0; maxfunc = 0;
for (func = 0; func <= maxfunc; func++) { for (func = 0; func <= maxfunc; func++) {
hdrtype = pci_ocp_read_config(sc->sc_dev, bus, slot, hdrtype = pci_ocp_read_config(sc->sc_dev, bus, slot,
@ -599,7 +600,7 @@ pci_ocp_init(struct pci_ocp_softc *sc, int bus, int maxslot)
PCIR_SUBBUS_1, 0xff, 1); PCIR_SUBBUS_1, 0xff, 1);
secbus = pci_ocp_init(sc, secbus, secbus = pci_ocp_init(sc, secbus,
(subclass == PCIS_BRIDGE_PCI) ? 31 : 1); (subclass == PCIS_BRIDGE_PCI) ? 32 : 1);
pci_ocp_write_config(sc->sc_dev, bus, slot, func, pci_ocp_write_config(sc->sc_dev, bus, slot, func,
PCIR_SUBBUS_1, secbus, 1); PCIR_SUBBUS_1, secbus, 1);
@ -721,7 +722,7 @@ pci_ocp_attach(device_t dev)
{ {
struct pci_ocp_softc *sc; struct pci_ocp_softc *sc;
uint32_t cfgreg; uint32_t cfgreg;
int error, maxslot; int error, nslots;
sc = device_get_softc(dev); sc = device_get_softc(dev);
sc->sc_dev = dev; sc->sc_dev = dev;
@ -765,8 +766,8 @@ pci_ocp_attach(device_t dev)
return (0); return (0);
} }
maxslot = (sc->sc_pcie_cap) ? 1 : 31; nslots = (sc->sc_pcie_cap) ? 1 : 32;
pci_ocp_init(sc, sc->sc_busnr, maxslot); pci_ocp_init(sc, sc->sc_busnr, nslots);
device_add_child(dev, "pci", -1); device_add_child(dev, "pci", -1);
return (bus_generic_attach(dev)); return (bus_generic_attach(dev));