Fix for control endpoint handling in the DWC OTG driver. The data
stage processing is only allowed after the setup complete event has been received. Else a race may occur and the OUT data can be corrupted. While at it ensure resetting a FIFO has the required wait loop. MFC after: 3 days
This commit is contained in:
Hans Petter Selasky
parent
af8f4185fb
commit
b4df5b00f2
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=283922
@ -180,6 +180,22 @@ dwc_otg_get_hw_ep_profile(struct usb_device *udev,
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*ppf = NULL;
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}
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static void
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dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
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{
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uint32_t temp;
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/* reset FIFO */
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DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
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/* wait for reset to complete */
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for (temp = 0; temp != 16; temp++) {
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value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
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if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
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break;
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}
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}
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static int
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dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
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{
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@ -331,12 +347,11 @@ dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
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}
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/* reset RX FIFO */
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DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
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GRSTCTL_RXFFLSH);
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dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
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if (mode != DWC_MODE_OTG) {
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/* reset all TX FIFOs */
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DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
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dwc_otg_tx_fifo_reset(sc,
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GRSTCTL_TXFIFO(0x10) |
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GRSTCTL_TXFFLSH);
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} else {
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@ -947,15 +962,21 @@ dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
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goto not_complete;
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if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
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GRXSTSRD_DPID_DATA0) {
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/* release FIFO */
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dwc_otg_common_rx_ack(sc);
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goto not_complete;
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}
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if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
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GRXSTSRD_STP_DATA) {
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if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
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GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
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/* release FIFO */
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dwc_otg_common_rx_ack(sc);
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goto not_complete;
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}
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/* release FIFO */
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dwc_otg_common_rx_ack(sc);
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return (0); /* complete */
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}
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if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
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GRXSTSRD_DPID_DATA0) {
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/* release FIFO */
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dwc_otg_common_rx_ack(sc);
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goto not_complete;
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@ -969,14 +990,6 @@ dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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/* get the packet byte count */
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count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
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/* verify data length */
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if (count != td->remainder) {
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DPRINTFN(0, "Invalid SETUP packet "
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"length, %d bytes\n", count);
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/* release FIFO */
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dwc_otg_common_rx_ack(sc);
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goto not_complete;
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}
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if (count != sizeof(req)) {
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DPRINTFN(0, "Unsupported SETUP packet "
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"length, %d bytes\n", count);
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@ -1002,43 +1015,27 @@ dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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}
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/* don't send any data by default */
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DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0),
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DXEPTSIZ_SET_NPKT(0) |
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DXEPTSIZ_SET_NBYTES(0));
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temp = sc->sc_in_ctl[0];
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/* enable IN endpoint */
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DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
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temp | DIEPCTL_EPENA);
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DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
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temp | DIEPCTL_SNAK);
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DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
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DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
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/* reset IN endpoint buffer */
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DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
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dwc_otg_tx_fifo_reset(sc,
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GRSTCTL_TXFIFO(0) |
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GRSTCTL_TXFFLSH);
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/* acknowledge RX status */
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dwc_otg_common_rx_ack(sc);
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return (0); /* complete */
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td->did_stall = 1;
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not_complete:
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/* abort any ongoing transfer, before enabling again */
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temp = sc->sc_out_ctl[0];
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temp |= DOEPCTL_EPENA |
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DOEPCTL_SNAK;
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/* enable OUT endpoint */
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DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp);
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if (!td->did_stall) {
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td->did_stall = 1;
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DPRINTFN(5, "stalling IN and OUT direction\n");
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temp = sc->sc_out_ctl[0];
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/* set stall after enabling endpoint */
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DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
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temp | DOEPCTL_STALL);
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@ -1049,13 +1046,6 @@ dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
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temp | DIEPCTL_STALL);
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}
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/* setup number of buffers to receive */
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DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
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DXEPTSIZ_SET_MULTI(3) |
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DXEPTSIZ_SET_NPKT(1) |
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DXEPTSIZ_SET_NBYTES(sizeof(req)));
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return (1); /* not complete */
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}
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@ -1499,7 +1489,9 @@ dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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/* check for SETUP packet */
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if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
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GRXSTSRD_STP_DATA) {
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GRXSTSRD_STP_DATA ||
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(sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
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GRXSTSRD_STP_COMPLETE) {
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if (td->remainder == 0) {
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/*
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* We are actually complete and have
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@ -1584,15 +1576,10 @@ dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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not_complete:
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temp = sc->sc_out_ctl[td->ep_no];
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temp |= DOEPCTL_EPENA | DOEPCTL_CNAK;
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DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp);
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/* enable SETUP and transfer complete interrupt */
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if (td->ep_no == 0) {
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DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
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DXEPTSIZ_SET_MULTI(3) |
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DXEPTSIZ_SET_NPKT(1) |
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DXEPTSIZ_SET_NBYTES(td->max_packet_size));
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} else {
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@ -1601,8 +1588,12 @@ dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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DXEPTSIZ_SET_MULTI(1) |
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DXEPTSIZ_SET_NPKT(4) |
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DXEPTSIZ_SET_NBYTES(4 *
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((td->max_packet_size + 3) & ~3)));
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((td->max_packet_size + 3) & ~3)));
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}
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temp = sc->sc_out_ctl[td->ep_no];
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DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
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DOEPCTL_EPENA | DOEPCTL_CNAK);
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return (1); /* not complete */
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}
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@ -2004,7 +1995,9 @@ dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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(GRXSTSRD_CHNUM_GET(temp) == 0)) {
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if ((temp & GRXSTSRD_PKTSTS_MASK) !=
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GRXSTSRD_STP_DATA) {
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GRXSTSRD_STP_DATA &&
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(temp & GRXSTSRD_PKTSTS_MASK) !=
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GRXSTSRD_STP_COMPLETE) {
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/* dump data - wrong direction */
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dwc_otg_common_rx_ack(sc);
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@ -2209,7 +2202,9 @@ dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
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(GRXSTSRD_CHNUM_GET(temp) == 0)) {
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if ((temp & GRXSTSRD_PKTSTS_MASK) ==
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GRXSTSRD_STP_DATA) {
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GRXSTSRD_STP_DATA ||
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(temp & GRXSTSRD_PKTSTS_MASK) ==
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GRXSTSRD_STP_COMPLETE) {
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DPRINTFN(5, "faking complete\n");
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/*
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* Race condition: We are complete!
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@ -2634,6 +2629,7 @@ dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
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/* non-data messages we simply skip */
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if (temp != GRXSTSRD_STP_DATA &&
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temp != GRXSTSRD_STP_COMPLETE &&
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temp != GRXSTSRD_OUT_DATA) {
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dwc_otg_common_rx_ack(sc);
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goto repeat;
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@ -3669,7 +3665,7 @@ dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
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/* we only reset the transmit FIFO */
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if (ep_dir) {
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DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
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dwc_otg_tx_fifo_reset(sc,
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GRSTCTL_TXFIFO(ep_no) |
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GRSTCTL_TXFFLSH);
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