Brucify.
Requested and reviewed by: bde MFC after: 2 weeks
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@ -120,7 +120,7 @@
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#define COM_C_IIR_TXRDYBUG (0x80000)
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#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
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#define COM_NOSCR(flags) ((flags) & 0x100000)
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#define COM_TI16754(flags) ((flags) & 0x200000)
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#define COM_TI16754(flags) ((flags) & 0x200000)
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#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
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#define sio_getreg(com, off) \
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@ -606,32 +606,28 @@ sioprobe(dev, xrid, rclk, noprobe)
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/* EXTRA DELAY? */
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/*
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* For the TI16754 chips set prescaler to 1 (4 is often the
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* default after-reset value), otherwise it's impossible to
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* For the TI16754 chips, set prescaler to 1 (4 is often the
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* default after-reset value) as otherwise it's impossible to
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* get highest baudrates.
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*/
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if (COM_TI16754(flags)) {
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u_char t1, t2;
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u_char cfcr, efr;
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/* Save LCR */
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t1 = sio_getreg(com, com_lctl);
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/* Enable EFR */
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sio_setreg(com, com_lctl, 0xbf);
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/* Save EFR */
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t2 = sio_getreg(com, com_iir);
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/* Unlock MCR[7] */
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sio_setreg(com, com_iir, t2 | 0x10);
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/* Disable EFR */
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sio_setreg(com, com_lctl, 0);
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/* Set prescaler to 1 */
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sio_setreg(com, com_mcr, sio_getreg(com, com_mcr) & 0x7f);
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/* Enable EFR */
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sio_setreg(com, com_lctl, 0xbf);
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/* Restore EFR */
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sio_setreg(com, com_iir, t2);
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/* Restore LCR */
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sio_setreg(com, com_lctl, t1);
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cfcr = sio_getreg(com, com_cfcr);
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sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
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efr = sio_getreg(com, com_efr);
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/* Unlock extended features to turn off prescaler. */
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sio_setreg(com, com_efr, efr | EFR_EFE);
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/* Disable EFR. */
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sio_setreg(com, com_cfcr, (cfcr != CFCR_EFR_ENABLE) ? cfcr : 0);
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/* Turn off prescaler. */
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sio_setreg(com, com_mcr,
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sio_getreg(com, com_mcr) & ~MCR_PRESCALE);
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sio_setreg(com, com_cfcr, CFCR_EFR_ENABLE);
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sio_setreg(com, com_efr, efr);
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sio_setreg(com, com_cfcr, cfcr);
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}
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/*
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* Initialize the speed and the word size and wait long enough to
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* drain the maximum of 16 bytes of junk in device output queues.
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@ -63,7 +63,7 @@
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#define FIFO_RX_MEDH 0x80
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#define FIFO_RX_HIGH 0xc0
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/* character format control register */
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/* character format control register (aka line control register) */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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@ -76,8 +76,10 @@
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
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/* modem control register */
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#define MCR_PRESCALE 0x80 /* only available on 16650 up */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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@ -105,6 +107,10 @@
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* enhanced feature register (only available on 16650 up) */
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#define com_efr com_fifo
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#define EFR_EFE 0x10 /* enhanced functions enable */
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#ifdef PC98
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/* Hardware extension mode register for RSB-2000/3000. */
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#define com_emr com_msr
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