cxgbe(4): Update all firmwares to 1.19.1.0.
These firmwares and the following list of changes are from the public ChelsioUwire-3.7.1.0 release. T6 Firmware ================================================================================ Version : 1.19.1.0 Date : 04/23/2018 ================================================================================ Fixes ----- BASE: - Fixed traffic stall when rate-limit is modified while running traffic. - Fixes a firmware crash in FW_ETH_TX_EO_WR handling. - Fixes host DCB support when FW_PORT_CMD is used. ETH: - Exit Auto-Negotiation if we don't receive base page from peer within 10s. This fixes some cases where in we keep on restarting auto negotiation without ever exiting, resulting in link failure. - Fixes an issue where VF packets counter were not increasing if VF packets coalesced WR is used by driver. OFLD: - Kernel and user mode NVMEoF performance enhancements. FOiSCSI: - Fixes fw crash when trying to connect to non-existence IPv6 iSNS target. ================================================================================ Version : 1.18.9.0 Date : 03/27/2018 ================================================================================ Fixes ----- BASE: - For Ethernet frames less than 64B, pad them with zero bytes as per IEEE spec (RFC 894). - Added a new parameter iqtype to FW_IQ_CMD to identify the ingress NIC or offload queues. This fixes an issue where driver was receiving interrupt with no new messages in queue. - FW_PARAMS_CMD processes all the valaid paramaters and returns value 0UL for any unknown parameter. OFLD: - Fixes connection failure during SRQ reuse. - Fixes incorrect cqe in case of WRITE with immediate operation. FOiSCSI: - Fixes a fw crash when wrong node-id is passed to FW_FOISCSI_CTRL_WR. FOFCoE: - Fixes a fw hang while creating NPIV. Enhancements ------------ ETH: - A new WR FW_ETH_TX_PKTS_VM_WR added to support VM packet coalescing. ================================================================================ Version : 1.18.4.0 Date : 02/28/2018 ================================================================================ Fixes ----- BASE: - Fixed Rate limiting not working for 101Mbps<=rate limit<=163Mbps range. - Fixed starting more than 32 VMs on PF4 causing firmware hang. ETH: - Fixed link failure due to FEC mismatch with optics. - Fixed link failure with link toggle stress tests. - Only BaseR FEC is supported for 50G. - Fixed a bug in next page handling which sometimes causes link down. - Fixed port down due to failre to read eeprom contents of some modules. - Fixed a bug causing adapter to fail with spider configuration. FOiSCSI: - Fixed a bug causing login failure when connecting to multiple targets. Enhancements ------------ BASE: - Added a new firmware API to retrieve the maximum temperaturethreshold for the chip (FW_PARAM_DEV_DIAG_MAXTMPTHRESH). ETH: - Added support for user to contol pause negotiation during auto negotiation. FOiSCSI: - Added a new facility to redirect few fw events to offload rx queue (based on driver's configration) - Driver can ignore providing ipv6 prefix len during ipv6 address configuration. ================================================================================ Version : 1.17.14.0 Date : 12/27/2017 ================================================================================ FIXES ----- BASE: - Fixed an FLR failure during simulteneous power up of VM. - Fixed an issue in vlan acl which was limiting vlan range to 1024. ETH: - Enabled RS-FEC for 25G active copper cable and 25GBASE-SR. - When auto negotiation is enabled, final pause settings are resolved based on local and peer pause settings. - Handle NACK for an I2C access. OFLD - Fixed rdma connection cleanup in SO adpater. - Fixed rdma connections during read invalidate. - Fixed the crash when invalid BW rate is passed to fw. - Fixed the traffic hang when BW allocation is changed from switch during traffic. FOFCoE: - Fixed an issue where initiator remains logged-in even after LLDP is disabled on switch. ENHANCEMENTS ------------ BASE: - Added support for 248 VFs. - Added fw driver periodic calibration for MC. ETH: - Added XLAUI port type support. - Added raw mac entry deletion support (FW_VI_MAC_ID_BASED_FREE). OFLD: - Inline IPSec support added (flag F_FW_ULPTX_WR_DATA indicates the inline IPSec WR). - New work request FW_RI_RDMA_WRITE_CMPL_WR (write with completion) added to T5 Firmware ================================================================================ Version : 1.19.1.0 Date : 04/23/2018 ================================================================================ Fixes ----- BASE: - Fixes a firmware crash in FW_ETH_TX_EO_WR handling. - Fixes host DCB support when FW_PORT_CMD is used. ETH: - Fixes an issue where VF packets counter were not increasing if VF packets coalesced WR is used by driver. OFLD: - Fixes an issue where fw hangs if max traffic rate passed is 0. FOiSCSI: - Fixes fw crash when trying to connect to non-existence IPv6 iSNS target. ================================================================================ Version : 1.18.9.0 Date : 03/27/2018 ================================================================================ Fixes ----- BASE: - For Ethernet frames less than 64B, pad them with zero bytes as per IEEE spec (RFC 894). - Added a new parameter iqtype to FW_IQ_CMD to identify the ingress NIC or offload queues. This fixes an issue where driver was receiving interrupt with no new messages in queue. ETH: - Pad the Ethernet packets of size less than 64B with zeros. This fixes the incorrect checksum generation of packets less then 64B. FOiSCSI: - Fixes a fw crash when wrong node-id is passed to FW_FOISCSI_CTRL_WR. FOFCoE: - Fixes a fw hang while creating NPIV. Enhancements ------------ ETH: - A new WR FW_ETH_TX_PKTS_VM_WR added to support VM packet coalescing. ================================================================================ Version : 1.18.4.0 Date : 02/28/2018 ================================================================================ Fixes ----- BASE: - Fixed starting more than 32 VMs on PF4 causing firmware hang. FOiSCSI: - Fixed a bug causing login failure when connecting to multiple targets. Enhancements ------------ BASE: - Added a new firmware API to retrieve the maximum temperaturethreshold for the chip (FW_PARAM_DEV_DIAG_MAXTMPTHRESH). ETH: - Added support for user to contol pause negotiation during auto negotiation. FOiSCSI: - Added a new facility to redirect few fw events to offload rx queue (based on driver's configration) - Driver can ignore providing ipv6 prefix len during ipv6 address configuration. ================================================================================ Version : 1.17.14.0 Date : 12/27/2017 ================================================================================ FIXES ----- BASE: - Fixed an issue in vlan acl which was limiting vlan range to 1024. ETH: - Corrected lane inversion logic. - Fixed improper LED behavior in T580 cards. - When auto negotiation is enabled, final pause settings are resolved based on local and peer pause settings. - Handle NACK for an I2C access. OFLD - Fixed rdma connections during read invalidate. FOiSCSI: - Fixed a connections hang when link is toggled frequently. FOFCoE: - Fixed an issue where initiator remains logged-in even after LLDP is disabled on switch. ENHANCEMENTS ------------ BASE: - Added support for 124 VFs. ETH: - Added XLAUI port type support. - Added raw mac entry deletion support (FW_VI_MAC_ID_BASED_FREE). OFLD: - New work request FW_RI_RDMA_WRITE_CMPL_WR (write with completion) added to optimize NVMEoF write. T4 Firmware ================================================================================ Version : 1.19.1.0 Date : 04/23/2018 ================================================================================ Fixes ----- BASE: - Fixes a firmware crash in FW_ETH_TX_EO_WR handling. - Fixes host DCB support when FW_PORT_CMD is used. FOiSCSI: - Fixes fw crash when trying to connect to non-existence IPv6 iSNS target. ================================================================================ Version : 1.18.9.0 Date : 03/27/2018 ================================================================================ Fixes ----- BASE: - Added a new paramter iqtype to FW_IQ_CMD to identify the ingress NIC or offload queues. This fixes an issue where driver was receiving interrupt with no new messages in queue. FOFCoE: - Fixes a fw hang while creating NPIV. Enhancements ------------ ETH: - A new WR FW_ETH_TX_PKTS_VM_WR added to support VM packet coalescing. ================================================================================ Version : 1.18.4.0 Date : 02/28/2018 ================================================================================ Enhancements ------------ BASE: - Added a new firmware API to retrieve the maximum temperaturethreshold for the chip (FW_PARAM_DEV_DIAG_MAXTMPTHRESH). ================================================================================ Version : 1.17.14.0 Date : 12/27/2017 ================================================================================ FIXES ----- BASE: - Fixed an issue in vlan acl which was limiting vlan range to 1024. MFC after: 3 days Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
ba405bc811
commit
b6f2c452cb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=333276
@ -1461,7 +1461,7 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.16.63.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.19.1.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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@ -1495,7 +1495,7 @@ t5fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.16.63.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.19.1.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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@ -1529,7 +1529,7 @@ t6fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t6fw.fwo"
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t6fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t6fw-1.16.63.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t6fw-1.19.1.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t6fw.fw"
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@ -3722,8 +3722,6 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
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fec = FW_PORT_CAP_FEC_RS;
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else if (lc->requested_fec & FEC_BASER_RS)
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fec = FW_PORT_CAP_FEC_BASER_RS;
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else if (lc->requested_fec & FEC_RESERVED)
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fec = FW_PORT_CAP_FEC_RESERVED;
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if (!(lc->supported & FW_PORT_CAP_ANEG) ||
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lc->requested_aneg == AUTONEG_DISABLE) {
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@ -7720,8 +7718,6 @@ static void handle_port_info(struct port_info *pi, const struct fw_port_info *p)
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fec |= FEC_RS;
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if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS)
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fec |= FEC_BASER_RS;
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if (lc->advertising & FW_PORT_CAP_FEC_RESERVED)
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fec |= FEC_RESERVED;
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lc->fec = fec;
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}
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File diff suppressed because it is too large
Load Diff
9747
sys/dev/cxgbe/firmware/t4fw-1.19.1.0.bin.uu
Normal file
9747
sys/dev/cxgbe/firmware/t4fw-1.19.1.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -118,6 +118,7 @@ enum fw_wr_opcodes {
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FW_RI_BIND_MW_WR = 0x18,
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FW_RI_FR_NSMR_WR = 0x19,
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FW_RI_FR_NSMR_TPTE_WR = 0x20,
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FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
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FW_RI_INV_LSTAG_WR = 0x1a,
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FW_RI_SEND_IMMEDIATE_WR = 0x15,
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FW_RI_ATOMIC_WR = 0x16,
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@ -666,6 +667,15 @@ struct fw_ulptx_wr {
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__u64 cookie;
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};
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/* flag for packet type - control packet (0), data packet (1)
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*/
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#define S_FW_ULPTX_WR_DATA 28
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#define M_FW_ULPTX_WR_DATA 0x1
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#define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA)
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#define G_FW_ULPTX_WR_DATA(x) \
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(((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
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#define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U)
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struct fw_tp_wr {
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__be32 op_to_immdlen;
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__be32 flowid_len16;
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@ -1815,6 +1825,35 @@ struct fw_ri_send_wr {
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#define G_FW_RI_SEND_WR_SENDOP(x) \
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(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
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struct fw_ri_rdma_write_cmpl_wr {
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__u8 opcode;
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__u8 flags;
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__u16 wrid;
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__u8 r1[3];
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__u8 len16;
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__u32 r2;
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__be32 stag_inv;
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__be32 plen;
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__be32 stag_sink;
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__be64 to_sink;
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union fw_ri_cmpl {
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struct fw_ri_immd_cmpl {
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__u8 op;
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__u8 r1[6];
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__u8 immdlen;
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__u8 data[16];
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} immd_src;
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struct fw_ri_isgl isgl_src;
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} u_cmpl;
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__be64 r3;
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#ifndef C99_NOT_SUPPORTED
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union fw_ri_write {
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struct fw_ri_immd immd_src[0];
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struct fw_ri_isgl isgl_src[0];
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} u;
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#endif
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};
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struct fw_ri_rdma_read_wr {
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__u8 opcode;
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__u8 flags;
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@ -2635,6 +2674,12 @@ struct fw_foiscsi_ctrl_wr {
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__u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
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};
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#define S_FW_FOISCSI_CTRL_WR_PORTID 1
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#define M_FW_FOISCSI_CTRL_WR_PORTID 0x7
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#define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID)
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#define G_FW_FOISCSI_CTRL_WR_PORTID(x) \
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(((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID)
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#define S_FW_FOISCSI_CTRL_WR_NO_FIN 0
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#define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1
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#define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN)
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@ -2837,6 +2882,12 @@ struct fw_coiscsi_tgt_wr {
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} conn_attr;
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};
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#define S_FW_COISCSI_TGT_WR_PORTID 0
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#define M_FW_COISCSI_TGT_WR_PORTID 0x7
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#define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID)
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#define G_FW_COISCSI_TGT_WR_PORTID(x) \
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(((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID)
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struct fw_coiscsi_tgt_conn_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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@ -2884,6 +2935,14 @@ struct fw_coiscsi_tgt_conn_wr {
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} conn_iscsi;
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};
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#define S_FW_COISCSI_TGT_CONN_WR_PORTID 0
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#define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7
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#define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
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((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID)
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#define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
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(((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \
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M_FW_COISCSI_TGT_CONN_WR_PORTID)
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#define S_FW_COISCSI_TGT_CONN_WR_FIN 0
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#define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1
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#define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN)
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@ -3022,6 +3081,12 @@ struct fw_coiscsi_stats_wr {
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} u;
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};
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#define S_FW_COISCSI_STATS_WR_PORTID 0
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#define M_FW_COISCSI_STATS_WR_PORTID 0x7
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#define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID)
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#define G_FW_COISCSI_STATS_WR_PORTID(x) \
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(((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID)
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struct fw_isns_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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@ -3049,6 +3114,12 @@ struct fw_isns_wr {
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} conn_attr;
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};
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#define S_FW_ISNS_WR_PORTID 0
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#define M_FW_ISNS_WR_PORTID 0x7
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#define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID)
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#define G_FW_ISNS_WR_PORTID(x) \
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(((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID)
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struct fw_isns_xmit_wr {
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__be32 op_to_immdlen;
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__be32 flowid_len16;
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@ -4573,6 +4644,7 @@ enum fw_caps_config_iscsi {
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enum fw_caps_config_crypto {
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FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
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FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
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FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
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};
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enum fw_caps_config_fcoe {
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@ -4693,6 +4765,7 @@ enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
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FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22,
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FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
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FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
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};
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/*
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@ -4720,6 +4793,7 @@ enum fw_params_param_dev_phyfw {
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enum fw_params_param_dev_diag {
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FW_PARAM_DEV_DIAG_TMP = 0x00,
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FW_PARAM_DEV_DIAG_VDD = 0x01,
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FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
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};
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enum fw_params_param_dev_fwcache {
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@ -5020,6 +5094,12 @@ enum fw_iq_type {
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FW_IQ_TYPE_VF_CQ
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};
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enum fw_iq_iqtype {
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FW_IQ_IQTYPE_OTHER,
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FW_IQ_IQTYPE_NIC,
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FW_IQ_IQTYPE_OFLD,
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};
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struct fw_iq_cmd {
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__be32 op_to_vfn;
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__be32 alloc_to_len16;
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@ -5226,6 +5306,12 @@ struct fw_iq_cmd {
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(((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
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#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
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#define S_FW_IQ_CMD_IQTYPE 24
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#define M_FW_IQ_CMD_IQTYPE 0x3
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#define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
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#define G_FW_IQ_CMD_IQTYPE(x) \
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(((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
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#define S_FW_IQ_CMD_FL0CNGCHMAP 20
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#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
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#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
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@ -6311,6 +6397,23 @@ struct fw_eq_ofld_cmd {
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#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
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#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
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/* Macros for VIID parsing:
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VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */
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#define S_FW_256VIID_PFN 9
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#define M_FW_256VIID_PFN 0x7
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#define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN)
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#define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
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#define S_FW_256VIID_VIVLD 8
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#define M_FW_256VIID_VIVLD 0x1
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#define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD)
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#define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
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#define S_FW_256VIID_VIN 0
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#define M_FW_256VIID_VIN 0xFF
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#define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN)
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#define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
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enum fw_vi_func {
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FW_VI_FUNC_ETH,
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FW_VI_FUNC_OFLD,
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@ -6420,6 +6523,7 @@ struct fw_vi_cmd {
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#define FW_VI_MAC_ADD_MAC 0x3FF
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#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
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#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
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#define FW_VI_MAC_ID_BASED_FREE 0x3FC
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enum fw_vi_mac_smac {
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FW_VI_MAC_MPS_TCAM_ENTRY,
|
||||
@ -6854,11 +6958,11 @@ enum fw_port_cap {
|
||||
FW_PORT_CAP_FC_RX = 0x0040,
|
||||
FW_PORT_CAP_FC_TX = 0x0080,
|
||||
FW_PORT_CAP_ANEG = 0x0100,
|
||||
FW_PORT_CAP_MDIX = 0x0200,
|
||||
FW_PORT_CAP_MDIAUTO = 0x0400,
|
||||
FW_PORT_CAP_MDIAUTO = 0x0200,
|
||||
FW_PORT_CAP_MDISTRAIGHT = 0x0400,
|
||||
FW_PORT_CAP_FEC_RS = 0x0800,
|
||||
FW_PORT_CAP_FEC_BASER_RS = 0x1000,
|
||||
FW_PORT_CAP_FEC_RESERVED = 0x2000,
|
||||
FW_PORT_CAP_FORCE_PAUSE = 0x2000,
|
||||
FW_PORT_CAP_802_3_PAUSE = 0x4000,
|
||||
FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
|
||||
};
|
||||
@ -6882,11 +6986,17 @@ enum fw_port_cap {
|
||||
(((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
|
||||
|
||||
#define S_FW_PORT_CAP_FEC 11
|
||||
#define M_FW_PORT_CAP_FEC 0x7
|
||||
#define M_FW_PORT_CAP_FEC 0x3
|
||||
#define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
|
||||
#define G_FW_PORT_CAP_FEC(x) \
|
||||
(((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
|
||||
|
||||
#define S_FW_PORT_CAP_FORCE_PAUSE 13
|
||||
#define M_FW_PORT_CAP_FORCE_PAUSE 0x1
|
||||
#define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE)
|
||||
#define G_FW_PORT_CAP_FORCE_PAUSE(x) \
|
||||
(((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
|
||||
|
||||
#define S_FW_PORT_CAP_802_3 14
|
||||
#define M_FW_PORT_CAP_802_3 0x3
|
||||
#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
|
||||
@ -6924,14 +7034,15 @@ enum fw_port_mdi {
|
||||
#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
|
||||
#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
|
||||
#define FW_PORT_CAP32_ANEG 0x00100000UL
|
||||
#define FW_PORT_CAP32_MDIX 0x00200000UL
|
||||
#define FW_PORT_CAP32_MDIAUTO 0x00400000UL
|
||||
#define FW_PORT_CAP32_MDIAUTO 0x00200000UL
|
||||
#define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
|
||||
#define FW_PORT_CAP32_FEC_RS 0x00800000UL
|
||||
#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
|
||||
#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
|
||||
#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
|
||||
#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
|
||||
#define FW_PORT_CAP32_RESERVED2 0xf0000000UL
|
||||
#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
|
||||
#define FW_PORT_CAP32_RESERVED2 0xe0000000UL
|
||||
|
||||
#define S_FW_PORT_CAP32_SPEED 0
|
||||
#define M_FW_PORT_CAP32_SPEED 0xfff
|
||||
@ -6957,6 +7068,12 @@ enum fw_port_mdi {
|
||||
#define G_FW_PORT_CAP32_ANEG(x) \
|
||||
(((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
|
||||
|
||||
#define S_FW_PORT_CAP32_FORCE_PAUSE 28
|
||||
#define M_FW_PORT_CAP32_FORCE_PAUSE 0x1
|
||||
#define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
|
||||
#define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
|
||||
(((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
|
||||
|
||||
enum fw_port_mdi32 {
|
||||
FW_PORT_CAP32_MDI_UNCHANGED,
|
||||
FW_PORT_CAP32_MDI_AUTO,
|
||||
@ -6983,6 +7100,9 @@ enum fw_port_mdi32 {
|
||||
#define CAP32_FEC(__cap32) \
|
||||
(V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
|
||||
|
||||
#define CAP32_FC(__cap32) \
|
||||
(V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
|
||||
|
||||
enum fw_port_action {
|
||||
FW_PORT_ACTION_L1_CFG = 0x0001,
|
||||
FW_PORT_ACTION_L2_CFG = 0x0002,
|
||||
@ -7483,6 +7603,7 @@ enum fw_port_type {
|
||||
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
|
||||
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
|
||||
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
|
||||
FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/
|
||||
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
|
||||
};
|
||||
|
||||
@ -8599,6 +8720,12 @@ struct fw_clip_cmd {
|
||||
(((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
|
||||
#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
|
||||
|
||||
#define S_FW_CLIP_CMD_INDEX 16
|
||||
#define M_FW_CLIP_CMD_INDEX 0x1fff
|
||||
#define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX)
|
||||
#define G_FW_CLIP_CMD_INDEX(x) \
|
||||
(((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
|
||||
|
||||
/******************************************************************************
|
||||
* F O i S C S I C O M M A N D s
|
||||
**************************************/
|
||||
@ -8621,7 +8748,8 @@ struct fw_chnet_iface_cmd {
|
||||
__be32 op_to_portid;
|
||||
__be32 retval_len16;
|
||||
__u8 subop;
|
||||
__u8 r2[3];
|
||||
__u8 r2[2];
|
||||
__u8 flags;
|
||||
__be32 ifid_ifstate;
|
||||
__be16 mtu;
|
||||
__be16 vlanid;
|
||||
@ -8636,6 +8764,22 @@ struct fw_chnet_iface_cmd {
|
||||
#define G_FW_CHNET_IFACE_CMD_PORTID(x) \
|
||||
(((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
|
||||
|
||||
#define S_FW_CHNET_IFACE_CMD_RSS_IQID 16
|
||||
#define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff
|
||||
#define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
|
||||
((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID)
|
||||
#define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
|
||||
(((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID)
|
||||
|
||||
#define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0
|
||||
#define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1
|
||||
#define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
|
||||
((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F)
|
||||
#define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
|
||||
(((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \
|
||||
M_FW_CHNET_IFACE_CMD_RSS_IQID_F)
|
||||
#define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U)
|
||||
|
||||
#define S_FW_CHNET_IFACE_CMD_IFID 8
|
||||
#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
|
||||
#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
|
||||
@ -9597,18 +9741,18 @@ enum fw_hdr_chip {
|
||||
|
||||
enum {
|
||||
T4FW_VERSION_MAJOR = 0x01,
|
||||
T4FW_VERSION_MINOR = 0x10,
|
||||
T4FW_VERSION_MICRO = 0x3f,
|
||||
T4FW_VERSION_MINOR = 0x13,
|
||||
T4FW_VERSION_MICRO = 0x01,
|
||||
T4FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T5FW_VERSION_MAJOR = 0x01,
|
||||
T5FW_VERSION_MINOR = 0x10,
|
||||
T5FW_VERSION_MICRO = 0x3f,
|
||||
T5FW_VERSION_MINOR = 0x13,
|
||||
T5FW_VERSION_MICRO = 0x01,
|
||||
T5FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T6FW_VERSION_MAJOR = 0x01,
|
||||
T6FW_VERSION_MINOR = 0x10,
|
||||
T6FW_VERSION_MICRO = 0x3f,
|
||||
T6FW_VERSION_MINOR = 0x13,
|
||||
T6FW_VERSION_MICRO = 0x01,
|
||||
T6FW_VERSION_BUILD = 0x00,
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
11462
sys/dev/cxgbe/firmware/t5fw-1.19.1.0.bin.uu
Normal file
11462
sys/dev/cxgbe/firmware/t5fw-1.19.1.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
12280
sys/dev/cxgbe/firmware/t6fw-1.19.1.0.bin.uu
Normal file
12280
sys/dev/cxgbe/firmware/t6fw-1.19.1.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
# Chelsio T6 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2014-2017 Chelsio Communications. All rights reserved.
|
||||
# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
|
||||
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
|
||||
@ -150,6 +150,9 @@
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
# ULPRX iSCSI Page Sizes
|
||||
reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
|
||||
# LE IPv4 compression disabled
|
||||
@ -177,10 +180,10 @@
|
||||
# iscsi force cmd mode.
|
||||
# Enable iscsi cmp mode.
|
||||
# MC configuration
|
||||
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC
|
||||
|
||||
# HMA configuration
|
||||
hma_size = 64 # Size (in MBs) of host memory expected
|
||||
hma_size = 92 # Size (in MBs) of host memory expected
|
||||
hma_regions = stag,pbl,rq # What all regions to place in host memory
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
@ -409,7 +412,7 @@
|
||||
nserver = 496 # number of server region entries
|
||||
nhash = 12288 # number of hash region entries
|
||||
nhpfilter = 64 # number of high priority filter region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
@ -571,7 +574,7 @@
|
||||
|
||||
[fini]
|
||||
version = 0x1425001c
|
||||
checksum = 0x8136d0f8
|
||||
checksum = 0x64f3def4
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
@ -4083,8 +4083,6 @@ init_l1cfg(struct port_info *pi)
|
||||
lc->requested_fec = FEC_RS;
|
||||
else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS)
|
||||
lc->requested_fec = FEC_BASER_RS;
|
||||
else if (lc->advertising & FW_PORT_CAP_FEC_RESERVED)
|
||||
lc->requested_fec = FEC_RESERVED;
|
||||
else
|
||||
lc->requested_fec = 0;
|
||||
}
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER= 1.16.63.0
|
||||
T4FW_VER= 1.19.1.0
|
||||
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES+= t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER= 1.16.63.0
|
||||
T5FW_VER= 1.19.1.0
|
||||
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES+= t5fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T6FW_VER= 1.16.63.0
|
||||
T6FW_VER= 1.19.1.0
|
||||
FIRMWS+= t6fw.fw:t6fw:${T6FW_VER}
|
||||
CLEANFILES+= t6fw.fw
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user