arm64: Make local stores observable before sending IPIs
Add a synchronizing instruction to flush and wait until the local CPU's writes are observable to other CPUs before sending IPIs. This fixes an issue where recipient CPUs doing a rendezvous could enter the rendezvous handling code before the initiator's writes to the smp_rv_* variables were visible. This manifested as a system hang, where a single CPU's increment of smp_rv_waiters[0] actually happened "before" the initiator's zeroing of that field, so all CPUs were stuck with the field appearing to be at ncpus - 1. Reviewed by: andrew, markj Approved by: scottl (implicit) MFC after: 1 week Sponsored by: Ampere Computing, Inc. Differential Revision: https://reviews.freebsd.org/D25798
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=364794
@ -304,6 +304,13 @@ pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
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{
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KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
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/*
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* Ensure that this CPU's stores will be visible to IPI
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* recipients before starting to send the interrupts.
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*/
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dsb(ishst);
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PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
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}
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