Add support for Allwinner A83T CPU frequency scaling.
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parent
b3868b9f16
commit
b78c83e321
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=305512
@ -47,8 +47,42 @@ __FBSDID("$FreeBSD$");
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#include <dev/extres/clk/clk_mux.h>
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#define CPU_CLK_SRC_SEL_WIDTH 2
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#define CPU_CLK_SRC_SEL_SHIFT 16
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#define A10_CPU_CLK_SRC_SEL_WIDTH 2
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#define A10_CPU_CLK_SRC_SEL_SHIFT 16
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#define A83T_Cx_CLK_SRC_SEL_WIDTH 1
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#define A83T_C0_CLK_SRC_SEL_SHIFT 12
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#define A83T_C1_CLK_SRC_SEL_SHIFT 28
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struct aw_cpuclk_config {
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u_int width;
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u_int shift;
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};
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static struct aw_cpuclk_config a10_config = {
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.width = A10_CPU_CLK_SRC_SEL_WIDTH,
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.shift = A10_CPU_CLK_SRC_SEL_SHIFT,
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};
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static struct aw_cpuclk_config a83t_c0_config = {
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.width = A83T_Cx_CLK_SRC_SEL_WIDTH,
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.shift = A83T_C0_CLK_SRC_SEL_SHIFT,
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};
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static struct aw_cpuclk_config a83t_c1_config = {
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.width = A83T_Cx_CLK_SRC_SEL_WIDTH,
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.shift = A83T_C1_CLK_SRC_SEL_SHIFT,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-cpu-clk", (uintptr_t)&a10_config },
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{ "allwinner,sun8i-a83t-c0cpu-clk", (uintptr_t)&a83t_c0_config },
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{ "allwinner,sun8i-a83t-c1cpu-clk", (uintptr_t)&a83t_c1_config },
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{ NULL, (uintptr_t)NULL }
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};
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#define CPUCLK_CONF(d) \
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(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
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static int
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aw_cpuclk_probe(device_t dev)
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@ -56,7 +90,7 @@ aw_cpuclk_probe(device_t dev)
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-cpu-clk"))
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if (CPUCLK_CONF(dev) == NULL)
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return (ENXIO);
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device_set_desc(dev, "Allwinner CPU Clock");
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@ -68,6 +102,7 @@ aw_cpuclk_attach(device_t dev)
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{
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struct clk_mux_def def;
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struct clkdom *clkdom;
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struct aw_cpuclk_config *conf;
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bus_addr_t paddr;
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bus_size_t psize;
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phandle_t node;
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@ -75,6 +110,7 @@ aw_cpuclk_attach(device_t dev)
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clk_t clk;
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node = ofw_bus_get_node(dev);
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conf = CPUCLK_CONF(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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@ -105,8 +141,8 @@ aw_cpuclk_attach(device_t dev)
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}
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def.clkdef.parent_cnt = ncells;
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def.offset = paddr;
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def.shift = CPU_CLK_SRC_SEL_SHIFT;
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def.width = CPU_CLK_SRC_SEL_WIDTH;
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def.shift = conf->shift;
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def.width = conf->width;
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error = clk_parse_ofw_clk_name(dev, node, &def.clkdef.name);
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if (error != 0) {
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@ -157,6 +157,17 @@ __FBSDID("$FreeBSD$");
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#define A80_PLL4_FACTOR_N (0xff << 8)
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#define A80_PLL4_FACTOR_N_SHIFT 8
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#define A83T_PLLCPUX_LOCK_TIME (0x7 << 24)
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#define A83T_PLLCPUX_LOCK_TIME_SHIFT 24
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#define A83T_PLLCPUX_CLOCK_OUTPUT_DIS (1 << 20)
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#define A83T_PLLCPUX_OUT_EXT_DIVP (1 << 16)
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#define A83T_PLLCPUX_FACTOR_N (0xff << 8)
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#define A83T_PLLCPUX_FACTOR_N_SHIFT 8
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#define A83T_PLLCPUX_FACTOR_N_MIN 12
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#define A83T_PLLCPUX_FACTOR_N_MAX 125
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#define A83T_PLLCPUX_POSTDIV_M (0x3 << 0)
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#define A83T_PLLCPUX_POSTDIV_M_SHIFT 0
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#define CLKID_A10_PLL3_1X 0
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#define CLKID_A10_PLL3_2X 1
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@ -202,6 +213,7 @@ enum aw_pll_type {
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AWPLL_A31_PLL6,
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AWPLL_A64_PLLHSIC,
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AWPLL_A80_PLL4,
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AWPLL_A83T_PLLCPUX,
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AWPLL_H3_PLL1,
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};
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@ -824,6 +836,46 @@ a64_pllhsic_init(device_t dev, bus_addr_t reg, struct clknode_init_def *def)
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return (0);
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}
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static int
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a83t_pllcpux_recalc(struct aw_pll_sc *sc, uint64_t *freq)
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{
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uint32_t val, n, p;
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DEVICE_LOCK(sc);
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PLL_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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n = (val & A83T_PLLCPUX_FACTOR_N) >> A83T_PLLCPUX_FACTOR_N_SHIFT;
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p = (val & A83T_PLLCPUX_OUT_EXT_DIVP) ? 4 : 1;
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*freq = (*freq * n) / p;
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return (0);
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}
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static int
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a83t_pllcpux_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout,
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int flags)
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{
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uint32_t val;
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u_int n;
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n = *fout / fin;
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if (n < A83T_PLLCPUX_FACTOR_N_MIN || n > A83T_PLLCPUX_FACTOR_N_MAX)
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return (EINVAL);
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DEVICE_LOCK(sc);
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PLL_READ(sc, &val);
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val &= ~A83T_PLLCPUX_FACTOR_N;
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val |= (n << A83T_PLLCPUX_FACTOR_N_SHIFT);
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val &= ~A83T_PLLCPUX_CLOCK_OUTPUT_DIS;
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PLL_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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return (0);
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}
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#define PLL(_type, _recalc, _set_freq, _init) \
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[(_type)] = { \
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.recalc = (_recalc), \
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@ -842,6 +894,7 @@ static struct aw_pll_funcs aw_pll_func[] = {
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PLL(AWPLL_A31_PLL1, a31_pll1_recalc, NULL, NULL),
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PLL(AWPLL_A31_PLL6, a31_pll6_recalc, NULL, a31_pll6_init),
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PLL(AWPLL_A80_PLL4, a80_pll4_recalc, NULL, NULL),
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PLL(AWPLL_A83T_PLLCPUX, a83t_pllcpux_recalc, a83t_pllcpux_set_freq, NULL),
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PLL(AWPLL_A64_PLLHSIC, a64_pllhsic_recalc, NULL, a64_pllhsic_init),
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PLL(AWPLL_H3_PLL1, a23_pll1_recalc, h3_pll1_set_freq, NULL),
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};
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@ -856,6 +909,7 @@ static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun6i-a31-pll1-clk", AWPLL_A31_PLL1 },
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{ "allwinner,sun6i-a31-pll6-clk", AWPLL_A31_PLL6 },
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{ "allwinner,sun8i-a23-pll1-clk", AWPLL_A23_PLL1 },
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{ "allwinner,sun8i-a83t-pllcpux-clk", AWPLL_A83T_PLLCPUX },
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{ "allwinner,sun8i-h3-pll1-clk", AWPLL_H3_PLL1 },
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{ "allwinner,sun9i-a80-pll4-clk", AWPLL_A80_PLL4 },
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{ "allwinner,sun50i-a64-pllhsic-clk", AWPLL_A64_PLLHSIC },
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@ -27,6 +27,18 @@
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*/
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/ {
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cpus {
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cpu@0 {
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clocks = <&c0_cpux_clk>;
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clock-latency = <2000000>;
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};
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cpu@100 {
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clocks = <&c1_cpux_clk>;
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clock-latency = <2000000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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@ -38,6 +50,38 @@
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};
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clocks {
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pll_c0cpux: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-pllcpux-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll_c0cpux";
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};
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pll_c1cpux: clk@01c20004 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-pllcpux-clk";
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reg = <0x01c20004 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll_c1cpux";
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};
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c0_cpux_clk: c0clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-c0cpu-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M>, <&pll_c0cpux>;
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clock-output-names = "c0_cpux";
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};
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c1_cpux_clk: c1clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a83t-c1cpu-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M>, <&pll_c1cpux>;
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clock-output-names = "c1_cpux";
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};
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/* cpus_clk compatible in gnu dt is incorrect */
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cpus_clk: clk@01f01400 {
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compatible = "allwinner,sun8i-a83t-cpus-clk";
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@ -29,6 +29,32 @@
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#include "sun8i-a83t-sinovoip-bpi-m3.dts"
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#include "a83t.dtsi"
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/ {
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cpus {
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cpu@0 {
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cpu-supply = <®_dcdc2>;
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operating-points = <
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/* kHz uV */
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1200000 840000
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1008000 840000
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648000 840000
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408000 840000
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>;
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};
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cpu@100 {
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cpu-supply = <®_dcdc3>;
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operating-points = <
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/* kHz uV */
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1200000 840000
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1008000 840000
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648000 840000
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408000 840000
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>;
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};
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};
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};
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&ehci0 {
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status = "okay";
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};
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@ -115,6 +141,16 @@
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <1>;
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regulators {
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reg_dcdc2: dcdc2 {
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regulator-name = "dcdc2";
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};
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reg_dcdc3: dcdc3 {
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regulator-name = "dcdc3";
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};
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};
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};
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};
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