Import of Binutils from the FSF 2.15 branch (just post-.0 release).
These bits are taken from the FSF anoncvs repo on 23-May-2004 04:41:00 UTC.
This commit is contained in:
David E. O'Brien
parent
ac1a00f2eb
commit
b7e4108c6b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/binutils/dist/; revision=179404
2701
contrib/binutils/bfd/coff-mips.c
Normal file
2701
contrib/binutils/bfd/coff-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
127
contrib/binutils/bfd/cpu-mips.c
Normal file
127
contrib/binutils/bfd/cpu-mips.c
Normal file
@ -0,0 +1,127 @@
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/* bfd back-end for mips support
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Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
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2002, 2003 Free Software Foundation, Inc.
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Written by Steve Chamberlain of Cygnus Support.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "bfd.h"
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#include "sysdep.h"
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#include "libbfd.h"
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static const bfd_arch_info_type *mips_compatible
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(const bfd_arch_info_type *, const bfd_arch_info_type *);
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/* The default routine tests bits_per_word, which is wrong on mips as
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mips word size doesn't correlate with reloc size. */
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static const bfd_arch_info_type *
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mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
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{
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if (a->arch != b->arch)
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return NULL;
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/* Machine compatibility is checked in
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_bfd_mips_elf_merge_private_bfd_data. */
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return a;
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}
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#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
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{ \
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BITS_WORD, /* bits in a word */ \
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BITS_ADDR, /* bits in an address */ \
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8, /* 8 bits in a byte */ \
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bfd_arch_mips, \
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NUMBER, \
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"mips", \
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PRINT, \
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3, \
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DEFAULT, \
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mips_compatible, \
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bfd_default_scan, \
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NEXT, \
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}
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enum
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{
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I_mips3000,
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I_mips3900,
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I_mips4000,
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I_mips4010,
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I_mips4100,
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I_mips4111,
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I_mips4120,
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I_mips4300,
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I_mips4400,
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I_mips4600,
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I_mips4650,
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I_mips5000,
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I_mips5400,
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I_mips5500,
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I_mips6000,
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I_mips7000,
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I_mips8000,
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I_mips10000,
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I_mips12000,
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I_mips16,
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I_mips5,
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I_mipsisa32,
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I_mipsisa32r2,
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I_mipsisa64,
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I_mipsisa64r2,
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I_sb1,
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
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N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
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N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)),
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N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
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N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)),
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N (64, 64, bfd_mach_mips4111, "mips:4111", FALSE, NN(I_mips4111)),
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N (64, 64, bfd_mach_mips4120, "mips:4120", FALSE, NN(I_mips4120)),
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N (64, 64, bfd_mach_mips4300, "mips:4300", FALSE, NN(I_mips4300)),
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N (64, 64, bfd_mach_mips4400, "mips:4400", FALSE, NN(I_mips4400)),
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N (64, 64, bfd_mach_mips4600, "mips:4600", FALSE, NN(I_mips4600)),
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N (64, 64, bfd_mach_mips4650, "mips:4650", FALSE, NN(I_mips4650)),
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N (64, 64, bfd_mach_mips5000, "mips:5000", FALSE, NN(I_mips5000)),
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N (64, 64, bfd_mach_mips5400, "mips:5400", FALSE, NN(I_mips5400)),
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N (64, 64, bfd_mach_mips5500, "mips:5500", FALSE, NN(I_mips5500)),
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N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
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N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
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N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
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N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
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N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
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N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
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N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)),
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N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)),
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N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
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N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
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N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
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N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
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};
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/* The default architecture is mips:3000, but with a machine number of
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zero. This lets the linker distinguish between a default setting
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of mips, and an explicit setting of mips:3000. */
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const bfd_arch_info_type bfd_mips_arch =
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N (32, 32, 0, "mips", TRUE, &arch_info_struct[0]);
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1618
contrib/binutils/bfd/elf32-mips.c
Normal file
1618
contrib/binutils/bfd/elf32-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
2815
contrib/binutils/bfd/elf64-mips.c
Normal file
2815
contrib/binutils/bfd/elf64-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
1983
contrib/binutils/bfd/elfn32-mips.c
Normal file
1983
contrib/binutils/bfd/elfn32-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
9234
contrib/binutils/bfd/elfxx-mips.c
Normal file
9234
contrib/binutils/bfd/elfxx-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
126
contrib/binutils/bfd/elfxx-mips.h
Normal file
126
contrib/binutils/bfd/elfxx-mips.h
Normal file
@ -0,0 +1,126 @@
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/* MIPS ELF specific backend routines.
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Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
|
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|
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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GNU General Public License for more details.
|
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|
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
|
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "elf/common.h"
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#include "elf/internal.h"
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extern bfd_boolean _bfd_mips_elf_new_section_hook
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(bfd *, asection *);
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extern void _bfd_mips_elf_symbol_processing
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(bfd *, asymbol *);
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extern bfd_boolean _bfd_mips_elf_name_local_section_symbols
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(bfd *);
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extern bfd_boolean _bfd_mips_elf_section_processing
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(bfd *, Elf_Internal_Shdr *);
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extern bfd_boolean _bfd_mips_elf_section_from_shdr
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(bfd *, Elf_Internal_Shdr *, const char *);
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extern bfd_boolean _bfd_mips_elf_fake_sections
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(bfd *, Elf_Internal_Shdr *, asection *);
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extern bfd_boolean _bfd_mips_elf_section_from_bfd_section
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(bfd *, asection *, int *);
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extern bfd_boolean _bfd_mips_elf_add_symbol_hook
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(bfd *, struct bfd_link_info *, Elf_Internal_Sym *,
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const char **, flagword *, asection **, bfd_vma *);
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extern bfd_boolean _bfd_mips_elf_link_output_symbol_hook
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(struct bfd_link_info *, const char *, Elf_Internal_Sym *,
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asection *, struct elf_link_hash_entry *);
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extern bfd_boolean _bfd_mips_elf_create_dynamic_sections
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(bfd *, struct bfd_link_info *);
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extern bfd_boolean _bfd_mips_elf_check_relocs
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(bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *);
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extern bfd_boolean _bfd_mips_elf_adjust_dynamic_symbol
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(struct bfd_link_info *, struct elf_link_hash_entry *);
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extern bfd_boolean _bfd_mips_elf_always_size_sections
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(bfd *, struct bfd_link_info *);
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extern bfd_boolean _bfd_mips_elf_size_dynamic_sections
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(bfd *, struct bfd_link_info *);
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extern bfd_boolean _bfd_mips_elf_relocate_section
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(bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
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Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
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extern bfd_boolean _bfd_mips_elf_finish_dynamic_symbol
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(bfd *, struct bfd_link_info *, struct elf_link_hash_entry *,
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Elf_Internal_Sym *);
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extern bfd_boolean _bfd_mips_elf_finish_dynamic_sections
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(bfd *, struct bfd_link_info *);
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extern void _bfd_mips_elf_final_write_processing
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(bfd *, bfd_boolean);
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extern int _bfd_mips_elf_additional_program_headers
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(bfd *);
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extern bfd_boolean _bfd_mips_elf_modify_segment_map
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(bfd *, struct bfd_link_info *);
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extern asection * _bfd_mips_elf_gc_mark_hook
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(asection *, struct bfd_link_info *, Elf_Internal_Rela *,
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struct elf_link_hash_entry *, Elf_Internal_Sym *);
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extern bfd_boolean _bfd_mips_elf_gc_sweep_hook
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(bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *);
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extern void _bfd_mips_elf_copy_indirect_symbol
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(const struct elf_backend_data *, struct elf_link_hash_entry *,
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struct elf_link_hash_entry *);
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extern void _bfd_mips_elf_hide_symbol
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(struct bfd_link_info *, struct elf_link_hash_entry *, bfd_boolean);
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extern bfd_boolean _bfd_mips_elf_ignore_discarded_relocs
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(asection *);
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extern bfd_boolean _bfd_mips_elf_find_nearest_line
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(bfd *, asection *, asymbol **, bfd_vma, const char **,
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const char **, unsigned int *);
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extern bfd_boolean _bfd_mips_elf_set_section_contents
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(bfd *, asection *, const void *, file_ptr, bfd_size_type);
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extern bfd_byte *_bfd_elf_mips_get_relocated_section_contents
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(bfd *, struct bfd_link_info *, struct bfd_link_order *,
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bfd_byte *, bfd_boolean, asymbol **);
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extern struct bfd_link_hash_table *_bfd_mips_elf_link_hash_table_create
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(bfd *);
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||||
extern bfd_boolean _bfd_mips_elf_final_link
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||||
(bfd *, struct bfd_link_info *);
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extern bfd_boolean _bfd_mips_elf_merge_private_bfd_data
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(bfd *, bfd *);
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||||
extern bfd_boolean _bfd_mips_elf_set_private_flags
|
||||
(bfd *, flagword);
|
||||
extern bfd_boolean _bfd_mips_elf_print_private_bfd_data
|
||||
(bfd *, void *);
|
||||
extern bfd_boolean _bfd_mips_elf_discard_info
|
||||
(bfd *, struct elf_reloc_cookie *, struct bfd_link_info *);
|
||||
extern bfd_boolean _bfd_mips_elf_write_section
|
||||
(bfd *, asection *, bfd_byte *);
|
||||
|
||||
extern bfd_boolean _bfd_mips_elf_read_ecoff_info
|
||||
(bfd *, asection *, struct ecoff_debug_info *);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf_gprel16_with_gp
|
||||
(bfd *, asymbol *, arelent *, asection *, bfd_boolean, void *, bfd_vma);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf32_gprel16_reloc
|
||||
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf_hi16_reloc
|
||||
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf_got16_reloc
|
||||
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf_lo16_reloc
|
||||
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
|
||||
extern bfd_reloc_status_type _bfd_mips_elf_generic_reloc
|
||||
(bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
|
||||
extern unsigned long _bfd_elf_mips_mach
|
||||
(flagword);
|
||||
extern bfd_boolean _bfd_mips_relax_section
|
||||
(bfd *, asection *, struct bfd_link_info *, bfd_boolean *);
|
||||
extern bfd_vma _bfd_mips_elf_sign_extend
|
||||
(bfd_vma, int);
|
||||
|
||||
extern struct bfd_elf_special_section const _bfd_mips_elf_special_sections[];
|
||||
#define elf_backend_name_local_section_symbols \
|
||||
_bfd_mips_elf_name_local_section_symbols
|
||||
#define elf_backend_special_sections _bfd_mips_elf_special_sections
|
||||
12
contrib/binutils/bfd/hosts/mipsbsd.h
Normal file
12
contrib/binutils/bfd/hosts/mipsbsd.h
Normal file
@ -0,0 +1,12 @@
|
||||
#include <machine/param.h>
|
||||
#include <machine/vmparam.h>
|
||||
#undef ALIGN
|
||||
|
||||
#define HOST_PAGE_SIZE NBPG
|
||||
/* #define HOST_SEGMENT_SIZE NBPG -- we use HOST_DATA_START_ADDR */
|
||||
#define HOST_MACHINE_ARCH bfd_arch_mips
|
||||
/* #define HOST_MACHINE_MACHINE */
|
||||
|
||||
#define HOST_TEXT_START_ADDR USRTEXT
|
||||
#define HOST_STACK_END_ADDR USRSTACK
|
||||
#define NO_CORE_COMMAND
|
||||
10
contrib/binutils/bfd/hosts/mipsmach3.h
Normal file
10
contrib/binutils/bfd/hosts/mipsmach3.h
Normal file
@ -0,0 +1,10 @@
|
||||
#include <machine/vmparam.h>
|
||||
#include <machine/machparam.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#define HOST_PAGE_SIZE NBPG
|
||||
/* #define HOST_SEGMENT_SIZE NBPG */
|
||||
#define HOST_MACHINE_ARCH bfd_arch_mips
|
||||
#define HOST_TEXT_START_ADDR USRTEXT
|
||||
#define HOST_DATA_START_ADDR USRDATA
|
||||
#define HOST_STACK_END_ADDR USRSTACK
|
||||
12
contrib/binutils/bfd/hosts/news-mips.h
Normal file
12
contrib/binutils/bfd/hosts/news-mips.h
Normal file
@ -0,0 +1,12 @@
|
||||
/* Sony News running NewsOS 3.2. */
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <machine/vmparam.h>
|
||||
|
||||
#define HOST_PAGE_SIZE NBPG
|
||||
|
||||
#define HOST_MACHINE_ARCH bfd_arch_mips
|
||||
|
||||
#define HOST_TEXT_START_ADDR USRTEXT
|
||||
#define HOST_DATA_START_ADDR USRDATA
|
||||
#define HOST_STACK_END_ADDR USRSTACK
|
||||
486
contrib/binutils/bfd/mipsbsd.c
Normal file
486
contrib/binutils/bfd/mipsbsd.c
Normal file
@ -0,0 +1,486 @@
|
||||
/* BFD backend for MIPS BSD (a.out) binaries.
|
||||
Copyright 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003
|
||||
Free Software Foundation, Inc.
|
||||
Written by Ralph Campbell.
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* #define ENTRY_CAN_BE_ZERO */
|
||||
#define N_HEADER_IN_TEXT(x) 1
|
||||
#define N_SHARED_LIB(x) 0
|
||||
#define N_TXTADDR(x) \
|
||||
(N_MAGIC(x) != ZMAGIC ? (x).a_entry : /* object file or NMAGIC */\
|
||||
TEXT_START_ADDR + EXEC_BYTES_SIZE /* no padding */\
|
||||
)
|
||||
#define N_DATADDR(x) (N_TXTADDR(x)+N_TXTSIZE(x))
|
||||
#define TEXT_START_ADDR 4096
|
||||
#define TARGET_PAGE_SIZE 4096
|
||||
#define SEGMENT_SIZE TARGET_PAGE_SIZE
|
||||
#define DEFAULT_ARCH bfd_arch_mips
|
||||
#define MACHTYPE_OK(mtype) ((mtype) == M_UNKNOWN \
|
||||
|| (mtype) == M_MIPS1 || (mtype) == M_MIPS2)
|
||||
#define MY_symbol_leading_char '\0'
|
||||
|
||||
/* Do not "beautify" the CONCAT* macro args. Traditional C will not
|
||||
remove whitespace added here, and thus will fail to concatenate
|
||||
the tokens. */
|
||||
#define MY(OP) CONCAT2 (mipsbsd_,OP)
|
||||
|
||||
#include "bfd.h"
|
||||
#include "sysdep.h"
|
||||
#include "libbfd.h"
|
||||
#include "libaout.h"
|
||||
|
||||
#define SET_ARCH_MACH(ABFD, EXEC) \
|
||||
MY(set_arch_mach) (ABFD, N_MACHTYPE (EXEC)); \
|
||||
MY(choose_reloc_size) (ABFD);
|
||||
static void MY(set_arch_mach) PARAMS ((bfd *abfd, unsigned long machtype));
|
||||
static void MY(choose_reloc_size) PARAMS ((bfd *abfd));
|
||||
|
||||
#define MY_write_object_contents MY(write_object_contents)
|
||||
static bfd_boolean MY(write_object_contents) PARAMS ((bfd *abfd));
|
||||
|
||||
/* We can't use MY(x) here because it leads to a recursive call to CONCAT2
|
||||
when expanded inside JUMP_TABLE. */
|
||||
#define MY_bfd_reloc_type_lookup mipsbsd_reloc_howto_type_lookup
|
||||
#define MY_canonicalize_reloc mipsbsd_canonicalize_reloc
|
||||
|
||||
#define MY_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
|
||||
#define MY_bfd_link_add_symbols _bfd_generic_link_add_symbols
|
||||
#define MY_final_link_callback unused
|
||||
#define MY_bfd_final_link _bfd_generic_final_link
|
||||
|
||||
#define MY_backend_data &MY(backend_data)
|
||||
#define MY_BFD_TARGET
|
||||
|
||||
#include "aout-target.h"
|
||||
|
||||
static bfd_reloc_status_type mips_fix_jmp_addr
|
||||
PARAMS ((bfd *, arelent *, struct bfd_symbol *, PTR, asection *,
|
||||
bfd *, char **));
|
||||
static reloc_howto_type *MY(reloc_howto_type_lookup)
|
||||
PARAMS ((bfd *, bfd_reloc_code_real_type));
|
||||
|
||||
long MY(canonicalize_reloc) PARAMS ((bfd *, sec_ptr, arelent **, asymbol **));
|
||||
|
||||
static void
|
||||
MY(set_arch_mach) (abfd, machtype)
|
||||
bfd *abfd;
|
||||
unsigned long machtype;
|
||||
{
|
||||
enum bfd_architecture arch;
|
||||
unsigned int machine;
|
||||
|
||||
/* Determine the architecture and machine type of the object file. */
|
||||
switch (machtype)
|
||||
{
|
||||
case M_MIPS1:
|
||||
arch = bfd_arch_mips;
|
||||
machine = bfd_mach_mips3000;
|
||||
break;
|
||||
|
||||
case M_MIPS2:
|
||||
arch = bfd_arch_mips;
|
||||
machine = bfd_mach_mips4000;
|
||||
break;
|
||||
|
||||
default:
|
||||
arch = bfd_arch_obscure;
|
||||
machine = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
bfd_set_arch_mach (abfd, arch, machine);
|
||||
}
|
||||
|
||||
/* Determine the size of a relocation entry, based on the architecture */
|
||||
static void
|
||||
MY (choose_reloc_size) (abfd)
|
||||
bfd *abfd;
|
||||
{
|
||||
switch (bfd_get_arch (abfd))
|
||||
{
|
||||
case bfd_arch_sparc:
|
||||
case bfd_arch_a29k:
|
||||
case bfd_arch_mips:
|
||||
obj_reloc_entry_size (abfd) = RELOC_EXT_SIZE;
|
||||
break;
|
||||
default:
|
||||
obj_reloc_entry_size (abfd) = RELOC_STD_SIZE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write an object file in BSD a.out format.
|
||||
Section contents have already been written. We write the
|
||||
file header, symbols, and relocation. */
|
||||
|
||||
static bfd_boolean
|
||||
MY (write_object_contents) (abfd)
|
||||
bfd *abfd;
|
||||
{
|
||||
struct external_exec exec_bytes;
|
||||
struct internal_exec *execp = exec_hdr (abfd);
|
||||
|
||||
/* Magic number, maestro, please! */
|
||||
switch (bfd_get_arch (abfd))
|
||||
{
|
||||
case bfd_arch_m68k:
|
||||
switch (bfd_get_mach (abfd))
|
||||
{
|
||||
case bfd_mach_m68010:
|
||||
N_SET_MACHTYPE (*execp, M_68010);
|
||||
break;
|
||||
default:
|
||||
case bfd_mach_m68020:
|
||||
N_SET_MACHTYPE (*execp, M_68020);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case bfd_arch_sparc:
|
||||
N_SET_MACHTYPE (*execp, M_SPARC);
|
||||
break;
|
||||
case bfd_arch_i386:
|
||||
N_SET_MACHTYPE (*execp, M_386);
|
||||
break;
|
||||
case bfd_arch_a29k:
|
||||
N_SET_MACHTYPE (*execp, M_29K);
|
||||
break;
|
||||
case bfd_arch_mips:
|
||||
switch (bfd_get_mach (abfd))
|
||||
{
|
||||
case bfd_mach_mips4000:
|
||||
case bfd_mach_mips6000:
|
||||
N_SET_MACHTYPE (*execp, M_MIPS2);
|
||||
break;
|
||||
default:
|
||||
N_SET_MACHTYPE (*execp, M_MIPS1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
N_SET_MACHTYPE (*execp, M_UNKNOWN);
|
||||
}
|
||||
|
||||
MY (choose_reloc_size) (abfd);
|
||||
|
||||
WRITE_HEADERS (abfd, execp);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* MIPS relocation types. */
|
||||
#define MIPS_RELOC_32 0
|
||||
#define MIPS_RELOC_JMP 1
|
||||
#define MIPS_RELOC_WDISP16 2
|
||||
#define MIPS_RELOC_HI16 3
|
||||
#define MIPS_RELOC_HI16_S 4
|
||||
#define MIPS_RELOC_LO16 5
|
||||
|
||||
/* This is only called when performing a BFD_RELOC_MIPS_JMP relocation.
|
||||
The jump destination address is formed from the upper 4 bits of the
|
||||
"current" program counter concatenated with the jump instruction's
|
||||
26 bit field and two trailing zeros.
|
||||
If the destination address is not in the same segment as the "current"
|
||||
program counter, then we need to signal an error. */
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_jmp_addr (abfd, reloc_entry, symbol, data, input_section, output_bfd,
|
||||
error_message)
|
||||
bfd *abfd ATTRIBUTE_UNUSED;
|
||||
arelent *reloc_entry;
|
||||
struct bfd_symbol *symbol;
|
||||
PTR data ATTRIBUTE_UNUSED;
|
||||
asection *input_section;
|
||||
bfd *output_bfd;
|
||||
char **error_message ATTRIBUTE_UNUSED;
|
||||
{
|
||||
bfd_vma relocation, pc;
|
||||
|
||||
/* If this is a partial relocation, just continue. */
|
||||
if (output_bfd != (bfd *)NULL)
|
||||
return bfd_reloc_continue;
|
||||
|
||||
/* If this is an undefined symbol, return error */
|
||||
if (bfd_is_und_section (symbol->section)
|
||||
&& (symbol->flags & BSF_WEAK) == 0)
|
||||
return bfd_reloc_undefined;
|
||||
|
||||
/* Work out which section the relocation is targeted at and the
|
||||
initial relocation command value. */
|
||||
if (bfd_is_com_section (symbol->section))
|
||||
relocation = 0;
|
||||
else
|
||||
relocation = symbol->value;
|
||||
|
||||
relocation += symbol->section->output_section->vma;
|
||||
relocation += symbol->section->output_offset;
|
||||
relocation += reloc_entry->addend;
|
||||
|
||||
pc = input_section->output_section->vma + input_section->output_offset +
|
||||
reloc_entry->address + 4;
|
||||
|
||||
if ((relocation & 0xF0000000) != (pc & 0xF0000000))
|
||||
return bfd_reloc_overflow;
|
||||
|
||||
return bfd_reloc_continue;
|
||||
}
|
||||
|
||||
/* This is only called when performing a BFD_RELOC_HI16_S relocation.
|
||||
We need to see if bit 15 is set in the result. If it is, we add
|
||||
0x10000 and continue normally. This will compensate for the sign extension
|
||||
when the low bits are added at run time. */
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_hi16_s PARAMS ((bfd *, arelent *, asymbol *, PTR,
|
||||
asection *, bfd *, char **));
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_hi16_s (abfd, reloc_entry, symbol, data, input_section,
|
||||
output_bfd, error_message)
|
||||
bfd *abfd ATTRIBUTE_UNUSED;
|
||||
arelent *reloc_entry;
|
||||
asymbol *symbol;
|
||||
PTR data ATTRIBUTE_UNUSED;
|
||||
asection *input_section ATTRIBUTE_UNUSED;
|
||||
bfd *output_bfd;
|
||||
char **error_message ATTRIBUTE_UNUSED;
|
||||
{
|
||||
bfd_vma relocation;
|
||||
|
||||
/* If this is a partial relocation, just continue. */
|
||||
if (output_bfd != (bfd *)NULL)
|
||||
return bfd_reloc_continue;
|
||||
|
||||
/* If this is an undefined symbol, return error. */
|
||||
if (bfd_is_und_section (symbol->section)
|
||||
&& (symbol->flags & BSF_WEAK) == 0)
|
||||
return bfd_reloc_undefined;
|
||||
|
||||
/* Work out which section the relocation is targeted at and the
|
||||
initial relocation command value. */
|
||||
if (bfd_is_com_section (symbol->section))
|
||||
relocation = 0;
|
||||
else
|
||||
relocation = symbol->value;
|
||||
|
||||
relocation += symbol->section->output_section->vma;
|
||||
relocation += symbol->section->output_offset;
|
||||
relocation += reloc_entry->addend;
|
||||
|
||||
if (relocation & 0x8000)
|
||||
reloc_entry->addend += 0x10000;
|
||||
|
||||
return bfd_reloc_continue;
|
||||
}
|
||||
|
||||
static reloc_howto_type mips_howto_table_ext[] = {
|
||||
{MIPS_RELOC_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, 0,
|
||||
"32", FALSE, 0, 0xffffffff, FALSE},
|
||||
{MIPS_RELOC_JMP, 2, 2, 26, FALSE, 0, complain_overflow_dont,
|
||||
mips_fix_jmp_addr,
|
||||
"MIPS_JMP", FALSE, 0, 0x03ffffff, FALSE},
|
||||
{MIPS_RELOC_WDISP16, 2, 2, 16, TRUE, 0, complain_overflow_signed, 0,
|
||||
"WDISP16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_HI16, 16, 2, 16, FALSE, 0, complain_overflow_bitfield, 0,
|
||||
"HI16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_HI16_S, 16, 2, 16, FALSE, 0, complain_overflow_bitfield,
|
||||
mips_fix_hi16_s,
|
||||
"HI16_S", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_LO16, 0, 2, 16, FALSE, 0, complain_overflow_dont, 0,
|
||||
"LO16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
};
|
||||
|
||||
static reloc_howto_type *
|
||||
MY(reloc_howto_type_lookup) (abfd, code)
|
||||
bfd *abfd;
|
||||
bfd_reloc_code_real_type code;
|
||||
{
|
||||
|
||||
if (bfd_get_arch (abfd) != bfd_arch_mips)
|
||||
return 0;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case BFD_RELOC_CTOR:
|
||||
case BFD_RELOC_32:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_32]);
|
||||
case BFD_RELOC_MIPS_JMP:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_JMP]);
|
||||
case BFD_RELOC_16_PCREL_S2:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_WDISP16]);
|
||||
case BFD_RELOC_HI16:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_HI16]);
|
||||
case BFD_RELOC_HI16_S:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_HI16_S]);
|
||||
case BFD_RELOC_LO16:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_LO16]);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* This is just like the standard aoutx.h version but we need to do our
|
||||
own mapping of external reloc type values to howto entries. */
|
||||
long
|
||||
MY(canonicalize_reloc) (abfd, section, relptr, symbols)
|
||||
bfd *abfd;
|
||||
sec_ptr section;
|
||||
arelent **relptr;
|
||||
asymbol **symbols;
|
||||
{
|
||||
arelent *tblptr = section->relocation;
|
||||
unsigned int count, c;
|
||||
extern reloc_howto_type NAME(aout,ext_howto_table)[];
|
||||
|
||||
/* If we have already read in the relocation table, return the values. */
|
||||
if (section->flags & SEC_CONSTRUCTOR)
|
||||
{
|
||||
arelent_chain *chain = section->constructor_chain;
|
||||
|
||||
for (count = 0; count < section->reloc_count; count++)
|
||||
{
|
||||
*relptr++ = &chain->relent;
|
||||
chain = chain->next;
|
||||
}
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
if (tblptr && section->reloc_count)
|
||||
{
|
||||
for (count = 0; count++ < section->reloc_count;)
|
||||
*relptr++ = tblptr++;
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
if (!NAME(aout,slurp_reloc_table) (abfd, section, symbols))
|
||||
return -1;
|
||||
tblptr = section->relocation;
|
||||
|
||||
/* fix up howto entries. */
|
||||
for (count = 0; count++ < section->reloc_count;)
|
||||
{
|
||||
c = tblptr->howto - NAME(aout,ext_howto_table);
|
||||
tblptr->howto = &mips_howto_table_ext[c];
|
||||
|
||||
*relptr++ = tblptr++;
|
||||
}
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
static const struct aout_backend_data MY(backend_data) = {
|
||||
0, /* zmagic contiguous */
|
||||
1, /* text incl header */
|
||||
0, /* entry is text address */
|
||||
0, /* exec_hdr_flags */
|
||||
TARGET_PAGE_SIZE, /* text vma */
|
||||
MY_set_sizes,
|
||||
0, /* text size includes exec header */
|
||||
0, /* add_dynamic_symbols */
|
||||
0, /* add_one_symbol */
|
||||
0, /* link_dynamic_object */
|
||||
0, /* write_dynamic_symbol */
|
||||
0, /* check_dynamic_reloc */
|
||||
0 /* finish_dynamic_link */
|
||||
};
|
||||
|
||||
extern const bfd_target aout_mips_big_vec;
|
||||
|
||||
const bfd_target aout_mips_little_vec =
|
||||
{
|
||||
"a.out-mips-little", /* name */
|
||||
bfd_target_aout_flavour,
|
||||
BFD_ENDIAN_LITTLE, /* target byte order (little) */
|
||||
BFD_ENDIAN_LITTLE, /* target headers byte order (little) */
|
||||
(HAS_RELOC | EXEC_P | /* object flags */
|
||||
HAS_LINENO | HAS_DEBUG |
|
||||
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
|
||||
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
|
||||
MY_symbol_leading_char,
|
||||
' ', /* ar_pad_char */
|
||||
15, /* ar_max_namelen */
|
||||
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
|
||||
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
|
||||
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
|
||||
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
|
||||
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
|
||||
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
|
||||
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
|
||||
bfd_generic_archive_p, MY_core_file_p},
|
||||
{bfd_false, MY_mkobject, /* bfd_set_format */
|
||||
_bfd_generic_mkarchive, bfd_false},
|
||||
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
|
||||
_bfd_write_archive_contents, bfd_false},
|
||||
|
||||
BFD_JUMP_TABLE_GENERIC (MY),
|
||||
BFD_JUMP_TABLE_COPY (MY),
|
||||
BFD_JUMP_TABLE_CORE (MY),
|
||||
BFD_JUMP_TABLE_ARCHIVE (MY),
|
||||
BFD_JUMP_TABLE_SYMBOLS (MY),
|
||||
BFD_JUMP_TABLE_RELOCS (MY),
|
||||
BFD_JUMP_TABLE_WRITE (MY),
|
||||
BFD_JUMP_TABLE_LINK (MY),
|
||||
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
|
||||
|
||||
& aout_mips_big_vec,
|
||||
|
||||
(PTR) MY_backend_data
|
||||
};
|
||||
|
||||
const bfd_target aout_mips_big_vec =
|
||||
{
|
||||
"a.out-mips-big", /* name */
|
||||
bfd_target_aout_flavour,
|
||||
BFD_ENDIAN_BIG, /* target byte order (big) */
|
||||
BFD_ENDIAN_BIG, /* target headers byte order (big) */
|
||||
(HAS_RELOC | EXEC_P | /* object flags */
|
||||
HAS_LINENO | HAS_DEBUG |
|
||||
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
|
||||
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
|
||||
MY_symbol_leading_char,
|
||||
' ', /* ar_pad_char */
|
||||
15, /* ar_max_namelen */
|
||||
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
|
||||
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
|
||||
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
|
||||
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
|
||||
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
|
||||
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
|
||||
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
|
||||
bfd_generic_archive_p, MY_core_file_p},
|
||||
{bfd_false, MY_mkobject, /* bfd_set_format */
|
||||
_bfd_generic_mkarchive, bfd_false},
|
||||
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
|
||||
_bfd_write_archive_contents, bfd_false},
|
||||
|
||||
BFD_JUMP_TABLE_GENERIC (MY),
|
||||
BFD_JUMP_TABLE_COPY (MY),
|
||||
BFD_JUMP_TABLE_CORE (MY),
|
||||
BFD_JUMP_TABLE_ARCHIVE (MY),
|
||||
BFD_JUMP_TABLE_SYMBOLS (MY),
|
||||
BFD_JUMP_TABLE_RELOCS (MY),
|
||||
BFD_JUMP_TABLE_WRITE (MY),
|
||||
BFD_JUMP_TABLE_LINK (MY),
|
||||
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
|
||||
|
||||
& aout_mips_little_vec,
|
||||
|
||||
(PTR) MY_backend_data
|
||||
};
|
||||
1000
contrib/binutils/bfd/pe-mips.c
Normal file
1000
contrib/binutils/bfd/pe-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
30
contrib/binutils/bfd/pei-mips.c
Normal file
30
contrib/binutils/bfd/pei-mips.c
Normal file
@ -0,0 +1,30 @@
|
||||
/* BFD back-end for MIPS PE IMAGE COFF files.
|
||||
Copyright 1995, 2000, 2001, 2002 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include "bfd.h"
|
||||
#include "sysdep.h"
|
||||
|
||||
#define TARGET_SYM mipslpei_vec
|
||||
#define TARGET_NAME "pei-mips"
|
||||
#define COFF_IMAGE_WITH_PE
|
||||
#define PCRELOFFSET TRUE
|
||||
#define COFF_LONG_SECTION_NAMES
|
||||
|
||||
#include "pe-mips.c"
|
||||
|
||||
37
contrib/binutils/gas/config/e-mipsecoff.c
Normal file
37
contrib/binutils/gas/config/e-mipsecoff.c
Normal file
@ -0,0 +1,37 @@
|
||||
#include "as.h"
|
||||
#include "emul.h"
|
||||
|
||||
static const char *mipsecoff_bfd_name PARAMS ((void));
|
||||
|
||||
static const char *
|
||||
mipsecoff_bfd_name ()
|
||||
{
|
||||
abort ();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define emul_bfd_name mipsecoff_bfd_name
|
||||
#define emul_format &ecoff_format_ops
|
||||
|
||||
#define emul_name "mipsbecoff"
|
||||
#define emul_struct_name mipsbecoff
|
||||
#define emul_default_endian 1
|
||||
#include "emul-target.h"
|
||||
|
||||
#undef emul_name
|
||||
#undef emul_struct_name
|
||||
#undef emul_default_endian
|
||||
|
||||
#define emul_name "mipslecoff"
|
||||
#define emul_struct_name mipslecoff
|
||||
#define emul_default_endian 0
|
||||
#include "emul-target.h"
|
||||
|
||||
#undef emul_name
|
||||
#undef emul_struct_name
|
||||
#undef emul_default_endian
|
||||
|
||||
#define emul_name "mipsecoff"
|
||||
#define emul_struct_name mipsecoff
|
||||
#define emul_default_endian 2
|
||||
#include "emul-target.h"
|
||||
37
contrib/binutils/gas/config/e-mipself.c
Normal file
37
contrib/binutils/gas/config/e-mipself.c
Normal file
@ -0,0 +1,37 @@
|
||||
#include "as.h"
|
||||
#include "emul.h"
|
||||
|
||||
static const char *mipself_bfd_name PARAMS ((void));
|
||||
|
||||
static const char *
|
||||
mipself_bfd_name ()
|
||||
{
|
||||
abort ();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define emul_bfd_name mipself_bfd_name
|
||||
#define emul_format &elf_format_ops
|
||||
|
||||
#define emul_name "mipsbelf"
|
||||
#define emul_struct_name mipsbelf
|
||||
#define emul_default_endian 1
|
||||
#include "emul-target.h"
|
||||
|
||||
#undef emul_name
|
||||
#undef emul_struct_name
|
||||
#undef emul_default_endian
|
||||
|
||||
#define emul_name "mipslelf"
|
||||
#define emul_struct_name mipslelf
|
||||
#define emul_default_endian 0
|
||||
#include "emul-target.h"
|
||||
|
||||
#undef emul_name
|
||||
#undef emul_struct_name
|
||||
#undef emul_default_endian
|
||||
|
||||
#define emul_name "mipself"
|
||||
#define emul_struct_name mipself
|
||||
#define emul_default_endian 2
|
||||
#include "emul-target.h"
|
||||
47
contrib/binutils/gas/config/itbl-mips.h
Normal file
47
contrib/binutils/gas/config/itbl-mips.h
Normal file
@ -0,0 +1,47 @@
|
||||
|
||||
/* itbl-mips.h
|
||||
|
||||
Copyright 1997 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
02111-1307, USA. */
|
||||
|
||||
/* Defines for Mips itbl cop support */
|
||||
|
||||
#include "opcode/mips.h"
|
||||
|
||||
/* Values for processors will be from 0 to NUMBER_OF_PROCESSORS-1 */
|
||||
#define NUMBER_OF_PROCESSORS 4
|
||||
#define MAX_BITPOS 31
|
||||
|
||||
/* Mips specifics */
|
||||
#define MIPS_OPCODE_COP0 (0x21) /* COPz+CO, bits 31-25: 0100zz1 */
|
||||
#define MIPS_ENCODE_COP_NUM(z) ((MIPS_OPCODE_COP0|z<<1)<<25)
|
||||
#define MIPS_IS_COP_INSN(insn) ((MIPS_OPCODE_COP0&(insn>>25)) \
|
||||
== MIPS_OPCODE_COP0)
|
||||
#define MIPS_DECODE_COP_NUM(insn) ((~MIPS_OPCODE_COP0&(insn>>25))>>1)
|
||||
#define MIPS_DECODE_COP_COFUN(insn) ((~MIPS_ENCODE_COP_NUM(3))&(insn))
|
||||
|
||||
/* definitions required by generic code */
|
||||
#define ITBL_IS_INSN(insn) MIPS_IS_COP_INSN(insn)
|
||||
#define ITBL_DECODE_PNUM(insn) MIPS_DECODE_COP_NUM(insn)
|
||||
#define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
|
||||
|
||||
#define ITBL_OPCODE_STRUCT mips_opcode
|
||||
#define ITBL_OPCODES mips_opcodes
|
||||
#define ITBL_NUM_OPCODES NUMOPCODES
|
||||
#define ITBL_NUM_MACROS M_NUM_MACROS
|
||||
14431
contrib/binutils/gas/config/tc-mips.c
Normal file
14431
contrib/binutils/gas/config/tc-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
188
contrib/binutils/gas/config/tc-mips.h
Normal file
188
contrib/binutils/gas/config/tc-mips.h
Normal file
@ -0,0 +1,188 @@
|
||||
/* tc-mips.h -- header file for tc-mips.c.
|
||||
Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by the OSF and Ralph Campbell.
|
||||
Written by Keith Knowles and Ralph Campbell, working independently.
|
||||
Modified for ECOFF support by Ian Lance Taylor of Cygnus Support.
|
||||
|
||||
This file is part of GAS.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
02111-1307, USA. */
|
||||
|
||||
#ifndef TC_MIPS
|
||||
#define TC_MIPS
|
||||
|
||||
struct frag;
|
||||
struct expressionS;
|
||||
|
||||
/* Default to big endian. */
|
||||
#ifndef TARGET_BYTES_BIG_ENDIAN
|
||||
#define TARGET_BYTES_BIG_ENDIAN 1
|
||||
#endif
|
||||
|
||||
#define TARGET_ARCH bfd_arch_mips
|
||||
|
||||
#define WORKING_DOT_WORD 1
|
||||
#define OLD_FLOAT_READS
|
||||
#define REPEAT_CONS_EXPRESSIONS
|
||||
#define RELOC_EXPANSION_POSSIBLE
|
||||
#define MAX_RELOC_EXPANSION 3
|
||||
#define LOCAL_LABELS_FB 1
|
||||
|
||||
/* Maximum symbol offset that can be encoded in a BFD_RELOC_GPREL16
|
||||
relocation. */
|
||||
#define MAX_GPREL_OFFSET (0x7FF0)
|
||||
|
||||
#define md_relax_frag(segment, fragp, stretch) \
|
||||
mips_relax_frag(segment, fragp, stretch)
|
||||
extern int mips_relax_frag (asection *, struct frag *, long);
|
||||
|
||||
#define md_undefined_symbol(name) (0)
|
||||
#define md_operand(x)
|
||||
|
||||
extern void mips_handle_align (struct frag *);
|
||||
#define HANDLE_ALIGN(fragp) mips_handle_align (fragp)
|
||||
|
||||
#define MAX_MEM_FOR_RS_ALIGN_CODE (1 + 2)
|
||||
|
||||
/* We permit PC relative difference expressions when generating
|
||||
embedded PIC code. */
|
||||
#define DIFF_EXPR_OK
|
||||
|
||||
/* Tell assembler that we have an itbl_mips.h header file to include. */
|
||||
#define HAVE_ITBL_CPU
|
||||
|
||||
/* The endianness of the target format may change based on command
|
||||
line arguments. */
|
||||
#define TARGET_FORMAT mips_target_format()
|
||||
extern const char *mips_target_format (void);
|
||||
|
||||
/* MIPS PIC level. */
|
||||
|
||||
enum mips_pic_level
|
||||
{
|
||||
/* Do not generate PIC code. */
|
||||
NO_PIC,
|
||||
|
||||
/* Generate PIC code as in the SVR4 MIPS ABI. */
|
||||
SVR4_PIC,
|
||||
|
||||
/* Generate PIC code without using a global offset table: the data
|
||||
segment has a maximum size of 64K, all data references are off
|
||||
the $gp register, and all text references are PC relative. This
|
||||
is used on some embedded systems. */
|
||||
EMBEDDED_PIC
|
||||
};
|
||||
|
||||
extern enum mips_pic_level mips_pic;
|
||||
|
||||
struct mips_cl_insn
|
||||
{
|
||||
unsigned long insn_opcode;
|
||||
const struct mips_opcode *insn_mo;
|
||||
/* The next two fields are used when generating mips16 code. */
|
||||
bfd_boolean use_extend;
|
||||
unsigned short extend;
|
||||
};
|
||||
|
||||
extern int tc_get_register (int frame);
|
||||
|
||||
#define md_after_parse_args() mips_after_parse_args()
|
||||
extern void mips_after_parse_args (void);
|
||||
|
||||
#define tc_init_after_args() mips_init_after_args()
|
||||
extern void mips_init_after_args (void);
|
||||
|
||||
#define md_parse_long_option(arg) mips_parse_long_option (arg)
|
||||
extern int mips_parse_long_option (const char *);
|
||||
|
||||
#define tc_frob_label(sym) mips_define_label (sym)
|
||||
extern void mips_define_label (symbolS *);
|
||||
|
||||
#define tc_frob_file_before_adjust() mips_frob_file_before_adjust ()
|
||||
extern void mips_frob_file_before_adjust (void);
|
||||
|
||||
#define tc_frob_file_before_fix() mips_frob_file ()
|
||||
extern void mips_frob_file (void);
|
||||
|
||||
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
|
||||
#define tc_frob_file_after_relocs mips_frob_file_after_relocs
|
||||
extern void mips_frob_file_after_relocs (void);
|
||||
#endif
|
||||
|
||||
#define tc_fix_adjustable(fixp) mips_fix_adjustable (fixp)
|
||||
extern int mips_fix_adjustable (struct fix *);
|
||||
|
||||
/* Values passed to md_apply_fix3 don't include symbol values. */
|
||||
#define MD_APPLY_SYM_VALUE(FIX) 0
|
||||
|
||||
/* Global syms must not be resolved, to support ELF shared libraries.
|
||||
When generating embedded code, we don't have shared libs. */
|
||||
#define EXTERN_FORCE_RELOC \
|
||||
(OUTPUT_FLAVOR == bfd_target_elf_flavour \
|
||||
&& mips_pic != EMBEDDED_PIC)
|
||||
|
||||
/* When generating embedded PIC code we must keep PC relative
|
||||
relocations. */
|
||||
#define TC_FORCE_RELOCATION(FIX) mips_force_relocation (FIX)
|
||||
extern int mips_force_relocation (struct fix *);
|
||||
|
||||
#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \
|
||||
(! SEG_NORMAL (SEG) || mips_force_relocation (FIX))
|
||||
|
||||
/* We use this to turn branches to global symbols into branches to
|
||||
local symbols, so that they can be simplified. */
|
||||
#define TC_VALIDATE_FIX(fixp, this_segment, skip_label) \
|
||||
do \
|
||||
if (! mips_validate_fix ((fixp), (this_segment))) \
|
||||
goto skip_label; \
|
||||
while (0)
|
||||
extern int mips_validate_fix (struct fix *, asection *);
|
||||
|
||||
/* Register mask variables. These are set by the MIPS assembly code
|
||||
and used by ECOFF and possibly other object file formats. */
|
||||
extern unsigned long mips_gprmask;
|
||||
extern unsigned long mips_cprmask[4];
|
||||
|
||||
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
|
||||
|
||||
#define elf_tc_final_processing mips_elf_final_processing
|
||||
extern void mips_elf_final_processing (void);
|
||||
|
||||
#endif
|
||||
|
||||
extern void md_mips_end (void);
|
||||
#define md_end() md_mips_end()
|
||||
|
||||
#define USE_GLOBAL_POINTER_OPT (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
|
||||
|| OUTPUT_FLAVOR == bfd_target_coff_flavour \
|
||||
|| OUTPUT_FLAVOR == bfd_target_elf_flavour)
|
||||
|
||||
extern void mips_pop_insert (void);
|
||||
#define md_pop_insert() mips_pop_insert()
|
||||
|
||||
extern void mips_flush_pending_output (void);
|
||||
#define md_flush_pending_output mips_flush_pending_output
|
||||
|
||||
extern void mips_enable_auto_align (void);
|
||||
#define md_elf_section_change_hook() mips_enable_auto_align()
|
||||
|
||||
extern enum dwarf2_format mips_dwarf2_format (void);
|
||||
#define DWARF2_FORMAT() mips_dwarf2_format ()
|
||||
|
||||
#define DWARF2_ADDR_SIZE(bfd) mips_dwarf2_addr_size ()
|
||||
|
||||
#endif /* TC_MIPS */
|
||||
40
contrib/binutils/gas/config/te-tmips.h
Normal file
40
contrib/binutils/gas/config/te-tmips.h
Normal file
@ -0,0 +1,40 @@
|
||||
/* Traditional MIPS targets
|
||||
Copyright 2000 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GAS, the GNU Assembler.
|
||||
|
||||
GAS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GAS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GAS; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
02111-1307, USA. */
|
||||
|
||||
/* This file is te-tmips.h and is intended to provide support for
|
||||
traditional mips targets like mips-dde-sysv4.2MP (Supermax ) ,
|
||||
mips-sni-sysv4* (Sinix) etc. The base for this file is te-generic.h.
|
||||
Created by Koundinya.K < kk@ddeorg.soft.net > with the help of
|
||||
Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>. */
|
||||
|
||||
/* Added these, because if we don't know what we're targeting we may
|
||||
need an assembler version of libgcc, and that will use local
|
||||
labels. */
|
||||
|
||||
#define TE_TMIPS 1
|
||||
#define LOCAL_LABELS_DOLLAR 1
|
||||
#define LOCAL_LABELS_FB 1
|
||||
|
||||
/* these define interfaces */
|
||||
#ifdef OBJ_HEADER
|
||||
#include OBJ_HEADER
|
||||
#else
|
||||
#include "obj-format.h"
|
||||
#endif
|
||||
377
contrib/binutils/gas/doc/c-mips.texi
Normal file
377
contrib/binutils/gas/doc/c-mips.texi
Normal file
@ -0,0 +1,377 @@
|
||||
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
|
||||
@c 2002, 2003, 2004
|
||||
@c Free Software Foundation, Inc.
|
||||
@c This is part of the GAS manual.
|
||||
@c For copying conditions, see the file as.texinfo.
|
||||
@ifset GENERIC
|
||||
@page
|
||||
@node MIPS-Dependent
|
||||
@chapter MIPS Dependent Features
|
||||
@end ifset
|
||||
@ifclear GENERIC
|
||||
@node Machine Dependencies
|
||||
@chapter MIPS Dependent Features
|
||||
@end ifclear
|
||||
|
||||
@cindex MIPS processor
|
||||
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
|
||||
different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
|
||||
and MIPS64. For information about the @sc{mips} instruction set, see
|
||||
@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
|
||||
For an overview of @sc{mips} assembly conventions, see ``Appendix D:
|
||||
Assembly Language Programming'' in the same work.
|
||||
|
||||
@menu
|
||||
* MIPS Opts:: Assembler options
|
||||
* MIPS Object:: ECOFF object code
|
||||
* MIPS Stabs:: Directives for debugging information
|
||||
* MIPS ISA:: Directives to override the ISA level
|
||||
* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
|
||||
* MIPS insn:: Directive to mark data as an instruction
|
||||
* MIPS option stack:: Directives to save and restore options
|
||||
* MIPS ASE instruction generation overrides:: Directives to control
|
||||
generation of MIPS ASE instructions
|
||||
@end menu
|
||||
|
||||
@node MIPS Opts
|
||||
@section Assembler options
|
||||
|
||||
The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
|
||||
special options:
|
||||
|
||||
@table @code
|
||||
@cindex @code{-G} option (MIPS)
|
||||
@item -G @var{num}
|
||||
This option sets the largest size of an object that can be referenced
|
||||
implicitly with the @code{gp} register. It is only accepted for targets
|
||||
that use @sc{ecoff} format. The default value is 8.
|
||||
|
||||
@cindex @code{-EB} option (MIPS)
|
||||
@cindex @code{-EL} option (MIPS)
|
||||
@cindex MIPS big-endian output
|
||||
@cindex MIPS little-endian output
|
||||
@cindex big-endian output, MIPS
|
||||
@cindex little-endian output, MIPS
|
||||
@item -EB
|
||||
@itemx -EL
|
||||
Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
|
||||
little-endian output at run time (unlike the other @sc{gnu} development
|
||||
tools, which must be configured for one or the other). Use @samp{-EB}
|
||||
to select big-endian output, and @samp{-EL} for little-endian.
|
||||
|
||||
@cindex MIPS architecture options
|
||||
@item -mips1
|
||||
@itemx -mips2
|
||||
@itemx -mips3
|
||||
@itemx -mips4
|
||||
@itemx -mips5
|
||||
@itemx -mips32
|
||||
@itemx -mips32r2
|
||||
@itemx -mips64
|
||||
@itemx -mips64r2
|
||||
Generate code for a particular MIPS Instruction Set Architecture level.
|
||||
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
|
||||
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
|
||||
@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
|
||||
@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
|
||||
@samp{-mips64}, and @samp{-mips64r2}
|
||||
correspond to generic
|
||||
@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
|
||||
and @sc{MIPS64 Release 2}
|
||||
ISA processors, respectively. You can also switch
|
||||
instruction sets during the assembly; see @ref{MIPS ISA, Directives to
|
||||
override the ISA level}.
|
||||
|
||||
@item -mgp32
|
||||
@itemx -mfp32
|
||||
Some macros have different expansions for 32-bit and 64-bit registers.
|
||||
The register sizes are normally inferred from the ISA and ABI, but these
|
||||
flags force a certain group of registers to be treated as 32 bits wide at
|
||||
all times. @samp{-mgp32} controls the size of general-purpose registers
|
||||
and @samp{-mfp32} controls the size of floating-point registers.
|
||||
|
||||
On some MIPS variants there is a 32-bit mode flag; when this flag is
|
||||
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
|
||||
save the 32-bit registers on a context switch, so it is essential never
|
||||
to use the 64-bit registers.
|
||||
|
||||
@item -mgp64
|
||||
Assume that 64-bit general purpose registers are available. This is
|
||||
provided in the interests of symmetry with -gp32.
|
||||
|
||||
@item -mips16
|
||||
@itemx -no-mips16
|
||||
Generate code for the MIPS 16 processor. This is equivalent to putting
|
||||
@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
|
||||
turns off this option.
|
||||
|
||||
@item -mips3d
|
||||
@itemx -no-mips3d
|
||||
Generate code for the MIPS-3D Application Specific Extension.
|
||||
This tells the assembler to accept MIPS-3D instructions.
|
||||
@samp{-no-mips3d} turns off this option.
|
||||
|
||||
@item -mdmx
|
||||
@itemx -no-mdmx
|
||||
Generate code for the MDMX Application Specific Extension.
|
||||
This tells the assembler to accept MDMX instructions.
|
||||
@samp{-no-mdmx} turns off this option.
|
||||
|
||||
@item -mfix7000
|
||||
@itemx -mno-fix7000
|
||||
Cause nops to be inserted if the read of the destination register
|
||||
of an mfhi or mflo instruction occurs in the following two instructions.
|
||||
|
||||
@item -mfix-vr4120
|
||||
@itemx -no-mfix-vr4120
|
||||
Insert nops to work around certain VR4120 errata. This option is
|
||||
intended to be used on GCC-generated code: it is not designed to catch
|
||||
all problems in hand-written assembler code.
|
||||
|
||||
@item -m4010
|
||||
@itemx -no-m4010
|
||||
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
|
||||
accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
|
||||
etc.), and to not schedule @samp{nop} instructions around accesses to
|
||||
the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
|
||||
option.
|
||||
|
||||
@item -m4650
|
||||
@itemx -no-m4650
|
||||
Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
|
||||
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
|
||||
instructions around accesses to the @samp{HI} and @samp{LO} registers.
|
||||
@samp{-no-m4650} turns off this option.
|
||||
|
||||
@itemx -m3900
|
||||
@itemx -no-m3900
|
||||
@itemx -m4100
|
||||
@itemx -no-m4100
|
||||
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
|
||||
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
|
||||
specific to that chip, and to schedule for that chip's hazards.
|
||||
|
||||
@item -march=@var{cpu}
|
||||
Generate code for a particular MIPS cpu. It is exactly equivalent to
|
||||
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
|
||||
understood. Valid @var{cpu} value are:
|
||||
|
||||
@quotation
|
||||
2000,
|
||||
3000,
|
||||
3900,
|
||||
4000,
|
||||
4010,
|
||||
4100,
|
||||
4111,
|
||||
vr4120,
|
||||
vr4130,
|
||||
vr4181,
|
||||
4300,
|
||||
4400,
|
||||
4600,
|
||||
4650,
|
||||
5000,
|
||||
rm5200,
|
||||
rm5230,
|
||||
rm5231,
|
||||
rm5261,
|
||||
rm5721,
|
||||
vr5400,
|
||||
vr5500,
|
||||
6000,
|
||||
rm7000,
|
||||
8000,
|
||||
rm9000,
|
||||
10000,
|
||||
12000,
|
||||
mips32-4k,
|
||||
sb1
|
||||
@end quotation
|
||||
|
||||
@item -mtune=@var{cpu}
|
||||
Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
|
||||
identical to @samp{-march=@var{cpu}}.
|
||||
|
||||
@item -mabi=@var{abi}
|
||||
Record which ABI the source code uses. The recognized arguments
|
||||
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
|
||||
|
||||
@cindex @code{-nocpp} ignored (MIPS)
|
||||
@item -nocpp
|
||||
This option is ignored. It is accepted for command-line compatibility with
|
||||
other assemblers, which use it to turn off C style preprocessing. With
|
||||
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
|
||||
@sc{gnu} assembler itself never runs the C preprocessor.
|
||||
|
||||
@item --construct-floats
|
||||
@itemx --no-construct-floats
|
||||
@cindex --construct-floats
|
||||
@cindex --no-construct-floats
|
||||
The @code{--no-construct-floats} option disables the construction of
|
||||
double width floating point constants by loading the two halves of the
|
||||
value into the two single width floating point registers that make up
|
||||
the double width register. This feature is useful if the processor
|
||||
support the FR bit in its status register, and this bit is known (by
|
||||
the programmer) to be set. This bit prevents the aliasing of the double
|
||||
width register by the single width registers.
|
||||
|
||||
By default @code{--construct-floats} is selected, allowing construction
|
||||
of these floating point constants.
|
||||
|
||||
@item --trap
|
||||
@itemx --no-break
|
||||
@c FIXME! (1) reflect these options (next item too) in option summaries;
|
||||
@c (2) stop teasing, say _which_ instructions expanded _how_.
|
||||
@code{@value{AS}} automatically macro expands certain division and
|
||||
multiplication instructions to check for overflow and division by zero. This
|
||||
option causes @code{@value{AS}} to generate code to take a trap exception
|
||||
rather than a break exception when an error is detected. The trap instructions
|
||||
are only supported at Instruction Set Architecture level 2 and higher.
|
||||
|
||||
@item --break
|
||||
@itemx --no-trap
|
||||
Generate code to take a break exception rather than a trap exception when an
|
||||
error is detected. This is the default.
|
||||
|
||||
@item -mpdr
|
||||
@itemx -mno-pdr
|
||||
Control generation of @code{.pdr} sections. Off by default on IRIX, on
|
||||
elsewhere.
|
||||
@end table
|
||||
|
||||
@node MIPS Object
|
||||
@section MIPS ECOFF object code
|
||||
|
||||
@cindex ECOFF sections
|
||||
@cindex MIPS ECOFF sections
|
||||
Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
|
||||
besides the usual @code{.text}, @code{.data} and @code{.bss}. The
|
||||
additional sections are @code{.rdata}, used for read-only data,
|
||||
@code{.sdata}, used for small data, and @code{.sbss}, used for small
|
||||
common objects.
|
||||
|
||||
@cindex small objects, MIPS ECOFF
|
||||
@cindex @code{gp} register, MIPS
|
||||
When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
|
||||
register to form the address of a ``small object''. Any object in the
|
||||
@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
|
||||
For external objects, or for objects in the @code{.bss} section, you can use
|
||||
the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
|
||||
@code{$gp}; the default value is 8, meaning that a reference to any object
|
||||
eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
|
||||
@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
|
||||
of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
|
||||
or @code{sbss} in any case). The size of an object in the @code{.bss} section
|
||||
is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
|
||||
size of an external object may be set with the @code{.extern} directive. For
|
||||
example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
|
||||
in length, whie leaving @code{sym} otherwise undefined.
|
||||
|
||||
Using small @sc{ecoff} objects requires linker support, and assumes that the
|
||||
@code{$gp} register is correctly initialized (normally done automatically by
|
||||
the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
|
||||
@code{$gp} register.
|
||||
|
||||
@node MIPS Stabs
|
||||
@section Directives for debugging information
|
||||
|
||||
@cindex MIPS debugging directives
|
||||
@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
|
||||
generating debugging information which are not support by traditional @sc{mips}
|
||||
assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
|
||||
@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
|
||||
@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
|
||||
generated by the three @code{.stab} directives can only be read by @sc{gdb},
|
||||
not by traditional @sc{mips} debuggers (this enhancement is required to fully
|
||||
support C++ debugging). These directives are primarily used by compilers, not
|
||||
assembly language programmers!
|
||||
|
||||
@node MIPS ISA
|
||||
@section Directives to override the ISA level
|
||||
|
||||
@cindex MIPS ISA override
|
||||
@kindex @code{.set mips@var{n}}
|
||||
@sc{gnu} @code{@value{AS}} supports an additional directive to change
|
||||
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
|
||||
mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
|
||||
or 64r2.
|
||||
The values other than 0 make the assembler accept instructions
|
||||
for the corresponding @sc{isa} level, from that point on in the
|
||||
assembly. @code{.set mips@var{n}} affects not only which instructions
|
||||
are permitted, but also how certain macros are expanded. @code{.set
|
||||
mips0} restores the @sc{isa} level to its original level: either the
|
||||
level you selected with command line options, or the default for your
|
||||
configuration. You can use this feature to permit specific @sc{r4000}
|
||||
instructions while assembling in 32 bit mode. Use this directive with
|
||||
care!
|
||||
|
||||
The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
|
||||
in which it will assemble instructions for the MIPS 16 processor. Use
|
||||
@samp{.set nomips16} to return to normal 32 bit mode.
|
||||
|
||||
Traditional @sc{mips} assemblers do not support this directive.
|
||||
|
||||
@node MIPS autoextend
|
||||
@section Directives for extending MIPS 16 bit instructions
|
||||
|
||||
@kindex @code{.set autoextend}
|
||||
@kindex @code{.set noautoextend}
|
||||
By default, MIPS 16 instructions are automatically extended to 32 bits
|
||||
when necessary. The directive @samp{.set noautoextend} will turn this
|
||||
off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
|
||||
must be explicitly extended with the @samp{.e} modifier (e.g.,
|
||||
@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
|
||||
to once again automatically extend instructions when necessary.
|
||||
|
||||
This directive is only meaningful when in MIPS 16 mode. Traditional
|
||||
@sc{mips} assemblers do not support this directive.
|
||||
|
||||
@node MIPS insn
|
||||
@section Directive to mark data as an instruction
|
||||
|
||||
@kindex @code{.insn}
|
||||
The @code{.insn} directive tells @code{@value{AS}} that the following
|
||||
data is actually instructions. This makes a difference in MIPS 16 mode:
|
||||
when loading the address of a label which precedes instructions,
|
||||
@code{@value{AS}} automatically adds 1 to the value, so that jumping to
|
||||
the loaded address will do the right thing.
|
||||
|
||||
@node MIPS option stack
|
||||
@section Directives to save and restore options
|
||||
|
||||
@cindex MIPS option stack
|
||||
@kindex @code{.set push}
|
||||
@kindex @code{.set pop}
|
||||
The directives @code{.set push} and @code{.set pop} may be used to save
|
||||
and restore the current settings for all the options which are
|
||||
controlled by @code{.set}. The @code{.set push} directive saves the
|
||||
current settings on a stack. The @code{.set pop} directive pops the
|
||||
stack and restores the settings.
|
||||
|
||||
These directives can be useful inside an macro which must change an
|
||||
option such as the ISA level or instruction reordering but does not want
|
||||
to change the state of the code which invoked the macro.
|
||||
|
||||
Traditional @sc{mips} assemblers do not support these directives.
|
||||
|
||||
@node MIPS ASE instruction generation overrides
|
||||
@section Directives to control generation of MIPS ASE instructions
|
||||
|
||||
@cindex MIPS MIPS-3D instruction generation override
|
||||
@kindex @code{.set mips3d}
|
||||
@kindex @code{.set nomips3d}
|
||||
The directive @code{.set mips3d} makes the assembler accept instructions
|
||||
from the MIPS-3D Application Specific Extension from that point on
|
||||
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
||||
instructions from being accepted.
|
||||
|
||||
@cindex MIPS MDMX instruction generation override
|
||||
@kindex @code{.set mdmx}
|
||||
@kindex @code{.set nomdmx}
|
||||
The directive @code{.set mdmx} makes the assembler accept instructions
|
||||
from the MDMX Application Specific Extension from that point on
|
||||
in the assembly. The @code{.set nomdmx} directive prevents MDMX
|
||||
instructions from being accepted.
|
||||
|
||||
Traditional @sc{mips} assemblers do not support these directives.
|
||||
114
contrib/binutils/gprof/mips.c
Normal file
114
contrib/binutils/gprof/mips.c
Normal file
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Copyright (c) 1983, 1993, 1998
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
#include "gprof.h"
|
||||
#include "search_list.h"
|
||||
#include "source.h"
|
||||
#include "symtab.h"
|
||||
#include "cg_arcs.h"
|
||||
#include "corefile.h"
|
||||
#include "hist.h"
|
||||
|
||||
static Sym indirect_child;
|
||||
|
||||
void mips_find_call PARAMS ((Sym *, bfd_vma, bfd_vma));
|
||||
|
||||
void
|
||||
mips_find_call (parent, p_lowpc, p_highpc)
|
||||
Sym *parent;
|
||||
bfd_vma p_lowpc;
|
||||
bfd_vma p_highpc;
|
||||
{
|
||||
bfd_vma pc, dest_pc;
|
||||
unsigned int op;
|
||||
int offset;
|
||||
Sym *child;
|
||||
static bfd_boolean inited = FALSE;
|
||||
|
||||
if (!inited)
|
||||
{
|
||||
inited = TRUE;
|
||||
sym_init (&indirect_child);
|
||||
indirect_child.name = _("<indirect child>");
|
||||
indirect_child.cg.prop.fract = 1.0;
|
||||
indirect_child.cg.cyc.head = &indirect_child;
|
||||
}
|
||||
|
||||
if (!core_text_space)
|
||||
{
|
||||
return;
|
||||
}
|
||||
if (p_lowpc < s_lowpc)
|
||||
{
|
||||
p_lowpc = s_lowpc;
|
||||
}
|
||||
if (p_highpc > s_highpc)
|
||||
{
|
||||
p_highpc = s_highpc;
|
||||
}
|
||||
DBG (CALLDEBUG, printf (_("[find_call] %s: 0x%lx to 0x%lx\n"),
|
||||
parent->name, (unsigned long) p_lowpc,
|
||||
(unsigned long) p_highpc));
|
||||
for (pc = p_lowpc; pc < p_highpc; pc += 4)
|
||||
{
|
||||
op = bfd_get_32 (core_bfd, &((char *)core_text_space)[pc - s_lowpc]);
|
||||
if ((op & 0xfc000000) == 0x0c000000)
|
||||
{
|
||||
/* This is a "jal" instruction. Check that the destination
|
||||
is the address of a function. */
|
||||
DBG (CALLDEBUG,
|
||||
printf (_("[find_call] 0x%lx: jal"), (unsigned long) pc));
|
||||
offset = (op & 0x03ffffff) << 2;
|
||||
dest_pc = (pc & ~(bfd_vma) 0xfffffff) | offset;
|
||||
if (dest_pc >= s_lowpc && dest_pc <= s_highpc)
|
||||
{
|
||||
child = sym_lookup (&symtab, dest_pc);
|
||||
DBG (CALLDEBUG,
|
||||
printf (" 0x%lx\t; name=%s, addr=0x%lx",
|
||||
(unsigned long) dest_pc, child->name,
|
||||
(unsigned long) child->addr));
|
||||
if (child->addr == dest_pc)
|
||||
{
|
||||
DBG (CALLDEBUG, printf ("\n"));
|
||||
/* a hit: */
|
||||
arc_add (parent, child, (unsigned long) 0);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
/* Something funny going on. */
|
||||
DBG (CALLDEBUG, printf ("\tbut it's a botch\n"));
|
||||
}
|
||||
else if ((op & 0xfc00f83f) == 0x0000f809)
|
||||
{
|
||||
/* This is a "jalr" instruction (indirect call). */
|
||||
DBG (CALLDEBUG,
|
||||
printf (_("[find_call] 0x%lx: jalr\n"), (unsigned long) pc));
|
||||
arc_add (parent, &indirect_child, (unsigned long) 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
367
contrib/binutils/include/coff/mips.h
Normal file
367
contrib/binutils/include/coff/mips.h
Normal file
@ -0,0 +1,367 @@
|
||||
/* ECOFF support on MIPS machines.
|
||||
coff/ecoff.h must be included before this file.
|
||||
|
||||
Copyright 2001 Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#define DO_NOT_DEFINE_AOUTHDR
|
||||
#define L_LNNO_SIZE 4
|
||||
#include "coff/external.h"
|
||||
|
||||
/* Magic numbers are defined in coff/ecoff.h. */
|
||||
#define MIPS_ECOFF_BADMAG(x) (((x).f_magic!=MIPS_MAGIC_1) && \
|
||||
((x).f_magic!=MIPS_MAGIC_LITTLE) &&\
|
||||
((x).f_magic!=MIPS_MAGIC_BIG) && \
|
||||
((x).f_magic!=MIPS_MAGIC_LITTLE2) && \
|
||||
((x).f_magic!=MIPS_MAGIC_BIG2) && \
|
||||
((x).f_magic!=MIPS_MAGIC_LITTLE3) && \
|
||||
((x).f_magic!=MIPS_MAGIC_BIG3))
|
||||
|
||||
|
||||
/********************** AOUT "OPTIONAL HEADER" **********************/
|
||||
|
||||
typedef struct external_aouthdr
|
||||
{
|
||||
unsigned char magic[2]; /* type of file */
|
||||
unsigned char vstamp[2]; /* version stamp */
|
||||
unsigned char tsize[4]; /* text size in bytes, padded to FW bdry*/
|
||||
unsigned char dsize[4]; /* initialized data " " */
|
||||
unsigned char bsize[4]; /* uninitialized data " " */
|
||||
unsigned char entry[4]; /* entry pt. */
|
||||
unsigned char text_start[4]; /* base of text used for this file */
|
||||
unsigned char data_start[4]; /* base of data used for this file */
|
||||
unsigned char bss_start[4]; /* base of bss used for this file */
|
||||
unsigned char gprmask[4]; /* ?? */
|
||||
unsigned char cprmask[4][4]; /* ?? */
|
||||
unsigned char gp_value[4]; /* value for gp register */
|
||||
} AOUTHDR;
|
||||
|
||||
/* compute size of a header */
|
||||
|
||||
#define AOUTSZ 56
|
||||
#define AOUTHDRSZ 56
|
||||
|
||||
/********************** RELOCATION DIRECTIVES **********************/
|
||||
|
||||
struct external_reloc
|
||||
{
|
||||
unsigned char r_vaddr[4];
|
||||
unsigned char r_bits[4];
|
||||
};
|
||||
|
||||
#define RELOC struct external_reloc
|
||||
#define RELSZ 8
|
||||
|
||||
/* MIPS ECOFF uses a packed 8 byte format for relocs. These constants
|
||||
are used to unpack the r_bits field. */
|
||||
|
||||
#define RELOC_BITS0_SYMNDX_SH_LEFT_BIG 16
|
||||
#define RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE 0
|
||||
|
||||
#define RELOC_BITS1_SYMNDX_SH_LEFT_BIG 8
|
||||
#define RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE 8
|
||||
|
||||
#define RELOC_BITS2_SYMNDX_SH_LEFT_BIG 0
|
||||
#define RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE 16
|
||||
|
||||
/* Originally, ECOFF used four bits for the reloc type and had three
|
||||
reserved bits. Irix 4 added another bit for the reloc type, which
|
||||
was easy because it was big endian and one of the spare bits became
|
||||
the new most significant bit. To make this also work for little
|
||||
endian ECOFF, we need to wrap one of the reserved bits around to
|
||||
become the most significant bit of the reloc type. */
|
||||
#define RELOC_BITS3_TYPE_BIG 0x3E
|
||||
#define RELOC_BITS3_TYPE_SH_BIG 1
|
||||
#define RELOC_BITS3_TYPE_LITTLE 0x78
|
||||
#define RELOC_BITS3_TYPE_SH_LITTLE 3
|
||||
#define RELOC_BITS3_TYPEHI_LITTLE 0x04
|
||||
#define RELOC_BITS3_TYPEHI_SH_LITTLE 2
|
||||
|
||||
#define RELOC_BITS3_EXTERN_BIG 0x01
|
||||
#define RELOC_BITS3_EXTERN_LITTLE 0x80
|
||||
|
||||
/* The r_type field in a reloc is one of the following values. I
|
||||
don't know if any other values can appear. These seem to be all
|
||||
that occur in the Ultrix 4.2 libraries. */
|
||||
#define MIPS_R_IGNORE 0
|
||||
#define MIPS_R_REFHALF 1
|
||||
#define MIPS_R_REFWORD 2
|
||||
#define MIPS_R_JMPADDR 3
|
||||
#define MIPS_R_REFHI 4
|
||||
#define MIPS_R_REFLO 5
|
||||
#define MIPS_R_GPREL 6
|
||||
#define MIPS_R_LITERAL 7
|
||||
|
||||
/* These reloc types are a Cygnus extension used when generating
|
||||
position independent code for embedded systems. The numbers are
|
||||
taken from Irix 4, but at least for internal relocs Irix 5 does not
|
||||
give them the same meaning. For an internal reloc the symbol index
|
||||
of RELHI and RELLO is modified as described below for
|
||||
MIPS_R_SWITCH. */
|
||||
#define MIPS_R_PCREL16 12
|
||||
#define MIPS_R_RELHI 13
|
||||
#define MIPS_R_RELLO 14
|
||||
|
||||
/* This reloc type is a Cygnus extension used when generating position
|
||||
independent code for embedded systems. It is used for an entry in
|
||||
a switch table, which looks like this:
|
||||
.word $L3-$LS12
|
||||
The object file will contain the correct difference, and does not
|
||||
require adjustment. However, when the linker is relaxing PC
|
||||
relative calls, it is possible for $L3 to move farther away. This
|
||||
reloc always appears in the .text section, and is always against
|
||||
the .text section. However, the symbol index is not
|
||||
RELOC_SECTION_TEXT. It is, instead, the distance between this
|
||||
switch table entry and $LS12. Thus, the original value of $L12 is
|
||||
vaddr - symndx
|
||||
and the original value of $L3 is
|
||||
vaddr - symndx + addend
|
||||
where addend is the value in the object file. Knowing this, the
|
||||
linker can know whether the addend in the object file must be
|
||||
adjusted. */
|
||||
#define MIPS_R_SWITCH 22
|
||||
|
||||
/********************** STABS **********************/
|
||||
|
||||
#define MIPS_IS_STAB ECOFF_IS_STAB
|
||||
#define MIPS_MARK_STAB ECOFF_MARK_STAB
|
||||
#define MIPS_UNMARK_STAB ECOFF_UNMARK_STAB
|
||||
|
||||
/********************** SYMBOLIC INFORMATION **********************/
|
||||
|
||||
/* Written by John Gilmore. */
|
||||
|
||||
/* ECOFF uses COFF-like section structures, but its own symbol format.
|
||||
This file defines the symbol format in fields whose size and alignment
|
||||
will not vary on different host systems. */
|
||||
|
||||
/* File header as a set of bytes */
|
||||
|
||||
struct hdr_ext
|
||||
{
|
||||
unsigned char h_magic[2];
|
||||
unsigned char h_vstamp[2];
|
||||
unsigned char h_ilineMax[4];
|
||||
unsigned char h_cbLine[4];
|
||||
unsigned char h_cbLineOffset[4];
|
||||
unsigned char h_idnMax[4];
|
||||
unsigned char h_cbDnOffset[4];
|
||||
unsigned char h_ipdMax[4];
|
||||
unsigned char h_cbPdOffset[4];
|
||||
unsigned char h_isymMax[4];
|
||||
unsigned char h_cbSymOffset[4];
|
||||
unsigned char h_ioptMax[4];
|
||||
unsigned char h_cbOptOffset[4];
|
||||
unsigned char h_iauxMax[4];
|
||||
unsigned char h_cbAuxOffset[4];
|
||||
unsigned char h_issMax[4];
|
||||
unsigned char h_cbSsOffset[4];
|
||||
unsigned char h_issExtMax[4];
|
||||
unsigned char h_cbSsExtOffset[4];
|
||||
unsigned char h_ifdMax[4];
|
||||
unsigned char h_cbFdOffset[4];
|
||||
unsigned char h_crfd[4];
|
||||
unsigned char h_cbRfdOffset[4];
|
||||
unsigned char h_iextMax[4];
|
||||
unsigned char h_cbExtOffset[4];
|
||||
};
|
||||
|
||||
/* File descriptor external record */
|
||||
|
||||
struct fdr_ext
|
||||
{
|
||||
unsigned char f_adr[4];
|
||||
unsigned char f_rss[4];
|
||||
unsigned char f_issBase[4];
|
||||
unsigned char f_cbSs[4];
|
||||
unsigned char f_isymBase[4];
|
||||
unsigned char f_csym[4];
|
||||
unsigned char f_ilineBase[4];
|
||||
unsigned char f_cline[4];
|
||||
unsigned char f_ioptBase[4];
|
||||
unsigned char f_copt[4];
|
||||
unsigned char f_ipdFirst[2];
|
||||
unsigned char f_cpd[2];
|
||||
unsigned char f_iauxBase[4];
|
||||
unsigned char f_caux[4];
|
||||
unsigned char f_rfdBase[4];
|
||||
unsigned char f_crfd[4];
|
||||
unsigned char f_bits1[1];
|
||||
unsigned char f_bits2[3];
|
||||
unsigned char f_cbLineOffset[4];
|
||||
unsigned char f_cbLine[4];
|
||||
};
|
||||
|
||||
#define FDR_BITS1_LANG_BIG 0xF8
|
||||
#define FDR_BITS1_LANG_SH_BIG 3
|
||||
#define FDR_BITS1_LANG_LITTLE 0x1F
|
||||
#define FDR_BITS1_LANG_SH_LITTLE 0
|
||||
|
||||
#define FDR_BITS1_FMERGE_BIG 0x04
|
||||
#define FDR_BITS1_FMERGE_LITTLE 0x20
|
||||
|
||||
#define FDR_BITS1_FREADIN_BIG 0x02
|
||||
#define FDR_BITS1_FREADIN_LITTLE 0x40
|
||||
|
||||
#define FDR_BITS1_FBIGENDIAN_BIG 0x01
|
||||
#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80
|
||||
|
||||
#define FDR_BITS2_GLEVEL_BIG 0xC0
|
||||
#define FDR_BITS2_GLEVEL_SH_BIG 6
|
||||
#define FDR_BITS2_GLEVEL_LITTLE 0x03
|
||||
#define FDR_BITS2_GLEVEL_SH_LITTLE 0
|
||||
|
||||
/* We ignore the `reserved' field in bits2. */
|
||||
|
||||
/* Procedure descriptor external record */
|
||||
|
||||
struct pdr_ext
|
||||
{
|
||||
unsigned char p_adr[4];
|
||||
unsigned char p_isym[4];
|
||||
unsigned char p_iline[4];
|
||||
unsigned char p_regmask[4];
|
||||
unsigned char p_regoffset[4];
|
||||
unsigned char p_iopt[4];
|
||||
unsigned char p_fregmask[4];
|
||||
unsigned char p_fregoffset[4];
|
||||
unsigned char p_frameoffset[4];
|
||||
unsigned char p_framereg[2];
|
||||
unsigned char p_pcreg[2];
|
||||
unsigned char p_lnLow[4];
|
||||
unsigned char p_lnHigh[4];
|
||||
unsigned char p_cbLineOffset[4];
|
||||
};
|
||||
|
||||
/* Runtime procedure table */
|
||||
|
||||
struct rpdr_ext
|
||||
{
|
||||
unsigned char p_adr[4];
|
||||
unsigned char p_regmask[4];
|
||||
unsigned char p_regoffset[4];
|
||||
unsigned char p_fregmask[4];
|
||||
unsigned char p_fregoffset[4];
|
||||
unsigned char p_frameoffset[4];
|
||||
unsigned char p_framereg[2];
|
||||
unsigned char p_pcreg[2];
|
||||
unsigned char p_irpss[4];
|
||||
unsigned char p_reserved[4];
|
||||
unsigned char p_exception_info[4];
|
||||
};
|
||||
|
||||
/* Line numbers */
|
||||
|
||||
struct line_ext
|
||||
{
|
||||
unsigned char l_line[4];
|
||||
};
|
||||
|
||||
/* Symbol external record */
|
||||
|
||||
struct sym_ext
|
||||
{
|
||||
unsigned char s_iss[4];
|
||||
unsigned char s_value[4];
|
||||
unsigned char s_bits1[1];
|
||||
unsigned char s_bits2[1];
|
||||
unsigned char s_bits3[1];
|
||||
unsigned char s_bits4[1];
|
||||
};
|
||||
|
||||
#define SYM_BITS1_ST_BIG 0xFC
|
||||
#define SYM_BITS1_ST_SH_BIG 2
|
||||
#define SYM_BITS1_ST_LITTLE 0x3F
|
||||
#define SYM_BITS1_ST_SH_LITTLE 0
|
||||
|
||||
#define SYM_BITS1_SC_BIG 0x03
|
||||
#define SYM_BITS1_SC_SH_LEFT_BIG 3
|
||||
#define SYM_BITS1_SC_LITTLE 0xC0
|
||||
#define SYM_BITS1_SC_SH_LITTLE 6
|
||||
|
||||
#define SYM_BITS2_SC_BIG 0xE0
|
||||
#define SYM_BITS2_SC_SH_BIG 5
|
||||
#define SYM_BITS2_SC_LITTLE 0x07
|
||||
#define SYM_BITS2_SC_SH_LEFT_LITTLE 2
|
||||
|
||||
#define SYM_BITS2_RESERVED_BIG 0x10
|
||||
#define SYM_BITS2_RESERVED_LITTLE 0x08
|
||||
|
||||
#define SYM_BITS2_INDEX_BIG 0x0F
|
||||
#define SYM_BITS2_INDEX_SH_LEFT_BIG 16
|
||||
#define SYM_BITS2_INDEX_LITTLE 0xF0
|
||||
#define SYM_BITS2_INDEX_SH_LITTLE 4
|
||||
|
||||
#define SYM_BITS3_INDEX_SH_LEFT_BIG 8
|
||||
#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4
|
||||
|
||||
#define SYM_BITS4_INDEX_SH_LEFT_BIG 0
|
||||
#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12
|
||||
|
||||
/* External symbol external record */
|
||||
|
||||
struct ext_ext
|
||||
{
|
||||
unsigned char es_bits1[1];
|
||||
unsigned char es_bits2[1];
|
||||
unsigned char es_ifd[2];
|
||||
struct sym_ext es_asym;
|
||||
};
|
||||
|
||||
#define EXT_BITS1_JMPTBL_BIG 0x80
|
||||
#define EXT_BITS1_JMPTBL_LITTLE 0x01
|
||||
|
||||
#define EXT_BITS1_COBOL_MAIN_BIG 0x40
|
||||
#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02
|
||||
|
||||
#define EXT_BITS1_WEAKEXT_BIG 0x20
|
||||
#define EXT_BITS1_WEAKEXT_LITTLE 0x04
|
||||
|
||||
/* Dense numbers external record */
|
||||
|
||||
struct dnr_ext
|
||||
{
|
||||
unsigned char d_rfd[4];
|
||||
unsigned char d_index[4];
|
||||
};
|
||||
|
||||
/* Relative file descriptor */
|
||||
|
||||
struct rfd_ext
|
||||
{
|
||||
unsigned char rfd[4];
|
||||
};
|
||||
|
||||
/* Optimizer symbol external record */
|
||||
|
||||
struct opt_ext
|
||||
{
|
||||
unsigned char o_bits1[1];
|
||||
unsigned char o_bits2[1];
|
||||
unsigned char o_bits3[1];
|
||||
unsigned char o_bits4[1];
|
||||
struct rndx_ext o_rndx;
|
||||
unsigned char o_offset[4];
|
||||
};
|
||||
|
||||
#define OPT_BITS2_VALUE_SH_LEFT_BIG 16
|
||||
#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0
|
||||
|
||||
#define OPT_BITS3_VALUE_SH_LEFT_BIG 8
|
||||
#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8
|
||||
|
||||
#define OPT_BITS4_VALUE_SH_LEFT_BIG 0
|
||||
#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16
|
||||
66
contrib/binutils/include/coff/mipspe.h
Normal file
66
contrib/binutils/include/coff/mipspe.h
Normal file
@ -0,0 +1,66 @@
|
||||
/* coff information for Windows CE with MIPS VR4111
|
||||
|
||||
Copyright 2001 Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#define L_LNNO_SIZE 2
|
||||
#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
|
||||
#include "coff/external.h"
|
||||
|
||||
#define MIPS_ARCH_MAGIC_WINCE 0x0166 /* Windows CE - little endian */
|
||||
#define MIPS_PE_MAGIC 0x010b
|
||||
|
||||
#define MIPSBADMAG(x) ((x).f_magic != MIPS_ARCH_MAGIC_WINCE)
|
||||
|
||||
/* define some NT default values */
|
||||
/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */
|
||||
#define NT_SECTION_ALIGNMENT 0x1000
|
||||
#define NT_FILE_ALIGNMENT 0x200
|
||||
#define NT_DEF_RESERVE 0x100000
|
||||
#define NT_DEF_COMMIT 0x1000
|
||||
|
||||
/********************** RELOCATION DIRECTIVES **********************/
|
||||
|
||||
/* The external reloc has an offset field, because some of the reloc
|
||||
types on the h8 don't have room in the instruction for the entire
|
||||
offset - eg the strange jump and high page addressing modes. */
|
||||
|
||||
struct external_reloc
|
||||
{
|
||||
char r_vaddr[4];
|
||||
char r_symndx[4];
|
||||
char r_type[2];
|
||||
};
|
||||
|
||||
#define RELOC struct external_reloc
|
||||
#define RELSZ 10
|
||||
|
||||
/* MIPS PE relocation types. */
|
||||
|
||||
#define MIPS_R_ABSOLUTE 0 /* ignored */
|
||||
#define MIPS_R_REFHALF 1
|
||||
#define MIPS_R_REFWORD 2
|
||||
#define MIPS_R_JMPADDR 3
|
||||
#define MIPS_R_REFHI 4 /* PAIR follows */
|
||||
#define MIPS_R_REFLO 5
|
||||
#define MIPS_R_GPREL 6
|
||||
#define MIPS_R_LITERAL 7 /* same as GPREL */
|
||||
#define MIPS_R_SECTION 10
|
||||
#define MIPS_R_SECREL 11
|
||||
#define MIPS_R_SECRELLO 12
|
||||
#define MIPS_R_SECRELHI 13 /* PAIR follows */
|
||||
#define MIPS_R_RVA 34 /* 0x22 */
|
||||
#define MIPS_R_PAIR 37 /* 0x25 - symndx is really a signed 16-bit addend */
|
||||
914
contrib/binutils/include/opcode/mips.h
Normal file
914
contrib/binutils/include/opcode/mips.h
Normal file
@ -0,0 +1,914 @@
|
||||
/* mips.h. Mips opcode list for GDB, the GNU debugger.
|
||||
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Ralph Campbell and OSF
|
||||
Commented and modified by Ian Lance Taylor, Cygnus Support
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
1, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef _MIPS_H_
|
||||
#define _MIPS_H_
|
||||
|
||||
/* These are bit masks and shift counts to use to access the various
|
||||
fields of an instruction. To retrieve the X field of an
|
||||
instruction, use the expression
|
||||
(i >> OP_SH_X) & OP_MASK_X
|
||||
To set the same field (to j), use
|
||||
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
|
||||
|
||||
Make sure you use fields that are appropriate for the instruction,
|
||||
of course.
|
||||
|
||||
The 'i' format uses OP, RS, RT and IMMEDIATE.
|
||||
|
||||
The 'j' format uses OP and TARGET.
|
||||
|
||||
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
|
||||
|
||||
The 'b' format uses OP, RS, RT and DELTA.
|
||||
|
||||
The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
|
||||
|
||||
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
|
||||
|
||||
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
|
||||
breakpoint instruction are not defined; Kane says the breakpoint
|
||||
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
|
||||
only use ten bits). An optional two-operand form of break/sdbbp
|
||||
allows the lower ten bits to be set too, and MIPS32 and later
|
||||
architectures allow 20 bits to be set with a signal operand
|
||||
(using CODE20).
|
||||
|
||||
The syscall instruction uses CODE20.
|
||||
|
||||
The general coprocessor instructions use COPZ. */
|
||||
|
||||
#define OP_MASK_OP 0x3f
|
||||
#define OP_SH_OP 26
|
||||
#define OP_MASK_RS 0x1f
|
||||
#define OP_SH_RS 21
|
||||
#define OP_MASK_FR 0x1f
|
||||
#define OP_SH_FR 21
|
||||
#define OP_MASK_FMT 0x1f
|
||||
#define OP_SH_FMT 21
|
||||
#define OP_MASK_BCC 0x7
|
||||
#define OP_SH_BCC 18
|
||||
#define OP_MASK_CODE 0x3ff
|
||||
#define OP_SH_CODE 16
|
||||
#define OP_MASK_CODE2 0x3ff
|
||||
#define OP_SH_CODE2 6
|
||||
#define OP_MASK_RT 0x1f
|
||||
#define OP_SH_RT 16
|
||||
#define OP_MASK_FT 0x1f
|
||||
#define OP_SH_FT 16
|
||||
#define OP_MASK_CACHE 0x1f
|
||||
#define OP_SH_CACHE 16
|
||||
#define OP_MASK_RD 0x1f
|
||||
#define OP_SH_RD 11
|
||||
#define OP_MASK_FS 0x1f
|
||||
#define OP_SH_FS 11
|
||||
#define OP_MASK_PREFX 0x1f
|
||||
#define OP_SH_PREFX 11
|
||||
#define OP_MASK_CCC 0x7
|
||||
#define OP_SH_CCC 8
|
||||
#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
|
||||
#define OP_SH_CODE20 6
|
||||
#define OP_MASK_SHAMT 0x1f
|
||||
#define OP_SH_SHAMT 6
|
||||
#define OP_MASK_FD 0x1f
|
||||
#define OP_SH_FD 6
|
||||
#define OP_MASK_TARGET 0x3ffffff
|
||||
#define OP_SH_TARGET 0
|
||||
#define OP_MASK_COPZ 0x1ffffff
|
||||
#define OP_SH_COPZ 0
|
||||
#define OP_MASK_IMMEDIATE 0xffff
|
||||
#define OP_SH_IMMEDIATE 0
|
||||
#define OP_MASK_DELTA 0xffff
|
||||
#define OP_SH_DELTA 0
|
||||
#define OP_MASK_FUNCT 0x3f
|
||||
#define OP_SH_FUNCT 0
|
||||
#define OP_MASK_SPEC 0x3f
|
||||
#define OP_SH_SPEC 0
|
||||
#define OP_SH_LOCC 8 /* FP condition code. */
|
||||
#define OP_SH_HICC 18 /* FP condition code. */
|
||||
#define OP_MASK_CC 0x7
|
||||
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
|
||||
#define OP_MASK_COP1NORM 0x1 /* a single bit. */
|
||||
#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
|
||||
#define OP_MASK_COP1SPEC 0xf
|
||||
#define OP_MASK_COP1SCLR 0x4
|
||||
#define OP_MASK_COP1CMP 0x3
|
||||
#define OP_SH_COP1CMP 4
|
||||
#define OP_SH_FORMAT 21 /* FP short format field. */
|
||||
#define OP_MASK_FORMAT 0x7
|
||||
#define OP_SH_TRUE 16
|
||||
#define OP_MASK_TRUE 0x1
|
||||
#define OP_SH_GE 17
|
||||
#define OP_MASK_GE 0x01
|
||||
#define OP_SH_UNSIGNED 16
|
||||
#define OP_MASK_UNSIGNED 0x1
|
||||
#define OP_SH_HINT 16
|
||||
#define OP_MASK_HINT 0x1f
|
||||
#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
|
||||
#define OP_MASK_MMI 0x3f
|
||||
#define OP_SH_MMISUB 6
|
||||
#define OP_MASK_MMISUB 0x1f
|
||||
#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
|
||||
#define OP_SH_PERFREG 1
|
||||
#define OP_SH_SEL 0 /* Coprocessor select field. */
|
||||
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
|
||||
#define OP_SH_CODE19 6 /* 19 bit wait code. */
|
||||
#define OP_MASK_CODE19 0x7ffff
|
||||
#define OP_SH_ALN 21
|
||||
#define OP_MASK_ALN 0x7
|
||||
#define OP_SH_VSEL 21
|
||||
#define OP_MASK_VSEL 0x1f
|
||||
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
|
||||
but 0x8-0xf don't select bytes. */
|
||||
#define OP_SH_VECBYTE 22
|
||||
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
|
||||
#define OP_SH_VECALIGN 21
|
||||
#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
|
||||
#define OP_SH_INSMSB 11
|
||||
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
|
||||
#define OP_SH_EXTMSBD 11
|
||||
|
||||
#define OP_OP_COP0 0x10
|
||||
#define OP_OP_COP1 0x11
|
||||
#define OP_OP_COP2 0x12
|
||||
#define OP_OP_COP3 0x13
|
||||
#define OP_OP_LWC1 0x31
|
||||
#define OP_OP_LWC2 0x32
|
||||
#define OP_OP_LWC3 0x33 /* a.k.a. pref */
|
||||
#define OP_OP_LDC1 0x35
|
||||
#define OP_OP_LDC2 0x36
|
||||
#define OP_OP_LDC3 0x37 /* a.k.a. ld */
|
||||
#define OP_OP_SWC1 0x39
|
||||
#define OP_OP_SWC2 0x3a
|
||||
#define OP_OP_SWC3 0x3b
|
||||
#define OP_OP_SDC1 0x3d
|
||||
#define OP_OP_SDC2 0x3e
|
||||
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
|
||||
|
||||
/* Values in the 'VSEL' field. */
|
||||
#define MDMX_FMTSEL_IMM_QH 0x1d
|
||||
#define MDMX_FMTSEL_IMM_OB 0x1e
|
||||
#define MDMX_FMTSEL_VEC_QH 0x15
|
||||
#define MDMX_FMTSEL_VEC_OB 0x16
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
struct mips_opcode
|
||||
{
|
||||
/* The name of the instruction. */
|
||||
const char *name;
|
||||
/* A string describing the arguments for this instruction. */
|
||||
const char *args;
|
||||
/* The basic opcode for the instruction. When assembling, this
|
||||
opcode is modified by the arguments to produce the actual opcode
|
||||
that is used. If pinfo is INSN_MACRO, then this is 0. */
|
||||
unsigned long match;
|
||||
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
|
||||
relevant portions of the opcode when disassembling. If the
|
||||
actual opcode anded with the match field equals the opcode field,
|
||||
then we have found the correct instruction. If pinfo is
|
||||
INSN_MACRO, then this field is the macro identifier. */
|
||||
unsigned long mask;
|
||||
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
|
||||
of bits describing the instruction, notably any relevant hazard
|
||||
information. */
|
||||
unsigned long pinfo;
|
||||
/* A collection of bits describing the instruction sets of which this
|
||||
instruction or macro is a member. */
|
||||
unsigned long membership;
|
||||
};
|
||||
|
||||
/* These are the characters which may appear in the args field of an
|
||||
instruction. They appear in the order in which the fields appear
|
||||
when the instruction is used. Commas and parentheses in the args
|
||||
string are ignored when assembling, and written into the output
|
||||
when disassembling.
|
||||
|
||||
Each of these characters corresponds to a mask field defined above.
|
||||
|
||||
"<" 5 bit shift amount (OP_*_SHAMT)
|
||||
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
|
||||
"a" 26 bit target address (OP_*_TARGET)
|
||||
"b" 5 bit base register (OP_*_RS)
|
||||
"c" 10 bit breakpoint code (OP_*_CODE)
|
||||
"d" 5 bit destination register specifier (OP_*_RD)
|
||||
"h" 5 bit prefx hint (OP_*_PREFX)
|
||||
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
|
||||
"j" 16 bit signed immediate (OP_*_DELTA)
|
||||
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
|
||||
Also used for immediate operands in vr5400 vector insns.
|
||||
"o" 16 bit signed offset (OP_*_DELTA)
|
||||
"p" 16 bit PC relative branch target address (OP_*_DELTA)
|
||||
"q" 10 bit extra breakpoint code (OP_*_CODE2)
|
||||
"r" 5 bit same register used as both source and target (OP_*_RS)
|
||||
"s" 5 bit source register specifier (OP_*_RS)
|
||||
"t" 5 bit target register (OP_*_RT)
|
||||
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
|
||||
"v" 5 bit same register used as both source and destination (OP_*_RS)
|
||||
"w" 5 bit same register used as both target and destination (OP_*_RT)
|
||||
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
|
||||
(used by clo and clz)
|
||||
"C" 25 bit coprocessor function code (OP_*_COPZ)
|
||||
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
|
||||
"J" 19 bit wait function code (OP_*_CODE19)
|
||||
"x" accept and ignore register name
|
||||
"z" must be zero register
|
||||
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
|
||||
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
|
||||
Enforces: 0 <= pos < 32.
|
||||
"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 0 < (pos+size) <= 32.
|
||||
"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 0 < (pos+size) <= 32.
|
||||
(Also used by "dext" w/ different limits, but limits for
|
||||
that are checked by the M_DEXT macro.)
|
||||
"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
|
||||
Enforces: 32 <= pos < 64.
|
||||
"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
|
||||
Floating point instructions:
|
||||
"D" 5 bit destination register (OP_*_FD)
|
||||
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
|
||||
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
|
||||
"S" 5 bit fs source 1 register (OP_*_FS)
|
||||
"T" 5 bit ft source 2 register (OP_*_FT)
|
||||
"R" 5 bit fr source 3 register (OP_*_FR)
|
||||
"V" 5 bit same register used as floating source and destination (OP_*_FS)
|
||||
"W" 5 bit same register used as floating target and destination (OP_*_FT)
|
||||
|
||||
Coprocessor instructions:
|
||||
"E" 5 bit target register (OP_*_RT)
|
||||
"G" 5 bit destination register (OP_*_RD)
|
||||
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
|
||||
"P" 5 bit performance-monitor register (OP_*_PERFREG)
|
||||
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
|
||||
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
|
||||
see also "k" above
|
||||
"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
|
||||
for pretty-printing in disassembly only.
|
||||
|
||||
Macro instructions:
|
||||
"A" General 32 bit expression
|
||||
"I" 32 bit immediate (value placed in imm_expr).
|
||||
"+I" 32 bit immediate (value placed in imm2_expr).
|
||||
"F" 64 bit floating point constant in .rdata
|
||||
"L" 64 bit floating point constant in .lit8
|
||||
"f" 32 bit floating point constant
|
||||
"l" 32 bit floating point constant in .lit4
|
||||
|
||||
MDMX instruction operands (note that while these use the FP register
|
||||
fields, they accept both $fN and $vN names for the registers):
|
||||
"O" MDMX alignment offset (OP_*_ALN)
|
||||
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
|
||||
"X" MDMX destination register (OP_*_FD)
|
||||
"Y" MDMX source register (OP_*_FS)
|
||||
"Z" MDMX source register (OP_*_FT)
|
||||
|
||||
Other:
|
||||
"()" parens surrounding optional value
|
||||
"," separates operands
|
||||
"[]" brackets around index for vector-op scalar operand specifier (vr5400)
|
||||
"+" Start of extension sequence.
|
||||
|
||||
Characters used so far, for quick reference when adding more:
|
||||
"%[]<>(),+"
|
||||
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
||||
"abcdefhijklopqrstuvwxz"
|
||||
|
||||
Extension character sequences used so far ("+" followed by the
|
||||
following), for quick reference when adding more:
|
||||
"ABCDEFGHI"
|
||||
*/
|
||||
|
||||
/* These are the bits which may be set in the pinfo field of an
|
||||
instructions, if it is not equal to INSN_MACRO. */
|
||||
|
||||
/* Modifies the general purpose register in OP_*_RD. */
|
||||
#define INSN_WRITE_GPR_D 0x00000001
|
||||
/* Modifies the general purpose register in OP_*_RT. */
|
||||
#define INSN_WRITE_GPR_T 0x00000002
|
||||
/* Modifies general purpose register 31. */
|
||||
#define INSN_WRITE_GPR_31 0x00000004
|
||||
/* Modifies the floating point register in OP_*_FD. */
|
||||
#define INSN_WRITE_FPR_D 0x00000008
|
||||
/* Modifies the floating point register in OP_*_FS. */
|
||||
#define INSN_WRITE_FPR_S 0x00000010
|
||||
/* Modifies the floating point register in OP_*_FT. */
|
||||
#define INSN_WRITE_FPR_T 0x00000020
|
||||
/* Reads the general purpose register in OP_*_RS. */
|
||||
#define INSN_READ_GPR_S 0x00000040
|
||||
/* Reads the general purpose register in OP_*_RT. */
|
||||
#define INSN_READ_GPR_T 0x00000080
|
||||
/* Reads the floating point register in OP_*_FS. */
|
||||
#define INSN_READ_FPR_S 0x00000100
|
||||
/* Reads the floating point register in OP_*_FT. */
|
||||
#define INSN_READ_FPR_T 0x00000200
|
||||
/* Reads the floating point register in OP_*_FR. */
|
||||
#define INSN_READ_FPR_R 0x00000400
|
||||
/* Modifies coprocessor condition code. */
|
||||
#define INSN_WRITE_COND_CODE 0x00000800
|
||||
/* Reads coprocessor condition code. */
|
||||
#define INSN_READ_COND_CODE 0x00001000
|
||||
/* TLB operation. */
|
||||
#define INSN_TLB 0x00002000
|
||||
/* Reads coprocessor register other than floating point register. */
|
||||
#define INSN_COP 0x00004000
|
||||
/* Instruction loads value from memory, requiring delay. */
|
||||
#define INSN_LOAD_MEMORY_DELAY 0x00008000
|
||||
/* Instruction loads value from coprocessor, requiring delay. */
|
||||
#define INSN_LOAD_COPROC_DELAY 0x00010000
|
||||
/* Instruction has unconditional branch delay slot. */
|
||||
#define INSN_UNCOND_BRANCH_DELAY 0x00020000
|
||||
/* Instruction has conditional branch delay slot. */
|
||||
#define INSN_COND_BRANCH_DELAY 0x00040000
|
||||
/* Conditional branch likely: if branch not taken, insn nullified. */
|
||||
#define INSN_COND_BRANCH_LIKELY 0x00080000
|
||||
/* Moves to coprocessor register, requiring delay. */
|
||||
#define INSN_COPROC_MOVE_DELAY 0x00100000
|
||||
/* Loads coprocessor register from memory, requiring delay. */
|
||||
#define INSN_COPROC_MEMORY_DELAY 0x00200000
|
||||
/* Reads the HI register. */
|
||||
#define INSN_READ_HI 0x00400000
|
||||
/* Reads the LO register. */
|
||||
#define INSN_READ_LO 0x00800000
|
||||
/* Modifies the HI register. */
|
||||
#define INSN_WRITE_HI 0x01000000
|
||||
/* Modifies the LO register. */
|
||||
#define INSN_WRITE_LO 0x02000000
|
||||
/* Takes a trap (easier to keep out of delay slot). */
|
||||
#define INSN_TRAP 0x04000000
|
||||
/* Instruction stores value into memory. */
|
||||
#define INSN_STORE_MEMORY 0x08000000
|
||||
/* Instruction uses single precision floating point. */
|
||||
#define FP_S 0x10000000
|
||||
/* Instruction uses double precision floating point. */
|
||||
#define FP_D 0x20000000
|
||||
/* Instruction is part of the tx39's integer multiply family. */
|
||||
#define INSN_MULT 0x40000000
|
||||
/* Instruction synchronize shared memory. */
|
||||
#define INSN_SYNC 0x80000000
|
||||
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_READ_MDMX_ACC 0
|
||||
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_WRITE_MDMX_ACC 0
|
||||
|
||||
/* Instruction is actually a macro. It should be ignored by the
|
||||
disassembler, and requires special treatment by the assembler. */
|
||||
#define INSN_MACRO 0xffffffff
|
||||
|
||||
/* Masks used to mark instructions to indicate which MIPS ISA level
|
||||
they were introduced in. ISAs, as defined below, are logical
|
||||
ORs of these bits, indicating that they support the instructions
|
||||
defined at the given level. */
|
||||
|
||||
#define INSN_ISA_MASK 0x00000fff
|
||||
#define INSN_ISA1 0x00000001
|
||||
#define INSN_ISA2 0x00000002
|
||||
#define INSN_ISA3 0x00000004
|
||||
#define INSN_ISA4 0x00000008
|
||||
#define INSN_ISA5 0x00000010
|
||||
#define INSN_ISA32 0x00000020
|
||||
#define INSN_ISA64 0x00000040
|
||||
#define INSN_ISA32R2 0x00000080
|
||||
#define INSN_ISA64R2 0x00000100
|
||||
|
||||
/* Masks used for MIPS-defined ASEs. */
|
||||
#define INSN_ASE_MASK 0x0000f000
|
||||
|
||||
/* MIPS 16 ASE */
|
||||
#define INSN_MIPS16 0x00002000
|
||||
/* MIPS-3D ASE */
|
||||
#define INSN_MIPS3D 0x00004000
|
||||
/* MDMX ASE */
|
||||
#define INSN_MDMX 0x00008000
|
||||
|
||||
/* Chip specific instructions. These are bitmasks. */
|
||||
|
||||
/* MIPS R4650 instruction. */
|
||||
#define INSN_4650 0x00010000
|
||||
/* LSI R4010 instruction. */
|
||||
#define INSN_4010 0x00020000
|
||||
/* NEC VR4100 instruction. */
|
||||
#define INSN_4100 0x00040000
|
||||
/* Toshiba R3900 instruction. */
|
||||
#define INSN_3900 0x00080000
|
||||
/* MIPS R10000 instruction. */
|
||||
#define INSN_10000 0x00100000
|
||||
/* Broadcom SB-1 instruction. */
|
||||
#define INSN_SB1 0x00200000
|
||||
/* NEC VR4111/VR4181 instruction. */
|
||||
#define INSN_4111 0x00400000
|
||||
/* NEC VR4120 instruction. */
|
||||
#define INSN_4120 0x00800000
|
||||
/* NEC VR5400 instruction. */
|
||||
#define INSN_5400 0x01000000
|
||||
/* NEC VR5500 instruction. */
|
||||
#define INSN_5500 0x02000000
|
||||
|
||||
/* MIPS ISA defines, use instead of hardcoding ISA level. */
|
||||
|
||||
#define ISA_UNKNOWN 0 /* Gas internal use. */
|
||||
#define ISA_MIPS1 (INSN_ISA1)
|
||||
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
|
||||
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
|
||||
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
|
||||
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
|
||||
|
||||
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
|
||||
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
|
||||
|
||||
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
|
||||
#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
|
||||
|
||||
|
||||
/* CPU defines, use instead of hardcoding processor number. Keep this
|
||||
in sync with bfd/archures.c in order for machine selection to work. */
|
||||
#define CPU_UNKNOWN 0 /* Gas internal use. */
|
||||
#define CPU_R3000 3000
|
||||
#define CPU_R3900 3900
|
||||
#define CPU_R4000 4000
|
||||
#define CPU_R4010 4010
|
||||
#define CPU_VR4100 4100
|
||||
#define CPU_R4111 4111
|
||||
#define CPU_VR4120 4120
|
||||
#define CPU_R4300 4300
|
||||
#define CPU_R4400 4400
|
||||
#define CPU_R4600 4600
|
||||
#define CPU_R4650 4650
|
||||
#define CPU_R5000 5000
|
||||
#define CPU_VR5400 5400
|
||||
#define CPU_VR5500 5500
|
||||
#define CPU_R6000 6000
|
||||
#define CPU_RM7000 7000
|
||||
#define CPU_R8000 8000
|
||||
#define CPU_R10000 10000
|
||||
#define CPU_R12000 12000
|
||||
#define CPU_MIPS16 16
|
||||
#define CPU_MIPS32 32
|
||||
#define CPU_MIPS32R2 33
|
||||
#define CPU_MIPS5 5
|
||||
#define CPU_MIPS64 64
|
||||
#define CPU_MIPS64R2 65
|
||||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||||
|
||||
/* Test for membership in an ISA including chip specific ISAs. INSN
|
||||
is pointer to an element of the opcode table; ISA is the specified
|
||||
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
||||
test, or zero if no CPU specific ISA test is desired. */
|
||||
|
||||
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
||||
(((insn)->membership & isa) != 0 \
|
||||
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
||||
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
|
||||
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
||||
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|
||||
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|
||||
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
|
||||
&& ((insn)->membership & INSN_10000) != 0) \
|
||||
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|
||||
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|
||||
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|
||||
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|
||||
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|
||||
|| 0) /* Please keep this term for easier source merging. */
|
||||
|
||||
/* This is a list of macro expanded instructions.
|
||||
|
||||
_I appended means immediate
|
||||
_A appended means address
|
||||
_AB appended means address with base register
|
||||
_D appended means 64 bit floating point constant
|
||||
_S appended means 32 bit floating point constant. */
|
||||
|
||||
enum
|
||||
{
|
||||
M_ABS,
|
||||
M_ADD_I,
|
||||
M_ADDU_I,
|
||||
M_AND_I,
|
||||
M_BEQ,
|
||||
M_BEQ_I,
|
||||
M_BEQL_I,
|
||||
M_BGE,
|
||||
M_BGEL,
|
||||
M_BGE_I,
|
||||
M_BGEL_I,
|
||||
M_BGEU,
|
||||
M_BGEUL,
|
||||
M_BGEU_I,
|
||||
M_BGEUL_I,
|
||||
M_BGT,
|
||||
M_BGTL,
|
||||
M_BGT_I,
|
||||
M_BGTL_I,
|
||||
M_BGTU,
|
||||
M_BGTUL,
|
||||
M_BGTU_I,
|
||||
M_BGTUL_I,
|
||||
M_BLE,
|
||||
M_BLEL,
|
||||
M_BLE_I,
|
||||
M_BLEL_I,
|
||||
M_BLEU,
|
||||
M_BLEUL,
|
||||
M_BLEU_I,
|
||||
M_BLEUL_I,
|
||||
M_BLT,
|
||||
M_BLTL,
|
||||
M_BLT_I,
|
||||
M_BLTL_I,
|
||||
M_BLTU,
|
||||
M_BLTUL,
|
||||
M_BLTU_I,
|
||||
M_BLTUL_I,
|
||||
M_BNE,
|
||||
M_BNE_I,
|
||||
M_BNEL_I,
|
||||
M_DABS,
|
||||
M_DADD_I,
|
||||
M_DADDU_I,
|
||||
M_DDIV_3,
|
||||
M_DDIV_3I,
|
||||
M_DDIVU_3,
|
||||
M_DDIVU_3I,
|
||||
M_DEXT,
|
||||
M_DINS,
|
||||
M_DIV_3,
|
||||
M_DIV_3I,
|
||||
M_DIVU_3,
|
||||
M_DIVU_3I,
|
||||
M_DLA_AB,
|
||||
M_DLCA_AB,
|
||||
M_DLI,
|
||||
M_DMUL,
|
||||
M_DMUL_I,
|
||||
M_DMULO,
|
||||
M_DMULO_I,
|
||||
M_DMULOU,
|
||||
M_DMULOU_I,
|
||||
M_DREM_3,
|
||||
M_DREM_3I,
|
||||
M_DREMU_3,
|
||||
M_DREMU_3I,
|
||||
M_DSUB_I,
|
||||
M_DSUBU_I,
|
||||
M_DSUBU_I_2,
|
||||
M_J_A,
|
||||
M_JAL_1,
|
||||
M_JAL_2,
|
||||
M_JAL_A,
|
||||
M_L_DOB,
|
||||
M_L_DAB,
|
||||
M_LA_AB,
|
||||
M_LB_A,
|
||||
M_LB_AB,
|
||||
M_LBU_A,
|
||||
M_LBU_AB,
|
||||
M_LCA_AB,
|
||||
M_LD_A,
|
||||
M_LD_OB,
|
||||
M_LD_AB,
|
||||
M_LDC1_AB,
|
||||
M_LDC2_AB,
|
||||
M_LDC3_AB,
|
||||
M_LDL_AB,
|
||||
M_LDR_AB,
|
||||
M_LH_A,
|
||||
M_LH_AB,
|
||||
M_LHU_A,
|
||||
M_LHU_AB,
|
||||
M_LI,
|
||||
M_LI_D,
|
||||
M_LI_DD,
|
||||
M_LI_S,
|
||||
M_LI_SS,
|
||||
M_LL_AB,
|
||||
M_LLD_AB,
|
||||
M_LS_A,
|
||||
M_LW_A,
|
||||
M_LW_AB,
|
||||
M_LWC0_A,
|
||||
M_LWC0_AB,
|
||||
M_LWC1_A,
|
||||
M_LWC1_AB,
|
||||
M_LWC2_A,
|
||||
M_LWC2_AB,
|
||||
M_LWC3_A,
|
||||
M_LWC3_AB,
|
||||
M_LWL_A,
|
||||
M_LWL_AB,
|
||||
M_LWR_A,
|
||||
M_LWR_AB,
|
||||
M_LWU_AB,
|
||||
M_MOVE,
|
||||
M_MUL,
|
||||
M_MUL_I,
|
||||
M_MULO,
|
||||
M_MULO_I,
|
||||
M_MULOU,
|
||||
M_MULOU_I,
|
||||
M_NOR_I,
|
||||
M_OR_I,
|
||||
M_REM_3,
|
||||
M_REM_3I,
|
||||
M_REMU_3,
|
||||
M_REMU_3I,
|
||||
M_DROL,
|
||||
M_ROL,
|
||||
M_DROL_I,
|
||||
M_ROL_I,
|
||||
M_DROR,
|
||||
M_ROR,
|
||||
M_DROR_I,
|
||||
M_ROR_I,
|
||||
M_S_DA,
|
||||
M_S_DOB,
|
||||
M_S_DAB,
|
||||
M_S_S,
|
||||
M_SC_AB,
|
||||
M_SCD_AB,
|
||||
M_SD_A,
|
||||
M_SD_OB,
|
||||
M_SD_AB,
|
||||
M_SDC1_AB,
|
||||
M_SDC2_AB,
|
||||
M_SDC3_AB,
|
||||
M_SDL_AB,
|
||||
M_SDR_AB,
|
||||
M_SEQ,
|
||||
M_SEQ_I,
|
||||
M_SGE,
|
||||
M_SGE_I,
|
||||
M_SGEU,
|
||||
M_SGEU_I,
|
||||
M_SGT,
|
||||
M_SGT_I,
|
||||
M_SGTU,
|
||||
M_SGTU_I,
|
||||
M_SLE,
|
||||
M_SLE_I,
|
||||
M_SLEU,
|
||||
M_SLEU_I,
|
||||
M_SLT_I,
|
||||
M_SLTU_I,
|
||||
M_SNE,
|
||||
M_SNE_I,
|
||||
M_SB_A,
|
||||
M_SB_AB,
|
||||
M_SH_A,
|
||||
M_SH_AB,
|
||||
M_SW_A,
|
||||
M_SW_AB,
|
||||
M_SWC0_A,
|
||||
M_SWC0_AB,
|
||||
M_SWC1_A,
|
||||
M_SWC1_AB,
|
||||
M_SWC2_A,
|
||||
M_SWC2_AB,
|
||||
M_SWC3_A,
|
||||
M_SWC3_AB,
|
||||
M_SWL_A,
|
||||
M_SWL_AB,
|
||||
M_SWR_A,
|
||||
M_SWR_AB,
|
||||
M_SUB_I,
|
||||
M_SUBU_I,
|
||||
M_SUBU_I_2,
|
||||
M_TEQ_I,
|
||||
M_TGE_I,
|
||||
M_TGEU_I,
|
||||
M_TLT_I,
|
||||
M_TLTU_I,
|
||||
M_TNE_I,
|
||||
M_TRUNCWD,
|
||||
M_TRUNCWS,
|
||||
M_ULD,
|
||||
M_ULD_A,
|
||||
M_ULH,
|
||||
M_ULH_A,
|
||||
M_ULHU,
|
||||
M_ULHU_A,
|
||||
M_ULW,
|
||||
M_ULW_A,
|
||||
M_USH,
|
||||
M_USH_A,
|
||||
M_USW,
|
||||
M_USW_A,
|
||||
M_USD,
|
||||
M_USD_A,
|
||||
M_XOR_I,
|
||||
M_COP0,
|
||||
M_COP1,
|
||||
M_COP2,
|
||||
M_COP3,
|
||||
M_NUM_MACROS
|
||||
};
|
||||
|
||||
|
||||
/* The order of overloaded instructions matters. Label arguments and
|
||||
register arguments look the same. Instructions that can have either
|
||||
for arguments must apear in the correct order in this table for the
|
||||
assembler to pick the right one. In other words, entries with
|
||||
immediate operands must apear after the same instruction with
|
||||
registers.
|
||||
|
||||
Many instructions are short hand for other instructions (i.e., The
|
||||
jal <register> instruction is short for jalr <register>). */
|
||||
|
||||
extern const struct mips_opcode mips_builtin_opcodes[];
|
||||
extern const int bfd_mips_num_builtin_opcodes;
|
||||
extern struct mips_opcode *mips_opcodes;
|
||||
extern int bfd_mips_num_opcodes;
|
||||
#define NUMOPCODES bfd_mips_num_opcodes
|
||||
|
||||
|
||||
/* The rest of this file adds definitions for the mips16 TinyRISC
|
||||
processor. */
|
||||
|
||||
/* These are the bitmasks and shift counts used for the different
|
||||
fields in the instruction formats. Other than OP, no masks are
|
||||
provided for the fixed portions of an instruction, since they are
|
||||
not needed.
|
||||
|
||||
The I format uses IMM11.
|
||||
|
||||
The RI format uses RX and IMM8.
|
||||
|
||||
The RR format uses RX, and RY.
|
||||
|
||||
The RRI format uses RX, RY, and IMM5.
|
||||
|
||||
The RRR format uses RX, RY, and RZ.
|
||||
|
||||
The RRI_A format uses RX, RY, and IMM4.
|
||||
|
||||
The SHIFT format uses RX, RY, and SHAMT.
|
||||
|
||||
The I8 format uses IMM8.
|
||||
|
||||
The I8_MOVR32 format uses RY and REGR32.
|
||||
|
||||
The IR_MOV32R format uses REG32R and MOV32Z.
|
||||
|
||||
The I64 format uses IMM8.
|
||||
|
||||
The RI64 format uses RY and IMM5.
|
||||
*/
|
||||
|
||||
#define MIPS16OP_MASK_OP 0x1f
|
||||
#define MIPS16OP_SH_OP 11
|
||||
#define MIPS16OP_MASK_IMM11 0x7ff
|
||||
#define MIPS16OP_SH_IMM11 0
|
||||
#define MIPS16OP_MASK_RX 0x7
|
||||
#define MIPS16OP_SH_RX 8
|
||||
#define MIPS16OP_MASK_IMM8 0xff
|
||||
#define MIPS16OP_SH_IMM8 0
|
||||
#define MIPS16OP_MASK_RY 0x7
|
||||
#define MIPS16OP_SH_RY 5
|
||||
#define MIPS16OP_MASK_IMM5 0x1f
|
||||
#define MIPS16OP_SH_IMM5 0
|
||||
#define MIPS16OP_MASK_RZ 0x7
|
||||
#define MIPS16OP_SH_RZ 2
|
||||
#define MIPS16OP_MASK_IMM4 0xf
|
||||
#define MIPS16OP_SH_IMM4 0
|
||||
#define MIPS16OP_MASK_REGR32 0x1f
|
||||
#define MIPS16OP_SH_REGR32 0
|
||||
#define MIPS16OP_MASK_REG32R 0x1f
|
||||
#define MIPS16OP_SH_REG32R 3
|
||||
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
|
||||
#define MIPS16OP_MASK_MOVE32Z 0x7
|
||||
#define MIPS16OP_SH_MOVE32Z 0
|
||||
#define MIPS16OP_MASK_IMM6 0x3f
|
||||
#define MIPS16OP_SH_IMM6 5
|
||||
|
||||
/* These are the characters which may appears in the args field of an
|
||||
instruction. They appear in the order in which the fields appear
|
||||
when the instruction is used. Commas and parentheses in the args
|
||||
string are ignored when assembling, and written into the output
|
||||
when disassembling.
|
||||
|
||||
"y" 3 bit register (MIPS16OP_*_RY)
|
||||
"x" 3 bit register (MIPS16OP_*_RX)
|
||||
"z" 3 bit register (MIPS16OP_*_RZ)
|
||||
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
||||
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
||||
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
||||
"0" zero register ($0)
|
||||
"S" stack pointer ($sp or $29)
|
||||
"P" program counter
|
||||
"R" return address register ($ra or $31)
|
||||
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
||||
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
||||
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
||||
"a" 26 bit jump address
|
||||
"e" 11 bit extension value
|
||||
"l" register list for entry instruction
|
||||
"L" register list for exit instruction
|
||||
|
||||
The remaining codes may be extended. Except as otherwise noted,
|
||||
the full extended operand is a 16 bit signed value.
|
||||
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
||||
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
||||
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
||||
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
||||
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
||||
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
||||
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
||||
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
||||
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
||||
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
||||
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
||||
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
||||
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
||||
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
||||
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
||||
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
||||
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
||||
"q" 11 bit branch address (MIPS16OP_*_IMM11)
|
||||
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
||||
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
||||
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
||||
*/
|
||||
|
||||
/* For the mips16, we use the same opcode table format and a few of
|
||||
the same flags. However, most of the flags are different. */
|
||||
|
||||
/* Modifies the register in MIPS16OP_*_RX. */
|
||||
#define MIPS16_INSN_WRITE_X 0x00000001
|
||||
/* Modifies the register in MIPS16OP_*_RY. */
|
||||
#define MIPS16_INSN_WRITE_Y 0x00000002
|
||||
/* Modifies the register in MIPS16OP_*_RZ. */
|
||||
#define MIPS16_INSN_WRITE_Z 0x00000004
|
||||
/* Modifies the T ($24) register. */
|
||||
#define MIPS16_INSN_WRITE_T 0x00000008
|
||||
/* Modifies the SP ($29) register. */
|
||||
#define MIPS16_INSN_WRITE_SP 0x00000010
|
||||
/* Modifies the RA ($31) register. */
|
||||
#define MIPS16_INSN_WRITE_31 0x00000020
|
||||
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
||||
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
|
||||
/* Reads the register in MIPS16OP_*_RX. */
|
||||
#define MIPS16_INSN_READ_X 0x00000080
|
||||
/* Reads the register in MIPS16OP_*_RY. */
|
||||
#define MIPS16_INSN_READ_Y 0x00000100
|
||||
/* Reads the register in MIPS16OP_*_MOVE32Z. */
|
||||
#define MIPS16_INSN_READ_Z 0x00000200
|
||||
/* Reads the T ($24) register. */
|
||||
#define MIPS16_INSN_READ_T 0x00000400
|
||||
/* Reads the SP ($29) register. */
|
||||
#define MIPS16_INSN_READ_SP 0x00000800
|
||||
/* Reads the RA ($31) register. */
|
||||
#define MIPS16_INSN_READ_31 0x00001000
|
||||
/* Reads the program counter. */
|
||||
#define MIPS16_INSN_READ_PC 0x00002000
|
||||
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
||||
#define MIPS16_INSN_READ_GPR_X 0x00004000
|
||||
/* Is a branch insn. */
|
||||
#define MIPS16_INSN_BRANCH 0x00010000
|
||||
|
||||
/* The following flags have the same value for the mips16 opcode
|
||||
table:
|
||||
INSN_UNCOND_BRANCH_DELAY
|
||||
INSN_COND_BRANCH_DELAY
|
||||
INSN_COND_BRANCH_LIKELY (never used)
|
||||
INSN_READ_HI
|
||||
INSN_READ_LO
|
||||
INSN_WRITE_HI
|
||||
INSN_WRITE_LO
|
||||
INSN_TRAP
|
||||
INSN_ISA3
|
||||
*/
|
||||
|
||||
extern const struct mips_opcode mips16_opcodes[];
|
||||
extern const int bfd_mips16_num_opcodes;
|
||||
|
||||
#endif /* _MIPS_H_ */
|
||||
58
contrib/binutils/ld/emulparams/elf32bmipn32-defs.sh
Normal file
58
contrib/binutils/ld/emulparams/elf32bmipn32-defs.sh
Normal file
@ -0,0 +1,58 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf64bmip.sh elf64btsmip.sh elf32btsmipn32.sh elf32bmipn32.sh
|
||||
|
||||
# This is an ELF platform.
|
||||
SCRIPT_NAME=elf
|
||||
|
||||
# Handle both big- and little-ended 32-bit MIPS objects.
|
||||
ARCH=mips
|
||||
OUTPUT_FORMAT="elf32-bigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
|
||||
TEMPLATE_NAME=elf32
|
||||
|
||||
case "$EMULATION_NAME" in
|
||||
elf32*n32*) ELFSIZE=32 ;;
|
||||
elf64*) ELFSIZE=64 ;;
|
||||
*) echo $0: unhandled emulation $EMULATION_NAME >&2; exit 1 ;;
|
||||
esac
|
||||
|
||||
if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then
|
||||
case " $EMULATION_LIBPATH " in
|
||||
*" ${EMULATION_NAME} "*)
|
||||
NATIVE=yes
|
||||
;;
|
||||
esac
|
||||
fi
|
||||
|
||||
# Look for 64 bit target libraries in /lib64, /usr/lib64 etc., first.
|
||||
LIBPATH_SUFFIX=$ELFSIZE
|
||||
|
||||
GENERATE_SHLIB_SCRIPT=yes
|
||||
|
||||
TEXT_START_ADDR=0x10000000
|
||||
MAXPAGESIZE=0x100000
|
||||
ENTRY=__start
|
||||
|
||||
# GOT-related settings.
|
||||
OTHER_GOT_SYMBOLS='
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
'
|
||||
OTHER_SDATA_SECTIONS="
|
||||
.lit8 ${RELOCATING-0} : { *(.lit8) }
|
||||
.lit4 ${RELOCATING-0} : { *(.lit4) }
|
||||
.srdata ${RELOCATING-0} : { *(.srdata) }
|
||||
"
|
||||
|
||||
# Magic symbols.
|
||||
TEXT_START_SYMBOLS='_ftext = . ;'
|
||||
DATA_START_SYMBOLS='_fdata = . ;'
|
||||
OTHER_BSS_SYMBOLS='_fbss = .;'
|
||||
|
||||
INITIAL_READONLY_SECTIONS=".MIPS.options : { *(.MIPS.options) }"
|
||||
# Discard any .MIPS.content* or .MIPS.events* sections. The linker
|
||||
# doesn't know how to adjust them.
|
||||
OTHER_SECTIONS="/DISCARD/ : { *(.MIPS.content*) *(.MIPS.events*) }"
|
||||
|
||||
TEXT_DYNAMIC=
|
||||
9
contrib/binutils/ld/emulparams/elf32btsmip.sh
Normal file
9
contrib/binutils/ld/emulparams/elf32btsmip.sh
Normal file
@ -0,0 +1,9 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf32ltsmip.sh
|
||||
|
||||
. ${srcdir}/emulparams/elf32bmip.sh
|
||||
OUTPUT_FORMAT="elf32-tradbigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-tradbigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-tradlittlemips"
|
||||
SHLIB_TEXT_START_ADDR=0
|
||||
ENTRY=__start
|
||||
15
contrib/binutils/ld/emulparams/elf32btsmipn32.sh
Normal file
15
contrib/binutils/ld/emulparams/elf32btsmipn32.sh
Normal file
@ -0,0 +1,15 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf32ltsmipn32.sh
|
||||
|
||||
. ${srcdir}/emulparams/elf32bmipn32-defs.sh
|
||||
OUTPUT_FORMAT="elf32-ntradbigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-ntradbigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-ntradlittlemips"
|
||||
COMMONPAGESIZE=0x1000
|
||||
|
||||
# Magic sections.
|
||||
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
|
||||
OTHER_SECTIONS='
|
||||
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
|
||||
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
|
||||
'
|
||||
2
contrib/binutils/ld/emulparams/elf32ltsmip.sh
Normal file
2
contrib/binutils/ld/emulparams/elf32ltsmip.sh
Normal file
@ -0,0 +1,2 @@
|
||||
. ${srcdir}/emulparams/elf32btsmip.sh
|
||||
OUTPUT_FORMAT="elf32-tradlittlemips"
|
||||
4
contrib/binutils/ld/emulparams/elf32ltsmipn32.sh
Normal file
4
contrib/binutils/ld/emulparams/elf32ltsmipn32.sh
Normal file
@ -0,0 +1,4 @@
|
||||
. ${srcdir}/emulparams/elf32btsmipn32.sh
|
||||
OUTPUT_FORMAT="elf32-ntradlittlemips"
|
||||
BIG_OUTPUT_FORMAT="elf32-ntradbigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-ntradlittlemips"
|
||||
27
contrib/binutils/ld/emulparams/elf32mipswindiss.sh
Normal file
27
contrib/binutils/ld/emulparams/elf32mipswindiss.sh
Normal file
@ -0,0 +1,27 @@
|
||||
TEMPLATE_NAME=elf32
|
||||
SCRIPT_NAME=elf
|
||||
OUTPUT_FORMAT="elf32-bigmips"
|
||||
BIG_OUTPUT_FORMAT="elf32-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
|
||||
ARCH=mips
|
||||
MACHINE=
|
||||
EMBEDDED=yes
|
||||
MAXPAGESIZE=0x40000
|
||||
|
||||
# The data below is taken from the windiss.dld linker script that comes with
|
||||
# the Diab linker.
|
||||
TEXT_START_ADDR=0x100000
|
||||
DATA_START_SYMBOLS='__DATA_ROM = .; __DATA_RAM = .;'
|
||||
SDATA_START_SYMBOLS='_SDA_BASE_ = .; _gp = . + 0x7ff0;'
|
||||
SDATA2_START_SYMBOLS='_SDA2_BASE_ = .;'
|
||||
EXECUTABLE_SYMBOLS='__HEAP_START = .; __SP_INIT = 0x800000; __SP_END = __SP_INIT - 0x20000; __HEAP_END = __SP_END; __DATA_END = _edata; __BSS_START = __bss_start; __BSS_END = _end; __HEAP_START = _end;'
|
||||
|
||||
# The Diab tools use a different init/fini convention. Initialization code
|
||||
# is place in sections named ".init$NN". These sections are then concatenated
|
||||
# into the .init section. It is important that .init$00 be first and .init$99
|
||||
# be last. The other sections should be sorted, but the current linker script
|
||||
# parse does not seem to allow that with the SORT keyword in this context.
|
||||
INIT_START='*(.init$00); *(.init$0[1-9]); *(.init$[1-8][0-9]); *(.init$9[0-8])'
|
||||
INIT_END='*(.init$99)'
|
||||
FINI_START='*(.fini$00); *(.fini$0[1-9]); *(.fini$[1-8][0-9]); *(.fini$9[0-8])'
|
||||
FINI_END='*(.fini$99)'
|
||||
16
contrib/binutils/ld/emulparams/elf64btsmip.sh
Normal file
16
contrib/binutils/ld/emulparams/elf64btsmip.sh
Normal file
@ -0,0 +1,16 @@
|
||||
# If you change this file, please also look at files which source this one:
|
||||
# elf64ltsmip.sh
|
||||
|
||||
. ${srcdir}/emulparams/elf32bmipn32-defs.sh
|
||||
OUTPUT_FORMAT="elf64-tradbigmips"
|
||||
BIG_OUTPUT_FORMAT="elf64-tradbigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf64-tradlittlemips"
|
||||
|
||||
# Magic sections.
|
||||
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
|
||||
OTHER_SECTIONS='
|
||||
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
|
||||
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
|
||||
'
|
||||
|
||||
TEXT_START_ADDR="0x120000000"
|
||||
4
contrib/binutils/ld/emulparams/elf64ltsmip.sh
Normal file
4
contrib/binutils/ld/emulparams/elf64ltsmip.sh
Normal file
@ -0,0 +1,4 @@
|
||||
. ${srcdir}/emulparams/elf64btsmip.sh
|
||||
OUTPUT_FORMAT="elf64-tradlittlemips"
|
||||
BIG_OUTPUT_FORMAT="elf64-tradbigmips"
|
||||
LITTLE_OUTPUT_FORMAT="elf64-tradlittlemips"
|
||||
6
contrib/binutils/ld/emulparams/mipsbig.sh
Normal file
6
contrib/binutils/ld/emulparams/mipsbig.sh
Normal file
@ -0,0 +1,6 @@
|
||||
SCRIPT_NAME=mips
|
||||
OUTPUT_FORMAT="ecoff-bigmips"
|
||||
BIG_OUTPUT_FORMAT="ecoff-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TARGET_PAGE_SIZE=0x1000000
|
||||
ARCH=mips
|
||||
7
contrib/binutils/ld/emulparams/mipsbsd.sh
Normal file
7
contrib/binutils/ld/emulparams/mipsbsd.sh
Normal file
@ -0,0 +1,7 @@
|
||||
SCRIPT_NAME=mipsbsd
|
||||
OUTPUT_FORMAT="a.out-mips-little"
|
||||
BIG_OUTPUT_FORMAT="a.out-mips-big"
|
||||
LITTLE_OUTPUT_FORMAT="a.out-mips-little"
|
||||
TEXT_START_ADDR=0x1020
|
||||
TARGET_PAGE_SIZE=4096
|
||||
ARCH=mips
|
||||
11
contrib/binutils/ld/emulparams/mipsidt.sh
Normal file
11
contrib/binutils/ld/emulparams/mipsidt.sh
Normal file
@ -0,0 +1,11 @@
|
||||
SCRIPT_NAME=mips
|
||||
OUTPUT_FORMAT="ecoff-bigmips"
|
||||
BIG_OUTPUT_FORMAT="ecoff-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TARGET_PAGE_SIZE=0x1000000
|
||||
ARCH=mips
|
||||
ENTRY=start
|
||||
TEXT_START_ADDR=0xa0012000
|
||||
DATA_ADDR=.
|
||||
TEMPLATE_NAME=mipsecoff
|
||||
EMBEDDED=yes
|
||||
11
contrib/binutils/ld/emulparams/mipsidtl.sh
Normal file
11
contrib/binutils/ld/emulparams/mipsidtl.sh
Normal file
@ -0,0 +1,11 @@
|
||||
SCRIPT_NAME=mips
|
||||
OUTPUT_FORMAT="ecoff-littlemips"
|
||||
BIG_OUTPUT_FORMAT="ecoff-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TARGET_PAGE_SIZE=0x1000000
|
||||
ARCH=mips
|
||||
ENTRY=start
|
||||
TEXT_START_ADDR=0xa0012000
|
||||
DATA_ADDR=.
|
||||
TEMPLATE_NAME=mipsecoff
|
||||
EMBEDDED=yes
|
||||
6
contrib/binutils/ld/emulparams/mipslit.sh
Normal file
6
contrib/binutils/ld/emulparams/mipslit.sh
Normal file
@ -0,0 +1,6 @@
|
||||
SCRIPT_NAME=mips
|
||||
OUTPUT_FORMAT="ecoff-littlemips"
|
||||
BIG_OUTPUT_FORMAT="ecoff-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TARGET_PAGE_SIZE=0x1000000
|
||||
ARCH=mips
|
||||
9
contrib/binutils/ld/emulparams/mipslnews.sh
Normal file
9
contrib/binutils/ld/emulparams/mipslnews.sh
Normal file
@ -0,0 +1,9 @@
|
||||
SCRIPT_NAME=mips
|
||||
OUTPUT_FORMAT="ecoff-littlemips"
|
||||
BIG_OUTPUT_FORMAT="ecoff-bigmips"
|
||||
LITTLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TARGET_PAGE_SIZE=0x1000000
|
||||
ARCH=mips
|
||||
TEXT_START_ADDR=0x80080000
|
||||
DATA_ADDR=.
|
||||
EMBEDDED=yes
|
||||
9
contrib/binutils/ld/emulparams/mipspe.sh
Normal file
9
contrib/binutils/ld/emulparams/mipspe.sh
Normal file
@ -0,0 +1,9 @@
|
||||
ARCH=mips
|
||||
SCRIPT_NAME=pe
|
||||
OUTPUT_FORMAT="pei-mips"
|
||||
OUTPUT_ARCH="mips"
|
||||
RELOCATEABLE_OUTPUT_FORMAT="ecoff-littlemips"
|
||||
TEMPLATE_NAME=pe
|
||||
SUBSYSTEM=PE_DEF_SUBSYSTEM
|
||||
INITIAL_SYMBOL_CHAR=\"_\"
|
||||
ENTRY="_mainCRTStartup"
|
||||
248
contrib/binutils/ld/emultempl/mipsecoff.em
Normal file
248
contrib/binutils/ld/emultempl/mipsecoff.em
Normal file
@ -0,0 +1,248 @@
|
||||
# This shell script emits a C file. -*- C -*-
|
||||
# It does some substitutions.
|
||||
if [ -z "$MACHINE" ]; then
|
||||
OUTPUT_ARCH=${ARCH}
|
||||
else
|
||||
OUTPUT_ARCH=${ARCH}:${MACHINE}
|
||||
fi
|
||||
cat >e${EMULATION_NAME}.c <<EOF
|
||||
/* This file is is generated by a shell script. DO NOT EDIT! */
|
||||
|
||||
/* Handle embedded relocs for MIPS.
|
||||
Copyright 1994, 1995, 1997, 2000, 2002, 2003, 2004
|
||||
Free Software Foundation, Inc.
|
||||
Written by Ian Lance Taylor <ian@cygnus.com> based on generic.em.
|
||||
|
||||
This file is part of GLD, the Gnu Linker.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#define TARGET_IS_${EMULATION_NAME}
|
||||
|
||||
#include "bfd.h"
|
||||
#include "sysdep.h"
|
||||
#include "bfdlink.h"
|
||||
|
||||
#include "ld.h"
|
||||
#include "ldmain.h"
|
||||
#include "ldmisc.h"
|
||||
|
||||
#include "ldexp.h"
|
||||
#include "ldlang.h"
|
||||
#include "ldfile.h"
|
||||
#include "ldemul.h"
|
||||
|
||||
static void check_sections (bfd *, asection *, void *);
|
||||
|
||||
static void
|
||||
gld${EMULATION_NAME}_before_parse (void)
|
||||
{
|
||||
#ifndef TARGET_ /* I.e., if not generic. */
|
||||
ldfile_set_output_arch ("${OUTPUT_ARCH}", bfd_arch_`echo ${ARCH} | sed -e 's/:.*//'`);
|
||||
#endif /* not TARGET_ */
|
||||
}
|
||||
|
||||
/* This function is run after all the input files have been opened.
|
||||
We create a .rel.sdata section for each input file with a non zero
|
||||
.sdata section. The BFD backend will fill in these sections with
|
||||
magic numbers which can be used to relocate the data section at run
|
||||
time. This will only do the right thing if all the input files
|
||||
have been compiled using -membedded-pic. */
|
||||
|
||||
static void
|
||||
gld${EMULATION_NAME}_after_open (void)
|
||||
{
|
||||
bfd *abfd;
|
||||
|
||||
if (! command_line.embedded_relocs
|
||||
|| link_info.relocatable)
|
||||
return;
|
||||
|
||||
for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
|
||||
{
|
||||
asection *datasec;
|
||||
|
||||
/* As first-order business, make sure that each input BFD is ECOFF. It
|
||||
better be, as we are directly calling an ECOFF backend function. */
|
||||
if (bfd_get_flavour (abfd) != bfd_target_ecoff_flavour)
|
||||
einfo ("%F%B: all input objects must be ECOFF for --embedded-relocs\n");
|
||||
|
||||
datasec = bfd_get_section_by_name (abfd, ".sdata");
|
||||
|
||||
/* Note that we assume that the reloc_count field has already
|
||||
been set up. We could call bfd_get_reloc_upper_bound, but
|
||||
that returns the size of a memory buffer rather than a reloc
|
||||
count. We do not want to call bfd_canonicalize_reloc,
|
||||
because although it would always work it would force us to
|
||||
read in the relocs into BFD canonical form, which would waste
|
||||
a significant amount of time and memory. */
|
||||
if (datasec != NULL && datasec->reloc_count > 0)
|
||||
{
|
||||
asection *relsec;
|
||||
|
||||
relsec = bfd_make_section (abfd, ".rel.sdata");
|
||||
if (relsec == NULL
|
||||
|| ! bfd_set_section_flags (abfd, relsec,
|
||||
(SEC_ALLOC
|
||||
| SEC_LOAD
|
||||
| SEC_HAS_CONTENTS
|
||||
| SEC_IN_MEMORY))
|
||||
|| ! bfd_set_section_alignment (abfd, relsec, 2)
|
||||
|| ! bfd_set_section_size (abfd, relsec,
|
||||
datasec->reloc_count * 4))
|
||||
einfo ("%F%B: can not create .rel.sdata section: %E\n");
|
||||
}
|
||||
|
||||
/* Double check that all other data sections are empty, as is
|
||||
required for embedded PIC code. */
|
||||
bfd_map_over_sections (abfd, check_sections, datasec);
|
||||
}
|
||||
}
|
||||
|
||||
/* Check that of the data sections, only the .sdata section has
|
||||
relocs. This is called via bfd_map_over_sections. */
|
||||
|
||||
static void
|
||||
check_sections (bfd *abfd, asection *sec, void *sdatasec)
|
||||
{
|
||||
if ((bfd_get_section_flags (abfd, sec) & SEC_CODE) == 0
|
||||
&& sec != sdatasec
|
||||
&& sec->reloc_count != 0)
|
||||
einfo ("%B%X: section %s has relocs; can not use --embedded-relocs\n",
|
||||
abfd, bfd_get_section_name (abfd, sec));
|
||||
}
|
||||
|
||||
/* This function is called after the section sizes and offsets have
|
||||
been set. If we are generating embedded relocs, it calls a special
|
||||
BFD backend routine to do the work. */
|
||||
|
||||
static void
|
||||
gld${EMULATION_NAME}_after_allocation (void)
|
||||
{
|
||||
bfd *abfd;
|
||||
|
||||
if (! command_line.embedded_relocs
|
||||
|| link_info.relocatable)
|
||||
return;
|
||||
|
||||
for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
|
||||
{
|
||||
asection *datasec, *relsec;
|
||||
char *errmsg;
|
||||
|
||||
datasec = bfd_get_section_by_name (abfd, ".sdata");
|
||||
|
||||
if (datasec == NULL || datasec->reloc_count == 0)
|
||||
continue;
|
||||
|
||||
relsec = bfd_get_section_by_name (abfd, ".rel.sdata");
|
||||
ASSERT (relsec != NULL);
|
||||
|
||||
if (! bfd_mips_ecoff_create_embedded_relocs (abfd, &link_info,
|
||||
datasec, relsec,
|
||||
&errmsg))
|
||||
{
|
||||
if (errmsg == NULL)
|
||||
einfo ("%B%X: can not create runtime reloc information: %E\n",
|
||||
abfd);
|
||||
else
|
||||
einfo ("%X%B: can not create runtime reloc information: %s\n",
|
||||
abfd, errmsg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static char *
|
||||
gld${EMULATION_NAME}_get_script (int *isfile)
|
||||
EOF
|
||||
|
||||
if test -n "$COMPILE_IN"
|
||||
then
|
||||
# Scripts compiled in.
|
||||
|
||||
# sed commands to quote an ld script as a C string.
|
||||
sc="-f stringify.sed"
|
||||
|
||||
cat >>e${EMULATION_NAME}.c <<EOF
|
||||
{
|
||||
*isfile = 0;
|
||||
|
||||
if (link_info.relocatable && config.build_constructors)
|
||||
return
|
||||
EOF
|
||||
sed $sc ldscripts/${EMULATION_NAME}.xu >> e${EMULATION_NAME}.c
|
||||
echo ' ; else if (link_info.relocatable) return' >> e${EMULATION_NAME}.c
|
||||
sed $sc ldscripts/${EMULATION_NAME}.xr >> e${EMULATION_NAME}.c
|
||||
echo ' ; else if (!config.text_read_only) return' >> e${EMULATION_NAME}.c
|
||||
sed $sc ldscripts/${EMULATION_NAME}.xbn >> e${EMULATION_NAME}.c
|
||||
echo ' ; else if (!config.magic_demand_paged) return' >> e${EMULATION_NAME}.c
|
||||
sed $sc ldscripts/${EMULATION_NAME}.xn >> e${EMULATION_NAME}.c
|
||||
echo ' ; else return' >> e${EMULATION_NAME}.c
|
||||
sed $sc ldscripts/${EMULATION_NAME}.x >> e${EMULATION_NAME}.c
|
||||
echo '; }' >> e${EMULATION_NAME}.c
|
||||
|
||||
else
|
||||
# Scripts read from the filesystem.
|
||||
|
||||
cat >>e${EMULATION_NAME}.c <<EOF
|
||||
{
|
||||
*isfile = 1;
|
||||
|
||||
if (link_info.relocatable && config.build_constructors)
|
||||
return "ldscripts/${EMULATION_NAME}.xu";
|
||||
else if (link_info.relocatable)
|
||||
return "ldscripts/${EMULATION_NAME}.xr";
|
||||
else if (!config.text_read_only)
|
||||
return "ldscripts/${EMULATION_NAME}.xbn";
|
||||
else if (!config.magic_demand_paged)
|
||||
return "ldscripts/${EMULATION_NAME}.xn";
|
||||
else
|
||||
return "ldscripts/${EMULATION_NAME}.x";
|
||||
}
|
||||
EOF
|
||||
|
||||
fi
|
||||
|
||||
cat >>e${EMULATION_NAME}.c <<EOF
|
||||
|
||||
struct ld_emulation_xfer_struct ld_${EMULATION_NAME}_emulation =
|
||||
{
|
||||
gld${EMULATION_NAME}_before_parse,
|
||||
syslib_default,
|
||||
hll_default,
|
||||
after_parse_default,
|
||||
gld${EMULATION_NAME}_after_open,
|
||||
gld${EMULATION_NAME}_after_allocation,
|
||||
set_output_arch_default,
|
||||
ldemul_default_target,
|
||||
before_allocation_default,
|
||||
gld${EMULATION_NAME}_get_script,
|
||||
"${EMULATION_NAME}",
|
||||
"${OUTPUT_FORMAT}",
|
||||
NULL, /* finish */
|
||||
NULL, /* create output section statements */
|
||||
NULL, /* open dynamic archive */
|
||||
NULL, /* place orphan */
|
||||
NULL, /* set symbols */
|
||||
NULL, /* parse args */
|
||||
NULL, /* add_options */
|
||||
NULL, /* handle_option */
|
||||
NULL, /* unrecognized file */
|
||||
NULL, /* list options */
|
||||
NULL, /* recognized file */
|
||||
NULL, /* find_potential_libraries */
|
||||
NULL /* new_vers_pattern */
|
||||
};
|
||||
EOF
|
||||
177
contrib/binutils/ld/emultempl/mipself.em
Normal file
177
contrib/binutils/ld/emultempl/mipself.em
Normal file
@ -0,0 +1,177 @@
|
||||
# This shell script emits a C file. -*- C -*-
|
||||
# Copyright 2002, 2003 Free Software Foundation, Inc.
|
||||
# Written by Mitch Lichtenberg <mpl@broadcom.com> and
|
||||
# Chris Demetriou <cgd@broadcom.com> based on m68kelf.em and mipsecoff.em.
|
||||
#
|
||||
# This file is part of GLD, the Gnu Linker.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
|
||||
# This file is sourced from elf32.em, and defines some extra routines for m68k
|
||||
# embedded systems using ELF and for some other systems using m68k ELF. While
|
||||
# it is sourced from elf32.em for all m68k ELF configurations, here we include
|
||||
# only the features we want depending on the configuration.
|
||||
|
||||
case ${target} in
|
||||
mips*-*-elf)
|
||||
echo "#define SUPPORT_EMBEDDED_RELOCS" >>e${EMULATION_NAME}.c
|
||||
;;
|
||||
esac
|
||||
|
||||
cat >>e${EMULATION_NAME}.c <<EOF
|
||||
|
||||
#ifdef SUPPORT_EMBEDDED_RELOCS
|
||||
static void mips_elf${ELFSIZE}_check_sections (bfd *, asection *, void *);
|
||||
#endif
|
||||
|
||||
/* This function is run after all the input files have been opened. */
|
||||
|
||||
static void
|
||||
mips_elf${ELFSIZE}_after_open (void)
|
||||
{
|
||||
/* Call the standard elf routine. */
|
||||
gld${EMULATION_NAME}_after_open ();
|
||||
|
||||
#ifdef SUPPORT_EMBEDDED_RELOCS
|
||||
if (command_line.embedded_relocs && (! link_info.relocatable))
|
||||
{
|
||||
bfd *abfd;
|
||||
|
||||
/* In the embedded relocs mode we create a .rel.sdata section for
|
||||
each input file with a .sdata section which has has
|
||||
relocations. The BFD backend will fill in these sections
|
||||
with magic numbers which can be used to relocate the data
|
||||
section at run time. */
|
||||
for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
|
||||
{
|
||||
asection *datasec;
|
||||
|
||||
/* As first-order business, make sure that each input BFD is
|
||||
ELF. We need to call a special BFD backend function to
|
||||
generate the embedded relocs, and we have that function
|
||||
only for ELF */
|
||||
|
||||
if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
|
||||
einfo ("%F%B: all input objects must be ELF for --embedded-relocs\n");
|
||||
|
||||
if (bfd_get_arch_size (abfd) != ${ELFSIZE})
|
||||
einfo ("%F%B: all input objects must be ${ELFSIZE}-bit ELF for --embedded-relocs\n");
|
||||
|
||||
datasec = bfd_get_section_by_name (abfd, ".sdata");
|
||||
|
||||
/* Note that we assume that the reloc_count field has already
|
||||
been set up. We could call bfd_get_reloc_upper_bound, but
|
||||
that returns the size of a memory buffer rather than a reloc
|
||||
count. We do not want to call bfd_canonicalize_reloc,
|
||||
because although it would always work it would force us to
|
||||
read in the relocs into BFD canonical form, which would waste
|
||||
a significant amount of time and memory. */
|
||||
|
||||
if (datasec != NULL && datasec->reloc_count > 0)
|
||||
{
|
||||
asection *relsec;
|
||||
|
||||
relsec = bfd_make_section (abfd, ".rel.sdata");
|
||||
if (relsec == NULL
|
||||
|| ! bfd_set_section_flags (abfd, relsec,
|
||||
(SEC_ALLOC
|
||||
| SEC_LOAD
|
||||
| SEC_HAS_CONTENTS
|
||||
| SEC_IN_MEMORY))
|
||||
|| ! bfd_set_section_alignment (abfd, relsec,
|
||||
(${ELFSIZE} == 32) ? 2 : 3)
|
||||
|| ! bfd_set_section_size (abfd, relsec,
|
||||
datasec->reloc_count
|
||||
* ((${ELFSIZE} / 8) + 8)))
|
||||
einfo ("%F%B: cannot create .rel.sdata section: %E\n");
|
||||
}
|
||||
|
||||
/* Double check that all other data sections have no relocs,
|
||||
as is required for embedded PIC code. */
|
||||
bfd_map_over_sections (abfd, mips_elf${ELFSIZE}_check_sections,
|
||||
datasec);
|
||||
}
|
||||
}
|
||||
#endif /* SUPPORT_EMBEDDED_RELOCS */
|
||||
}
|
||||
|
||||
#ifdef SUPPORT_EMBEDDED_RELOCS
|
||||
/* Check that of the data sections, only the .sdata section has
|
||||
relocs. This is called via bfd_map_over_sections. */
|
||||
|
||||
static void
|
||||
mips_elf${ELFSIZE}_check_sections (bfd *abfd, asection *sec, void *sdatasec)
|
||||
{
|
||||
if ((bfd_get_section_flags (abfd, sec) & SEC_DATA)
|
||||
&& sec != sdatasec
|
||||
&& sec->reloc_count != 0)
|
||||
einfo ("%B%X: section %s has relocs; cannot use --embedded-relocs\n",
|
||||
abfd, bfd_get_section_name (abfd, sec));
|
||||
}
|
||||
#endif /* SUPPORT_EMBEDDED_RELOCS */
|
||||
|
||||
/* This function is called after the section sizes and offsets have
|
||||
been set. If we are generating embedded relocs, it calls a special
|
||||
BFD backend routine to do the work. */
|
||||
|
||||
static void
|
||||
mips_elf${ELFSIZE}_after_allocation (void)
|
||||
{
|
||||
/* Call the standard elf routine. */
|
||||
after_allocation_default ();
|
||||
|
||||
#ifdef SUPPORT_EMBEDDED_RELOCS
|
||||
if (command_line.embedded_relocs && (! link_info.relocatable))
|
||||
{
|
||||
bfd *abfd;
|
||||
|
||||
for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next)
|
||||
{
|
||||
asection *datasec, *relsec;
|
||||
char *errmsg;
|
||||
|
||||
datasec = bfd_get_section_by_name (abfd, ".sdata");
|
||||
|
||||
if (datasec == NULL || datasec->reloc_count == 0)
|
||||
continue;
|
||||
|
||||
relsec = bfd_get_section_by_name (abfd, ".rel.sdata");
|
||||
ASSERT (relsec != NULL);
|
||||
|
||||
if (! bfd_mips_elf${ELFSIZE}_create_embedded_relocs (abfd,
|
||||
&link_info,
|
||||
datasec,
|
||||
relsec,
|
||||
&errmsg))
|
||||
{
|
||||
if (errmsg == NULL)
|
||||
einfo ("%B%X: can not create runtime reloc information: %E\n",
|
||||
abfd);
|
||||
else
|
||||
einfo ("%X%B: can not create runtime reloc information: %s\n",
|
||||
abfd, errmsg);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* SUPPORT_EMBEDDED_RELOCS */
|
||||
}
|
||||
|
||||
EOF
|
||||
|
||||
# We have our own after_open and after_allocation functions, but they call
|
||||
# the standard routines, so give them a different name.
|
||||
LDEMUL_AFTER_OPEN=mips_elf${ELFSIZE}_after_open
|
||||
LDEMUL_AFTER_ALLOCATION=mips_elf${ELFSIZE}_after_allocation
|
||||
72
contrib/binutils/ld/scripttempl/mips.sc
Normal file
72
contrib/binutils/ld/scripttempl/mips.sc
Normal file
@ -0,0 +1,72 @@
|
||||
# Linker script for MIPS systems.
|
||||
# Ian Lance Taylor <ian@cygnus.com>.
|
||||
# These variables may be overridden by the emulation file. The
|
||||
# defaults are appropriate for a DECstation running Ultrix.
|
||||
test -z "$ENTRY" && ENTRY=__start
|
||||
|
||||
if [ -z "$EMBEDDED" ]; then
|
||||
test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x400000 + SIZEOF_HEADERS"
|
||||
else
|
||||
test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x400000"
|
||||
fi
|
||||
if test "x$LD_FLAG" = "xn" -o "x$LD_FLAG" = "xN"; then
|
||||
DATA_ADDR=.
|
||||
else
|
||||
test -z "$DATA_ADDR" && DATA_ADDR=0x10000000
|
||||
fi
|
||||
cat <<EOF
|
||||
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
|
||||
"${LITTLE_OUTPUT_FORMAT}")
|
||||
${LIB_SEARCH_DIRS}
|
||||
|
||||
ENTRY(${ENTRY})
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
${RELOCATING+. = ${TEXT_START_ADDR};}
|
||||
.text : {
|
||||
${RELOCATING+ _ftext = . };
|
||||
*(.init)
|
||||
${RELOCATING+ eprol = .};
|
||||
*(.text)
|
||||
${RELOCATING+PROVIDE (__runtime_reloc_start = .);}
|
||||
*(.rel.sdata)
|
||||
${RELOCATING+PROVIDE (__runtime_reloc_stop = .);}
|
||||
*(.fini)
|
||||
${RELOCATING+ etext = .};
|
||||
${RELOCATING+ _etext = .};
|
||||
}
|
||||
${RELOCATING+. = ${DATA_ADDR};}
|
||||
.rdata : {
|
||||
*(.rdata)
|
||||
}
|
||||
${RELOCATING+ _fdata = ALIGN(16);}
|
||||
.data : {
|
||||
*(.data)
|
||||
${CONSTRUCTING+CONSTRUCTORS}
|
||||
}
|
||||
${RELOCATING+ _gp = ALIGN(16) + 0x8000;}
|
||||
.lit8 : {
|
||||
*(.lit8)
|
||||
}
|
||||
.lit4 : {
|
||||
*(.lit4)
|
||||
}
|
||||
.sdata : {
|
||||
*(.sdata)
|
||||
}
|
||||
${RELOCATING+ edata = .;}
|
||||
${RELOCATING+ _edata = .;}
|
||||
${RELOCATING+ _fbss = .;}
|
||||
.sbss : {
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
}
|
||||
.bss : {
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
${RELOCATING+ end = .;}
|
||||
${RELOCATING+ _end = .;}
|
||||
}
|
||||
EOF
|
||||
30
contrib/binutils/ld/scripttempl/mipsbsd.sc
Normal file
30
contrib/binutils/ld/scripttempl/mipsbsd.sc
Normal file
@ -0,0 +1,30 @@
|
||||
cat <<EOF
|
||||
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
|
||||
"${LITTLE_OUTPUT_FORMAT}")
|
||||
OUTPUT_ARCH(${ARCH})
|
||||
|
||||
${RELOCATING+${LIB_SEARCH_DIRS}}
|
||||
SECTIONS
|
||||
{
|
||||
${RELOCATING+. = ${TEXT_START_ADDR};}
|
||||
.text :
|
||||
{
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
*(.text)
|
||||
${RELOCATING+etext = ${DATA_ALIGNMENT};}
|
||||
}
|
||||
${RELOCATING+. = ${DATA_ALIGNMENT};}
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
${CONSTRUCTING+CONSTRUCTORS}
|
||||
${RELOCATING+edata = .;}
|
||||
}
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
${RELOCATING+end = . };
|
||||
}
|
||||
}
|
||||
EOF
|
||||
1835
contrib/binutils/opcodes/mips-dis.c
Normal file
1835
contrib/binutils/opcodes/mips-dis.c
Normal file
File diff suppressed because it is too large
Load Diff
1218
contrib/binutils/opcodes/mips-opc.c
Normal file
1218
contrib/binutils/opcodes/mips-opc.c
Normal file
File diff suppressed because it is too large
Load Diff
227
contrib/binutils/opcodes/mips16-opc.c
Normal file
227
contrib/binutils/opcodes/mips16-opc.c
Normal file
@ -0,0 +1,227 @@
|
||||
/* mips16-opc.c. Mips16 opcode table.
|
||||
Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
|
||||
Contributed by Ian Lance Taylor, Cygnus Support
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
1, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
02111-1307, USA. */
|
||||
|
||||
#include <stdio.h>
|
||||
#include "sysdep.h"
|
||||
#include "opcode/mips.h"
|
||||
|
||||
/* This is the opcodes table for the mips16 processor. The format of
|
||||
this table is intentionally identical to the one in mips-opc.c.
|
||||
However, the special letters that appear in the argument string are
|
||||
different, and the table uses some different flags. */
|
||||
|
||||
/* Use some short hand macros to keep down the length of the lines in
|
||||
the opcodes table. */
|
||||
|
||||
#define UBD INSN_UNCOND_BRANCH_DELAY
|
||||
#define BR MIPS16_INSN_BRANCH
|
||||
|
||||
#define WR_x MIPS16_INSN_WRITE_X
|
||||
#define WR_y MIPS16_INSN_WRITE_Y
|
||||
#define WR_z MIPS16_INSN_WRITE_Z
|
||||
#define WR_T MIPS16_INSN_WRITE_T
|
||||
#define WR_SP MIPS16_INSN_WRITE_SP
|
||||
#define WR_31 MIPS16_INSN_WRITE_31
|
||||
#define WR_Y MIPS16_INSN_WRITE_GPR_Y
|
||||
|
||||
#define RD_x MIPS16_INSN_READ_X
|
||||
#define RD_y MIPS16_INSN_READ_Y
|
||||
#define RD_Z MIPS16_INSN_READ_Z
|
||||
#define RD_T MIPS16_INSN_READ_T
|
||||
#define RD_SP MIPS16_INSN_READ_SP
|
||||
#define RD_31 MIPS16_INSN_READ_31
|
||||
#define RD_PC MIPS16_INSN_READ_PC
|
||||
#define RD_X MIPS16_INSN_READ_GPR_X
|
||||
|
||||
#define WR_HI INSN_WRITE_HI
|
||||
#define WR_LO INSN_WRITE_LO
|
||||
#define RD_HI INSN_READ_HI
|
||||
#define RD_LO INSN_READ_LO
|
||||
|
||||
#define TRAP INSN_TRAP
|
||||
|
||||
#define I3 INSN_ISA3
|
||||
|
||||
#define T3 INSN_3900
|
||||
|
||||
const struct mips_opcode mips16_opcodes[] =
|
||||
{
|
||||
{"nop", "", 0x6500, 0xffff, RD_Z, 0 }, /* move $0,$Z */
|
||||
{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0 },
|
||||
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0 },
|
||||
{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 },
|
||||
{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 },
|
||||
{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
|
||||
{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
|
||||
{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 },
|
||||
{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 },
|
||||
{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0 },
|
||||
{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 },
|
||||
{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 },
|
||||
{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
|
||||
{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 },
|
||||
{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 },
|
||||
{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 },
|
||||
{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0 },
|
||||
{"b", "q", 0x1000, 0xf800, BR, 0 },
|
||||
{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0 },
|
||||
{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0 },
|
||||
{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0 },
|
||||
{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0 },
|
||||
{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0 },
|
||||
{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0 },
|
||||
{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0 },
|
||||
{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0 },
|
||||
{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0 },
|
||||
{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0 },
|
||||
{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0 },
|
||||
{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0 },
|
||||
{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0 },
|
||||
{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0 },
|
||||
{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0 },
|
||||
{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0 },
|
||||
{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0 },
|
||||
{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0 },
|
||||
{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0 },
|
||||
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0 },
|
||||
{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0 },
|
||||
{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0 },
|
||||
{"break", "6", 0xe805, 0xf81f, TRAP, 0 },
|
||||
{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0 },
|
||||
{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0 },
|
||||
{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 },
|
||||
{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0 },
|
||||
{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 },
|
||||
{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
|
||||
{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 },
|
||||
{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 },
|
||||
{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
|
||||
{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
|
||||
{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
|
||||
{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 },
|
||||
{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 },
|
||||
{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 },
|
||||
{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 },
|
||||
{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
|
||||
{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 },
|
||||
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 },
|
||||
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 },
|
||||
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0 },
|
||||
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0 },
|
||||
{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0 },
|
||||
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0 },
|
||||
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 },
|
||||
{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0 },
|
||||
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 },
|
||||
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0 },
|
||||
{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 },
|
||||
{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 },
|
||||
{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 },
|
||||
{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 },
|
||||
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 },
|
||||
{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0 },
|
||||
{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0 },
|
||||
{"exit", "L", 0xed09, 0xff1f, TRAP, 0 },
|
||||
{"exit", "L", 0xee09, 0xff1f, TRAP, 0 },
|
||||
{"exit", "L", 0xef09, 0xff1f, TRAP, 0 },
|
||||
{"entry", "l", 0xe809, 0xf81f, TRAP, 0 },
|
||||
{"extend", "e", 0xf000, 0xf800, 0, 0 },
|
||||
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
|
||||
{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
|
||||
{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
|
||||
{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 },
|
||||
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0 },
|
||||
{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0 },
|
||||
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 },
|
||||
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0 },
|
||||
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 },
|
||||
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0 },
|
||||
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0 },
|
||||
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0 },
|
||||
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 },
|
||||
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 },
|
||||
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 },
|
||||
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 },
|
||||
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0 },
|
||||
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0 },
|
||||
{"li", "x,U", 0x6800, 0xf800, WR_x, 0 },
|
||||
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0 },
|
||||
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0 },
|
||||
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0 },
|
||||
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0 },
|
||||
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 },
|
||||
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0 },
|
||||
{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0 },
|
||||
{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0 },
|
||||
{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0 },
|
||||
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0 },
|
||||
{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0 },
|
||||
{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0 },
|
||||
{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0 },
|
||||
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0 },
|
||||
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 },
|
||||
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0 },
|
||||
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0 },
|
||||
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 },
|
||||
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 },
|
||||
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0 },
|
||||
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0 },
|
||||
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0 },
|
||||
{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 },
|
||||
{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0 },
|
||||
{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 },
|
||||
{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 },
|
||||
{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0 },
|
||||
{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 },
|
||||
{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0 },
|
||||
{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0 },
|
||||
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 },
|
||||
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0 },
|
||||
{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0 },
|
||||
{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0 },
|
||||
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0 },
|
||||
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0 },
|
||||
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0 },
|
||||
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0 },
|
||||
};
|
||||
|
||||
const int bfd_mips16_num_opcodes =
|
||||
((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
|
||||
Loading…
Reference in New Issue
Block a user