From b865714d953167a48defc516c86fa762be0c1bd9 Mon Sep 17 00:00:00 2001 From: Kristof Provost Date: Wed, 1 Jul 2020 19:15:43 +0000 Subject: [PATCH] riscv pmap: zero reserved pte bits in ppn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The top 10 bits of a pte are reserved by specification[1] and are not part of the PPN. [1] 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified', '4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is shown in Figure 4.18. ... Bits 63–54 are reserved for future use and must be zeroed by software for forward compatibility." Submitted by: Nathaniel Filardo Reviewed by: kp, mhorne Differential Revision: https://reviews.freebsd.org/D25523 --- sys/riscv/include/pte.h | 3 +++ sys/riscv/riscv/pmap.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/sys/riscv/include/pte.h b/sys/riscv/include/pte.h index a88566d890ae..965faa7eea9e 100644 --- a/sys/riscv/include/pte.h +++ b/sys/riscv/include/pte.h @@ -83,6 +83,9 @@ typedef uint64_t pn_t; /* page number */ #define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \ PTE_SW_MANAGED | PTE_SW_WIRED) +/* Bits 63 - 54 are reserved for future use. */ +#define PTE_HI_MASK 0xFFC0000000000000ULL + #define PTE_PPN0_S 10 #define PTE_PPN1_S 19 #define PTE_PPN2_S 28 diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c index 33902bb1e85f..725bf647b7a1 100644 --- a/sys/riscv/riscv/pmap.c +++ b/sys/riscv/riscv/pmap.c @@ -339,7 +339,8 @@ pagezero(void *p) #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK) #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK) -#define PTE_TO_PHYS(pte) ((pte >> PTE_PPN0_S) * PAGE_SIZE) +#define PTE_TO_PHYS(pte) \ + ((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE) static __inline pd_entry_t * pmap_l1(pmap_t pmap, vm_offset_t va)