[atheros] [if_arge] Various fixes to avoid TX stalls and bad sized packets
This is stuff I've been running for a couple years. It's inspired by changes I found in the linux ag71xx ethernet driver. * Delay between stopping DMA and checking to see if it's stopped; this gives the hardware time to do its thing. * Non-final frames in the chain need to be a multiple of 4 bytes in size. Ensure this is the case when assembling a TX DMA list. * Add counters for tx/rx underflow and too-short packets. * Log if TX/RX DMA couldn't be stopped when resetting the MAC. * Add some more debugging / logging around TX/RX ring bits. Tested: * AR7240, AR7241 * AR9344 (TL-WDR3600/TL-WDR4300 APs) * AR9331 (Carambola 2)
This commit is contained in:
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134a253edc
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=360865
@ -332,6 +332,11 @@ arge_attach_sysctl(device_t dev)
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"tx_pkts_unaligned_len", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_len,
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0, "number of TX unaligned packets (len)");
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"tx_pkts_unaligned_tooshort", CTLFLAG_RW,
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&sc->stats.tx_pkts_unaligned_tooshort,
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0, "number of TX unaligned packets (mbuf length < 4 bytes)");
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"tx_pkts_nosegs", CTLFLAG_RW, &sc->stats.tx_pkts_nosegs,
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0, "number of TX packets fail with no ring slots avail");
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@ -347,6 +352,13 @@ arge_attach_sysctl(device_t dev)
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"intr_ok", CTLFLAG_RW, &sc->stats.intr_ok,
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0, "number of OK interrupts");
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"tx_underflow", CTLFLAG_RW, &sc->stats.tx_underflow,
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0, "Number of TX underflows");
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"rx_overflow", CTLFLAG_RW, &sc->stats.rx_overflow,
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0, "Number of RX overflows");
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#ifdef ARGE_DEBUG
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
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CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
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@ -1365,15 +1377,24 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
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static void
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arge_reset_dma(struct arge_softc *sc)
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{
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uint32_t val;
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ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
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ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
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ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
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/* Give hardware a chance to finish */
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DELAY(1000);
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ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
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ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
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ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: RX_STATUS=%08x, TX_STATUS=%08x\n",
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__func__,
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ARGE_READ(sc, AR71XX_DMA_RX_STATUS),
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ARGE_READ(sc, AR71XX_DMA_TX_STATUS));
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/* Clear all possible RX interrupts */
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while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
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ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
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@ -1397,6 +1418,24 @@ arge_reset_dma(struct arge_softc *sc)
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* flushed to RAM before underlying buffers are freed.
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*/
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arge_flush_ddr(sc);
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/* Check if we cleared RX status */
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val = ARGE_READ(sc, AR71XX_DMA_RX_STATUS);
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if (val != 0) {
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device_printf(sc->arge_dev,
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"%s: unable to clear DMA_RX_STATUS: %08x\n",
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__func__, val);
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}
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/* Check if we cleared TX status */
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val = ARGE_READ(sc, AR71XX_DMA_TX_STATUS);
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/* Mask out reserved bits */
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val = val & 0x00ffffff;
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if (val != 0) {
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device_printf(sc->arge_dev,
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"%s: unable to clear DMA_TX_STATUS: %08x\n",
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__func__, val);
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}
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}
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static void
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@ -1417,9 +1456,13 @@ arge_init_locked(struct arge_softc *sc)
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ARGE_LOCK_ASSERT(sc);
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ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: called\n", __func__);
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if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
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return;
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ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: init'ing\n", __func__);
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/* Init circular RX list. */
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if (arge_rx_ring_init(sc) != 0) {
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device_printf(sc->arge_dev,
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@ -1431,6 +1474,7 @@ arge_init_locked(struct arge_softc *sc)
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/* Init tx descriptors. */
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arge_tx_ring_init(sc);
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/* Restart DMA */
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arge_reset_dma(sc);
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if (sc->arge_miibus) {
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@ -1452,6 +1496,11 @@ arge_init_locked(struct arge_softc *sc)
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arge_update_link_locked(sc);
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}
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ARGEDEBUG(sc, ARGE_DBG_RESET, "%s: desc ring; TX=0x%x, RX=0x%x\n",
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__func__,
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ARGE_TX_RING_ADDR(sc, 0),
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ARGE_RX_RING_ADDR(sc, 0));
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ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
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ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
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@ -1495,6 +1544,15 @@ arge_mbuf_chain_is_tx_aligned(struct arge_softc *sc, struct mbuf *m0)
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sc->stats.tx_pkts_unaligned_len++;
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return 0;
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}
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/*
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* All chips have this requirement for length being greater
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* than 4.
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*/
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if ((m->m_next != NULL) && ((m->m_len < 4))) {
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sc->stats.tx_pkts_unaligned_tooshort++;
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return 0;
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}
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}
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return 1;
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}
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@ -1582,6 +1640,11 @@ arge_encap(struct arge_softc *sc, struct mbuf **m_head)
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tmp |= ARGE_DESC_EMPTY;
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desc->packet_ctrl = tmp;
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ARGEDEBUG(sc, ARGE_DBG_TX, " [%d / %d] addr=0x%x, len=%d\n",
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i,
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prod,
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(uint32_t) txsegs[i].ds_addr, (int) txsegs[i].ds_len);
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/* XXX Note: only relevant for older MACs; but check length! */
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if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
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(txsegs[i].ds_addr & 3))
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@ -2606,7 +2669,7 @@ arge_intr(void *arg)
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}
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/*
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* If we've finished TXing and there's space for more packets
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* If we've finished RX /or/ TX and there's space for more packets
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* to be queued for TX, do so. Otherwise we may end up in a
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* situation where the interface send queue was filled
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* whilst the hardware queue was full, then the hardware
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@ -2620,8 +2683,7 @@ arge_intr(void *arg)
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* after a TX underrun, then having the hardware queue added
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* to below.
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*/
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if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
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(ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
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if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
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if (!IFQ_IS_EMPTY(&ifp->if_snd))
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arge_start_locked(ifp);
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}
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@ -206,6 +206,7 @@ struct arge_softc {
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uint32_t tx_pkts_unaligned;
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uint32_t tx_pkts_unaligned_start;
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uint32_t tx_pkts_unaligned_len;
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uint32_t tx_pkts_unaligned_tooshort;
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uint32_t tx_pkts_nosegs;
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uint32_t tx_pkts_aligned;
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uint32_t rx_overflow;
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