Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives). RISC-V page table entries support A (accessed) and D (dirty) bits. The spec makes hardware support for these bits optional. Implementations that do not manage these bits in hardware raise page faults for accesses to a valid page without A set and writes to a writable page without D set. Check for these types of faults when handling a page fault and fixup the PTE without calling vm_fault if they occur. Reviewed by: jhb, markj Approved by: re (gjb) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D17424
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=339423
@ -153,6 +153,8 @@ bool pmap_get_tables(pmap_t, vm_offset_t, pd_entry_t **, pd_entry_t **,
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#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
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int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t);
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#endif /* _KERNEL */
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#endif /* !LOCORE */
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@ -1,6 +1,6 @@
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/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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@ -65,7 +65,7 @@ typedef uint64_t pn_t; /* page number */
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#define Ln_ENTRIES (1 << 9)
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#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
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/* Bits 9:7 are reserved for software */
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/* Bits 9:8 are reserved for software */
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#define PTE_SW_MANAGED (1 << 9)
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#define PTE_SW_WIRED (1 << 8)
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#define PTE_D (1 << 7) /* Dirty */
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@ -78,6 +78,7 @@ typedef uint64_t pn_t; /* page number */
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#define PTE_V (1 << 0) /* Valid */
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#define PTE_RWX (PTE_R | PTE_W | PTE_X)
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#define PTE_RX (PTE_R | PTE_X)
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#define PTE_KERN (PTE_V | PTE_RWX | PTE_A | PTE_D)
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#define PTE_PPN0_S 10
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#define PTE_PPN1_S 19
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@ -94,7 +94,7 @@ _start:
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add t3, t4, t2
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li t5, 0
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2:
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li t0, (PTE_V | PTE_RWX | PTE_D)
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li t0, (PTE_KERN)
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slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */
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or t5, t0, t2
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sd t5, (s1) /* Store PTE entry to position */
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@ -126,7 +126,7 @@ _start:
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mv s2, s11
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srli s2, s2, PAGE_SHIFT
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li t0, (PTE_V | PTE_RWX | PTE_D)
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li t0, (PTE_KERN)
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slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */
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or t0, t0, t2
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@ -15,7 +15,7 @@
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* All rights reserved.
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* Copyright (c) 2014 The FreeBSD Foundation
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* All rights reserved.
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* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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@ -487,7 +487,7 @@ pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
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/* superpages */
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pn = (pa / PAGE_SIZE);
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entry = (PTE_V | PTE_RWX);
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entry = PTE_KERN;
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(&l1[l1_slot], entry);
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}
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@ -965,7 +965,7 @@ pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
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KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va));
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pn = (pa / PAGE_SIZE);
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entry = (PTE_V | PTE_RWX);
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entry = PTE_KERN;
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(l3, entry);
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@ -1063,7 +1063,7 @@ pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
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pn = (pa / PAGE_SIZE);
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l3 = pmap_l3(kernel_pmap, va);
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entry = (PTE_V | PTE_RWX);
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entry = PTE_KERN;
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entry |= (pn << PTE_PPN0_S);
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pmap_load_store(l3, entry);
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@ -1465,7 +1465,8 @@ pmap_growkernel(vm_offset_t addr)
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continue; /* try again */
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}
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l2 = pmap_l1_to_l2(l1, kernel_vm_end);
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if ((pmap_load(l2) & PTE_A) != 0) {
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if ((pmap_load(l2) & PTE_V) != 0 &&
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(pmap_load(l2) & PTE_RWX) == 0) {
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kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
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if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
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kernel_vm_end = vm_map_max(kernel_map);
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@ -2008,6 +2009,41 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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PMAP_UNLOCK(pmap);
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}
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int
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pmap_fault_fixup(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
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{
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pt_entry_t orig_l3;
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pt_entry_t new_l3;
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pt_entry_t *l3;
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l3 = pmap_l3(pmap, va);
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if (l3 == NULL)
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return (0);
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orig_l3 = pmap_load(l3);
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if ((orig_l3 & PTE_V) == 0 ||
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((prot & VM_PROT_WRITE) != 0 && (orig_l3 & PTE_W) == 0) ||
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((prot & VM_PROT_READ) != 0 && (orig_l3 & PTE_R) == 0))
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return (0);
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new_l3 = orig_l3 | PTE_A;
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if ((prot & VM_PROT_WRITE) != 0)
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new_l3 |= PTE_D;
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if (orig_l3 != new_l3) {
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pmap_load_store(l3, new_l3);
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pmap_invalidate_page(pmap, va);
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return (1);
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}
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/*
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* XXX: This case should never happen since it means
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* the PTE shouldn't have resulted in a fault.
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*/
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return (0);
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}
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/*
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* Insert the given physical page (p) at
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* the specified virtual address (v) in the
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@ -2415,8 +2451,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
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pa = VM_PAGE_TO_PHYS(m);
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pn = (pa / PAGE_SIZE);
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/* RISCVTODO: check permissions */
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entry = (PTE_V | PTE_RWX);
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entry = (PTE_V | PTE_R | PTE_X);
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entry |= (pn << PTE_PPN0_S);
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/*
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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@ -212,6 +212,9 @@ data_abort(struct trapframe *frame, int lower)
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ftype = (VM_PROT_READ);
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}
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if (pmap_fault_fixup(map->pmap, va, ftype))
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goto done;
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if (map != kernel_map) {
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/*
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* Keep swapout from messing with us during this
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@ -256,6 +259,7 @@ data_abort(struct trapframe *frame, int lower)
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}
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}
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done:
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if (lower)
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userret(td, frame);
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}
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