Move to a SMMU specific struct for the smmu pmap
This is not managed through the VM subsystem so only needs to hold the data the SMMU driver needs. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D39184
This commit is contained in:
Andrew Turner
parent
49ee1a7ef0
commit
b97e94d91e
@ -62,6 +62,11 @@ __FBSDID("$FreeBSD$");
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#define IOMMU_PAGE_SIZE 4096
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#define SMMU_PMAP_LOCK(pmap) mtx_lock(&(pmap)->sp_mtx)
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#define SMMU_PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->sp_mtx)
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#define SMMU_PMAP_LOCK_ASSERT(pmap, type) \
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mtx_assert(&(pmap)->sp_mtx, (type))
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#define NL0PG (IOMMU_PAGE_SIZE/(sizeof (pd_entry_t)))
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#define NL1PG (IOMMU_PAGE_SIZE/(sizeof (pd_entry_t)))
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#define NL2PG (IOMMU_PAGE_SIZE/(sizeof (pd_entry_t)))
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@ -80,9 +85,9 @@ __FBSDID("$FreeBSD$");
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#define smmu_l2_index(va) (((va) >> IOMMU_L2_SHIFT) & IOMMU_Ln_ADDR_MASK)
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#define smmu_l3_index(va) (((va) >> IOMMU_L3_SHIFT) & IOMMU_Ln_ADDR_MASK)
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static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex);
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static void _smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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struct spglist *free);
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static vm_page_t _pmap_alloc_l3(struct smmu_pmap *pmap, vm_pindex_t ptepindex);
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static void _smmu_pmap_unwire_l3(struct smmu_pmap *pmap, vm_offset_t va,
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vm_page_t m, struct spglist *free);
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/*
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* These load the old table data and store the new value.
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@ -98,10 +103,10 @@ static void _smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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/********************/
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static __inline pd_entry_t *
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smmu_pmap_l0(pmap_t pmap, vm_offset_t va)
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smmu_pmap_l0(struct smmu_pmap *pmap, vm_offset_t va)
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{
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return (&pmap->pm_l0[smmu_l0_index(va)]);
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return (&pmap->sp_l0[smmu_l0_index(va)]);
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}
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static __inline pd_entry_t *
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@ -114,7 +119,7 @@ smmu_pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
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}
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static __inline pd_entry_t *
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smmu_pmap_l1(pmap_t pmap, vm_offset_t va)
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smmu_pmap_l1(struct smmu_pmap *pmap, vm_offset_t va)
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{
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pd_entry_t *l0;
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@ -145,7 +150,7 @@ smmu_pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va)
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}
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static __inline pd_entry_t *
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smmu_pmap_l2(pmap_t pmap, vm_offset_t va)
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smmu_pmap_l2(struct smmu_pmap *pmap, vm_offset_t va)
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{
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pd_entry_t *l1;
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@ -181,7 +186,7 @@ smmu_pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va)
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* The next level may or may not point to a valid page or block.
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*/
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static __inline pd_entry_t *
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smmu_pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
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smmu_pmap_pde(struct smmu_pmap *pmap, vm_offset_t va, int *level)
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{
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pd_entry_t *l0, *l1, *l2, desc;
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@ -216,7 +221,7 @@ smmu_pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
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* the first invalid level.
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*/
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static __inline pt_entry_t *
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smmu_pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
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smmu_pmap_pte(struct smmu_pmap *pmap, vm_offset_t va, int *level)
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{
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pd_entry_t *l1, *l2, desc;
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pt_entry_t *l3;
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@ -266,24 +271,36 @@ smmu_pmap_l3_valid(pt_entry_t l3)
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CTASSERT(IOMMU_L1_BLOCK == IOMMU_L2_BLOCK);
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#ifdef INVARIANTS
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static __inline void
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smmu_pmap_resident_count_inc(pmap_t pmap, int count)
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smmu_pmap_resident_count_inc(struct smmu_pmap *pmap, int count)
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{
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PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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pmap->pm_stats.resident_count += count;
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SMMU_PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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pmap->sp_resident_count += count;
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}
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static __inline void
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smmu_pmap_resident_count_dec(pmap_t pmap, int count)
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smmu_pmap_resident_count_dec(struct smmu_pmap *pmap, int count)
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{
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PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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KASSERT(pmap->pm_stats.resident_count >= count,
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SMMU_PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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KASSERT(pmap->sp_resident_count >= count,
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("pmap %p resident count underflow %ld %d", pmap,
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pmap->pm_stats.resident_count, count));
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pmap->pm_stats.resident_count -= count;
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pmap->sp_resident_count, count));
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pmap->sp_resident_count -= count;
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}
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#else
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static __inline void
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smmu_pmap_resident_count_inc(struct smmu_pmap *pmap, int count)
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{
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}
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static __inline void
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smmu_pmap_resident_count_dec(struct smmu_pmap *pmap, int count)
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{
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}
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#endif
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/***************************************************
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* Page table page management routines.....
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@ -316,7 +333,7 @@ smmu_pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
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* page table page was unmapped and FALSE otherwise.
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*/
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static inline boolean_t
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smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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smmu_pmap_unwire_l3(struct smmu_pmap *pmap, vm_offset_t va, vm_page_t m,
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struct spglist *free)
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{
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@ -329,11 +346,11 @@ smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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}
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static void
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_smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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_smmu_pmap_unwire_l3(struct smmu_pmap *pmap, vm_offset_t va, vm_page_t m,
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struct spglist *free)
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{
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PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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SMMU_PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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/*
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* unmap the page table page
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*/
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@ -385,7 +402,7 @@ _smmu_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
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}
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int
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smmu_pmap_pinit(pmap_t pmap)
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smmu_pmap_pinit(struct smmu_pmap *pmap)
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{
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vm_page_t m;
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@ -394,14 +411,11 @@ smmu_pmap_pinit(pmap_t pmap)
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*/
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m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED |
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VM_ALLOC_ZERO);
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pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m);
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pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr);
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pmap->sp_l0_paddr = VM_PAGE_TO_PHYS(m);
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pmap->sp_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->sp_l0_paddr);
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vm_radix_init(&pmap->pm_root);
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bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
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pmap->pm_levels = 4;
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pmap->pm_ttbr = VM_PAGE_TO_PHYS(m);
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pmap->sp_resident_count = 0;
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mtx_init(&pmap->sp_mtx, "smmu pmap", NULL, MTX_DEF);
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return (1);
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}
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@ -418,11 +432,11 @@ smmu_pmap_pinit(pmap_t pmap)
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* race conditions.
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*/
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static vm_page_t
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_pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex)
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_pmap_alloc_l3(struct smmu_pmap *pmap, vm_pindex_t ptepindex)
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{
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vm_page_t m, l1pg, l2pg;
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PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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SMMU_PMAP_LOCK_ASSERT(pmap, MA_OWNED);
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/*
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* Allocate a page table page.
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@ -456,7 +470,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex)
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vm_pindex_t l0index;
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l0index = ptepindex - (NUL2E + NUL1E);
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l0 = &pmap->pm_l0[l0index];
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l0 = &pmap->sp_l0[l0index];
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smmu_pmap_store(l0, VM_PAGE_TO_PHYS(m) | IOMMU_L0_TABLE);
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} else if (ptepindex >= NUL2E) {
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vm_pindex_t l0index, l1index;
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@ -466,7 +480,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex)
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l1index = ptepindex - NUL2E;
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l0index = l1index >> IOMMU_L0_ENTRIES_SHIFT;
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l0 = &pmap->pm_l0[l0index];
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l0 = &pmap->sp_l0[l0index];
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tl0 = smmu_pmap_load(l0);
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if (tl0 == 0) {
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/* recurse for allocating page dir */
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@ -492,7 +506,7 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex)
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l1index = ptepindex >> Ln_ENTRIES_SHIFT;
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l0index = l1index >> IOMMU_L0_ENTRIES_SHIFT;
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l0 = &pmap->pm_l0[l0index];
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l0 = &pmap->sp_l0[l0index];
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tl0 = smmu_pmap_load(l0);
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if (tl0 == 0) {
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/* recurse for allocating page dir */
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@ -542,19 +556,18 @@ _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex)
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* Should only be called if the map contains no valid mappings.
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*/
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void
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smmu_pmap_release(pmap_t pmap)
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smmu_pmap_release(struct smmu_pmap *pmap)
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{
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vm_page_t m;
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KASSERT(pmap->pm_stats.resident_count == 0,
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KASSERT(pmap->sp_resident_count == 0,
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("pmap_release: pmap resident count %ld != 0",
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pmap->pm_stats.resident_count));
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KASSERT(vm_radix_is_empty(&pmap->pm_root),
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("pmap_release: pmap has reserved page table page(s)"));
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pmap->sp_resident_count));
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m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr);
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m = PHYS_TO_VM_PAGE(pmap->sp_l0_paddr);
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vm_page_unwire_noq(m);
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vm_page_free_zero(m);
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mtx_destroy(&pmap->sp_mtx);
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}
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/***************************************************
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@ -565,7 +578,7 @@ smmu_pmap_release(pmap_t pmap)
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* Add a single Mali GPU entry. This function does not sleep.
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*/
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int
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pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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pmap_gpu_enter(struct smmu_pmap *pmap, vm_offset_t va, vm_paddr_t pa,
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vm_prot_t prot, u_int flags)
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{
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pd_entry_t *pde;
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@ -578,7 +591,6 @@ pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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int lvl;
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int rv;
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KASSERT(pmap != kernel_pmap, ("kernel pmap used for GPU"));
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KASSERT(va < VM_MAXUSER_ADDRESS, ("wrong address space"));
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KASSERT((va & PAGE_MASK) == 0, ("va is misaligned"));
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KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
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@ -594,7 +606,7 @@ pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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CTR2(KTR_PMAP, "pmap_gpu_enter: %.16lx -> %.16lx", va, pa);
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PMAP_LOCK(pmap);
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SMMU_PMAP_LOCK(pmap);
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/*
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* In the case that a page table page is not
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@ -639,7 +651,7 @@ pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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rv = KERN_SUCCESS;
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out:
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PMAP_UNLOCK(pmap);
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SMMU_PMAP_UNLOCK(pmap);
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return (rv);
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}
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@ -648,7 +660,7 @@ pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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* Remove a single Mali GPU entry.
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*/
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int
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pmap_gpu_remove(pmap_t pmap, vm_offset_t va)
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pmap_gpu_remove(struct smmu_pmap *pmap, vm_offset_t va)
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{
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pd_entry_t *pde;
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pt_entry_t *pte;
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@ -656,9 +668,8 @@ pmap_gpu_remove(pmap_t pmap, vm_offset_t va)
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int rc;
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KASSERT((va & PAGE_MASK) == 0, ("va is misaligned"));
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KASSERT(pmap != kernel_pmap, ("kernel pmap used for GPU"));
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PMAP_LOCK(pmap);
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SMMU_PMAP_LOCK(pmap);
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pde = smmu_pmap_pde(pmap, va, &lvl);
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if (pde == NULL || lvl != 2) {
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@ -674,7 +685,7 @@ pmap_gpu_remove(pmap_t pmap, vm_offset_t va)
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rc = KERN_SUCCESS;
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out:
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PMAP_UNLOCK(pmap);
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SMMU_PMAP_UNLOCK(pmap);
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return (rc);
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}
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@ -683,7 +694,7 @@ pmap_gpu_remove(pmap_t pmap, vm_offset_t va)
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* Add a single SMMU entry. This function does not sleep.
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*/
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int
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smmu_pmap_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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smmu_pmap_enter(struct smmu_pmap *pmap, vm_offset_t va, vm_paddr_t pa,
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vm_prot_t prot, u_int flags)
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{
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pd_entry_t *pde;
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@ -707,7 +718,7 @@ smmu_pmap_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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CTR2(KTR_PMAP, "pmap_senter: %.16lx -> %.16lx", va, pa);
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PMAP_LOCK(pmap);
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SMMU_PMAP_LOCK(pmap);
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/*
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* In the case that a page table page is not
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@ -737,7 +748,7 @@ smmu_pmap_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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rv = KERN_SUCCESS;
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out:
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PMAP_UNLOCK(pmap);
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SMMU_PMAP_UNLOCK(pmap);
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return (rv);
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}
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@ -746,13 +757,13 @@ smmu_pmap_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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* Remove a single SMMU entry.
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*/
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int
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smmu_pmap_remove(pmap_t pmap, vm_offset_t va)
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smmu_pmap_remove(struct smmu_pmap *pmap, vm_offset_t va)
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{
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pt_entry_t *pte;
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int lvl;
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int rc;
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PMAP_LOCK(pmap);
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SMMU_PMAP_LOCK(pmap);
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pte = smmu_pmap_pte(pmap, va, &lvl);
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KASSERT(lvl == 3,
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@ -765,7 +776,7 @@ smmu_pmap_remove(pmap_t pmap, vm_offset_t va)
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} else
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rc = KERN_FAILURE;
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PMAP_UNLOCK(pmap);
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SMMU_PMAP_UNLOCK(pmap);
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return (rc);
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}
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@ -776,7 +787,7 @@ smmu_pmap_remove(pmap_t pmap, vm_offset_t va)
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* this function panics.
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*/
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void
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smmu_pmap_remove_pages(pmap_t pmap)
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smmu_pmap_remove_pages(struct smmu_pmap *pmap)
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{
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pd_entry_t l0e, *l1, l1e, *l2, l2e;
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pt_entry_t *l3, l3e;
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@ -787,11 +798,11 @@ smmu_pmap_remove_pages(pmap_t pmap)
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vm_paddr_t pa1;
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int i, j, k, l;
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PMAP_LOCK(pmap);
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SMMU_PMAP_LOCK(pmap);
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for (sva = VM_MINUSER_ADDRESS, i = smmu_l0_index(sva);
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(i < Ln_ENTRIES && sva < VM_MAXUSER_ADDRESS); i++) {
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l0e = pmap->pm_l0[i];
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l0e = pmap->sp_l0[i];
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if ((l0e & ATTR_DESCR_VALID) == 0) {
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sva += IOMMU_L0_SIZE;
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continue;
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@ -848,11 +859,11 @@ smmu_pmap_remove_pages(pmap_t pmap)
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smmu_pmap_resident_count_dec(pmap, 1);
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vm_page_free(m0);
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smmu_pmap_clear(&pmap->pm_l0[i]);
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smmu_pmap_clear(&pmap->sp_l0[i]);
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}
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KASSERT(pmap->pm_stats.resident_count == 0,
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("Invalid resident count %jd", pmap->pm_stats.resident_count));
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KASSERT(pmap->sp_resident_count == 0,
|
||||
("Invalid resident count %jd", pmap->sp_resident_count));
|
||||
|
||||
PMAP_UNLOCK(pmap);
|
||||
SMMU_PMAP_UNLOCK(pmap);
|
||||
}
|
||||
|
||||
@ -33,19 +33,28 @@
|
||||
#ifndef _ARM64_IOMMU_IOMMU_PMAP_H_
|
||||
#define _ARM64_IOMMU_IOMMU_PMAP_H_
|
||||
|
||||
struct smmu_pmap {
|
||||
struct mtx sp_mtx;
|
||||
vm_paddr_t sp_l0_paddr;
|
||||
pd_entry_t *sp_l0;
|
||||
#ifdef INVARIANTS
|
||||
long sp_resident_count;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* System MMU (SMMU). */
|
||||
int smmu_pmap_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, vm_prot_t prot,
|
||||
u_int flags);
|
||||
int smmu_pmap_remove(pmap_t pmap, vm_offset_t va);
|
||||
int smmu_pmap_enter(struct smmu_pmap *pmap, vm_offset_t va, vm_paddr_t pa,
|
||||
vm_prot_t prot, u_int flags);
|
||||
int smmu_pmap_remove(struct smmu_pmap *pmap, vm_offset_t va);
|
||||
|
||||
/* Mali GPU */
|
||||
int pmap_gpu_enter(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
|
||||
int pmap_gpu_enter(struct smmu_pmap *pmap, vm_offset_t va, vm_paddr_t pa,
|
||||
vm_prot_t prot, u_int flags);
|
||||
int pmap_gpu_remove(pmap_t pmap, vm_offset_t va);
|
||||
int pmap_gpu_remove(struct smmu_pmap *pmap, vm_offset_t va);
|
||||
|
||||
/* Common */
|
||||
void smmu_pmap_remove_pages(pmap_t pmap);
|
||||
void smmu_pmap_release(pmap_t pmap);
|
||||
int smmu_pmap_pinit(pmap_t);
|
||||
void smmu_pmap_remove_pages(struct smmu_pmap *pmap);
|
||||
void smmu_pmap_release(struct smmu_pmap *pmap);
|
||||
int smmu_pmap_pinit(struct smmu_pmap *pmap);
|
||||
|
||||
#endif /* !_ARM64_IOMMU_IOMMU_PMAP_H_ */
|
||||
|
||||
@ -840,7 +840,7 @@ smmu_init_cd(struct smmu_softc *sc, struct smmu_domain *domain)
|
||||
uint64_t val;
|
||||
vm_size_t size;
|
||||
struct smmu_cd *cd;
|
||||
pmap_t p;
|
||||
struct smmu_pmap *p;
|
||||
|
||||
size = 1 * (CD_DWORDS << 3);
|
||||
|
||||
@ -875,8 +875,8 @@ smmu_init_cd(struct smmu_softc *sc, struct smmu_domain *domain)
|
||||
val |= ((64 - sc->ias) << CD0_T0SZ_S);
|
||||
val |= CD0_IPS_48BITS;
|
||||
|
||||
paddr = p->pm_l0_paddr & CD1_TTB0_M;
|
||||
KASSERT(paddr == p->pm_l0_paddr, ("bad allocation 1"));
|
||||
paddr = p->sp_l0_paddr & CD1_TTB0_M;
|
||||
KASSERT(paddr == p->sp_l0_paddr, ("bad allocation 1"));
|
||||
|
||||
ptr[1] = paddr;
|
||||
ptr[2] = 0;
|
||||
@ -1729,7 +1729,6 @@ smmu_domain_alloc(device_t dev, struct iommu_unit *iommu)
|
||||
domain->asid = (uint16_t)new_asid;
|
||||
|
||||
smmu_pmap_pinit(&domain->p);
|
||||
PMAP_LOCK_INIT(&domain->p);
|
||||
|
||||
error = smmu_init_cd(sc, domain);
|
||||
if (error) {
|
||||
|
||||
@ -35,6 +35,8 @@
|
||||
#ifndef _ARM64_IOMMU_SMMUVAR_H_
|
||||
#define _ARM64_IOMMU_SMMUVAR_H_
|
||||
|
||||
#include <arm64/iommu/iommu_pmap.h>
|
||||
|
||||
#define SMMU_DEVSTR "ARM System Memory Management Unit"
|
||||
#define SMMU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
||||
#define SMMU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
|
||||
@ -55,7 +57,7 @@ struct smmu_domain {
|
||||
LIST_ENTRY(smmu_domain) next;
|
||||
u_int entries_cnt;
|
||||
struct smmu_cd *cd;
|
||||
struct pmap p;
|
||||
struct smmu_pmap p;
|
||||
uint16_t asid;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user