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Import device-tree files from Linux 6.0

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Sponsored by:   Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot 2022-11-15 20:02:06 +01:00
commit b97ee269ea
1708 changed files with 60964 additions and 7606 deletions
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4
sys/contrib/device-tree/Bindings/Makefile
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@ -42,9 +42,7 @@ quiet_cmd_chk_bindings = CHKDT $@
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
printf '%s\n' $(real-prereqs), \
$(find_all_cmd)) > $$f ; \
$(find_all_cmd) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f

10
sys/contrib/device-tree/Bindings/arm/altera.yaml
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@ -25,7 +25,14 @@ properties:
items:
- enum:
- altr,socfpga-arria10-socdk
- enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Mercury+ AA1 boards
items:
- enum:
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
@ -47,6 +54,7 @@ properties:
items:
- enum:
- altr,socfpga-stratix10-socdk
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
- description: SoCFPGA VT

2
sys/contrib/device-tree/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
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@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Firmware registers Interface
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Meson SoCs have a register bank with status and data shared with the

101
sys/contrib/device-tree/Bindings/arm/arm,coresight-catu.yaml Normal file
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@ -0,0 +1,101 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Address Translation Unit (CATU)
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Address Translation Unit (CATU) translates addresses between an
AXI master and system memory. The CATU is normally used along with the TMC to
implement scattering of virtual trace buffers in physical memory. The CATU
translates contiguous Virtual Addresses (VAs) from an AXI master into
non-contiguous Physical Addresses (PAs) that are intended for system memory.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-catu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-catu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
interrupts:
maxItems: 1
description: Address translation error interrupt
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI Slave connected to another Coresight component
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
catu@207e0000 {
compatible = "arm,coresight-catu", "arm,primecell";
reg = <0x207e0000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
in-ports {
port {
catu_in_port: endpoint {
remote-endpoint = <&etr_out_port>;
};
};
};
};
...

81
sys/contrib/device-tree/Bindings/arm/arm,coresight-cpu-debug.yaml Normal file
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@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight CPU Debug Component
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight CPU debug component are compliant with the ARMv8 architecture
reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
external debug module is mainly used for two modes: self-hosted debug and
external debug, and it can be accessed from mmio region from Coresight and
eventually the debug module connects with CPU for debugging. And the debug
module provides sample-based profiling extension, which can be used to sample
CPU program counter, secure state and exception level, etc; usually every CPU
has one dedicated debug module to be connected.
select:
properties:
compatible:
contains:
const: arm,coresight-cpu-debug
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-cpu-debug
- const: arm,primecell
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
cpu:
description:
A phandle to the cpu this debug component is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
power-domains:
maxItems: 1
description:
A phandle to the debug power domain if the debug logic has its own
dedicated power domain. CPU idle states may also need to be separately
constrained to keep CPU cores powered.
required:
- compatible
- reg
- clocks
- clock-names
- cpu
unevaluatedProperties: false
examples:
- |
debug@f6590000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0xf6590000 0x1000>;
clocks = <&sys_ctrl 1>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
};
...

331
sys/contrib/device-tree/Bindings/arm/arm,coresight-cti.yaml Normal file
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@ -0,0 +1,331 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Cross Trigger Interface (CTI) device.
description: |
The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
to one or more CoreSight components and/or a CPU, with CTIs interconnected in
a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
The ECT components are not part of the trace generation data path and are thus
not part of the CoreSight graph.
The CTI component properties define the connections between the individual
CTI and the components it is directly connected to, consisting of input and
output hardware trigger signals. CTIs can have a maximum number of input and
output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
number is defined at design time, the maximum of each defined in the DEVID
register.
CTIs are interconnected in a star topology via the CTM, using a number of
programmable channels, usually 4, but again implementation defined and
described in the DEVID register. The star topology is not required to be
described in the bindings as the actual connections are software
programmable.
In general the connections between CTI and components via the trigger signals
are implementation defined, except when the CTI is connected to an ARM v8
architecture core and optional ETM.
In this case the ARM v8 architecture defines the required signal connections
between CTI and the CPU core and ETM if present. In the case of a v8
architecturally connected CTI an additional compatible string is used to
indicate this feature (arm,coresight-cti-v8-arch).
When CTI trigger connection information is unavailable then a minimal driver
binding can be declared with no explicit trigger signals. This will result
the driver detecting the maximum available triggers and channels from the
DEVID register and make them all available for use as a single default
connection. Any user / client application will require additional information
on the connections between the CTI and other components for correct operation.
This information might be found by enabling the Integration Test registers in
the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
configuration). These registers may be used to explore the trigger connections
between CTI and other CoreSight components.
Certain triggers between CoreSight devices and the CTI have specific types
and usages. These can be defined along with the signal indexes with the
constants defined in <dt-bindings/arm/coresight-cti-dt.h>
For example a CTI connected to a core will usually have a DBGREQ signal. This
is defined in the binding as type PE_EDBGREQ. These types will appear in an
optional array alongside the signal indexes. Omitting types will default all
signals to GEN_IO.
Note that some hardware trigger signals can be connected to non-CoreSight
components (e.g. UART etc) depending on hardware implementation.
maintainers:
- Mike Leach <mike.leach@linaro.org>
allOf:
- $ref: /schemas/arm/primecell.yaml#
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
enum:
- arm,coresight-cti
required:
- compatible
properties:
$nodename:
pattern: "^cti(@[0-9a-f]+)$"
compatible:
oneOf:
- items:
- const: arm,coresight-cti
- const: arm,primecell
- items:
- const: arm,coresight-cti-v8-arch
- const: arm,coresight-cti
- const: arm,primecell
reg:
maxItems: 1
cpu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Handle to cpu this device is associated with. This must appear in the
base cti node if compatible string arm,coresight-cti-v8-arch is used,
or may appear in a trig-conns child node when appropriate.
arm,cti-ctm-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the CTM this CTI is connected to, in large systems with multiple
separate CTI/CTM nets. Typically multi-socket systems where the CTM is
propagated between sockets.
arm,cs-dev-assoc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
defines a phandle reference to an associated CoreSight trace device.
When the associated trace device is enabled, then the respective CTI
will be enabled. Use in a trig-conns node, or in CTI base node when
compatible string arm,coresight-cti-v8-arch used. If the associated
device has not been registered then the node name will be stored as
the connection name for later resolution. If the associated device is
not a CoreSight device or not registered then the node name will remain
the connection name and automatic enabling will not occur.
# size cells and address cells required if trig-conns node present.
"#size-cells":
const: 0
"#address-cells":
const: 1
patternProperties:
'^trig-conns@([0-9]+)$':
type: object
description:
A trigger connections child node which describes the trigger signals
between this CTI and another hardware device. This device may be a CPU,
CoreSight device, any other hardware device or simple external IO lines.
The connection may have both input and output triggers, or only one or the
other.
properties:
reg:
maxItems: 1
arm,trig-in-sigs:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger in signal numbers in use by a trig-conns node.
arm,trig-in-types:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of constants representing the types for the CTI trigger in
signals. Types in this array match to the corresponding signal in the
arm,trig-in-sigs array. If the -types array is smaller, or omitted
completely, then the types will default to GEN_IO.
arm,trig-out-sigs:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger out signal numbers in use by a trig-conns node.
arm,trig-out-types:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of constants representing the types for the CTI trigger out
signals. Types in this array match to the corresponding signal
in the arm,trig-out-sigs array. If the "-types" array is smaller,
or omitted completely, then the types will default to GEN_IO.
arm,trig-filters:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger out signals that will be blocked from becoming
active, unless filtering is disabled on the driver.
arm,trig-conn-name:
$ref: /schemas/types.yaml#/definitions/string
description:
Defines a connection name that will be displayed, if the cpu or
arm,cs-dev-assoc properties are not being used in this connection.
Principle use for CTI that are connected to non-CoreSight devices, or
external IO.
anyOf:
- required:
- arm,trig-in-sigs
- required:
- arm,trig-out-sigs
oneOf:
- required:
- arm,trig-conn-name
- required:
- cpu
- required:
- arm,cs-dev-assoc
required:
- reg
required:
- compatible
- reg
- clocks
- clock-names
if:
properties:
compatible:
contains:
const: arm,coresight-cti-v8-arch
then:
required:
- cpu
unevaluatedProperties: false
examples:
# minimum CTI definition. DEVID register used to set number of triggers.
- |
cti@20020000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x20020000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
};
# v8 architecturally defined CTI - CPU + ETM connections generated by the
# driver according to the v8 architecture specification.
- |
cti@859000 {
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
"arm,primecell";
reg = <0x859000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
arm,cs-dev-assoc = <&etm1>;
};
# Implementation defined CTI - CPU + ETM connections explicitly defined..
# Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
# #size-cells and #address-cells are required if trig-conns@ nodes present.
- |
#include <dt-bindings/arm/coresight-cti-dt.h>
cti@858000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x858000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
arm,cti-ctm-id = <1>;
#address-cells = <1>;
#size-cells = <0>;
trig-conns@0 {
reg = <0>;
arm,trig-in-sigs = <4 5 6 7>;
arm,trig-in-types = <ETM_EXTOUT
ETM_EXTOUT
ETM_EXTOUT
ETM_EXTOUT>;
arm,trig-out-sigs = <4 5 6 7>;
arm,trig-out-types = <ETM_EXTIN
ETM_EXTIN
ETM_EXTIN
ETM_EXTIN>;
arm,cs-dev-assoc = <&etm0>;
};
trig-conns@1 {
reg = <1>;
cpu = <&CPU0>;
arm,trig-in-sigs = <0 1>;
arm,trig-in-types = <PE_DBGTRIGGER
PE_PMUIRQ>;
arm,trig-out-sigs=<0 1 2 >;
arm,trig-out-types = <PE_EDBGREQ
PE_DBGRESTART
PE_CTIIRQ>;
arm,trig-filters = <0>;
};
};
# Implementation defined CTI - non CoreSight component connections.
- |
cti@20110000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x20110000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
trig-conns@0 {
reg = <0>;
arm,trig-in-sigs=<0>;
arm,trig-in-types=<GEN_INTREQ>;
arm,trig-out-sigs=<0>;
arm,trig-out-types=<GEN_HALTREQ>;
arm,trig-conn-name = "sys_profiler";
};
trig-conns@1 {
reg = <1>;
arm,trig-out-sigs=<2 3>;
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "watchdog";
};
trig-conns@2 {
reg = <2>;
arm,trig-in-sigs=<1 6>;
arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "g_counter";
};
};
...

126
sys/contrib/device-tree/Bindings/arm/arm,coresight-dynamic-funnel.yaml Normal file
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@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Programmable Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight funnel merges 2-8 trace sources into a single trace
stream with programmable enable and priority of input ports.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-funnel
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-funnel
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-7])?$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
funnel@20040000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x20040000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
funnel_out_port0: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in_port0: endpoint {
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <1>;
funnel_in_port1: endpoint {
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <2>;
funnel_in_port2: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
};
...

126
sys/contrib/device-tree/Bindings/arm/arm,coresight-dynamic-replicator.yaml Normal file
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@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Coresight Programmable Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-dynamic-replicator
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-dynamic-replicator
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
qcom,replicator-loses-context:
type: boolean
description:
Indicates that the replicator will lose register context when AMBA clock
is removed which is observed in some replicator designs.
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[01])?$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
- out-ports
unevaluatedProperties: false
examples:
- |
replicator@20120000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x20120000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&csys2_funnel_out_port>;
};
};
};
};
...

92
sys/contrib/device-tree/Bindings/arm/arm,coresight-etb10.yaml Normal file
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace Buffer
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
used as a circular buffer.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-etb10
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-etb10
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etb@20010000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x20010000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etb_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
...

156
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Embedded Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Embedded Trace Macrocell (ETM) is a real-time trace module providing
instruction and data tracing of a processor.
select:
properties:
compatible:
contains:
enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- arm,coresight-etm4x-sysreg
required:
- compatible
allOf:
- if:
not:
properties:
compatible:
contains:
const: arm,coresight-etm4x-sysreg
then:
$ref: /schemas/arm/primecell.yaml#
required:
- reg
properties:
compatible:
oneOf:
- description:
Embedded Trace Macrocell with memory mapped access.
items:
- enum:
- arm,coresight-etm3x
- arm,coresight-etm4x
- const: arm,primecell
- description:
Embedded Trace Macrocell (version 4.x), with system register access only
const: arm,coresight-etm4x-sysreg
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,coresight-loses-context-with-cpu:
type: boolean
description:
Indicates that the hardware will lose register context on CPU power down
(e.g. CPUIdle). An example of where this may be needed are systems which
contain a coresight component and CPU in the same power domain. When the
CPU powers down the coresight component also powers down and loses its
context.
arm,cp14:
type: boolean
description:
Must be present if the system accesses ETM/PTM management registers via
co-processor 14.
qcom,skip-power-up:
type: boolean
description:
Indicates that an implementation can skip powering up the trace unit.
TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
since ETMs are in the same power domain as their CPU cores. This property
is required to identify such systems with hardware errata where the CPU
watchdog counter is stopped when TRCPDCR.PU is set.
cpu:
description:
phandle to the cpu this ETM is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- clocks
- clock-names
- cpu
- out-ports
unevaluatedProperties: false
examples:
- |
ptm@2201c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201c000 0x1000>;
cpu = <&cpu0>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
ptm@2201d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x2201d000 0x1000>;
cpu = <&cpu1>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
out-ports {
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel_in_port1>;
};
};
};
};
...

90
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Funnel
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight static funnel merges 2-8 trace sources into a single trace
stream.
properties:
compatible:
const: arm,coresight-static-funnel
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[0-7]$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
funnel {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint = <&top_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint = <&cluster0_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint = <&cluster1_etf_out>;
};
};
};
};
...

91
sys/contrib/device-tree/Bindings/arm/arm,coresight-static-replicator.yaml Normal file
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@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Static Trace Bus Replicator
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight replicator splits a single trace stream into two trace streams
for systems that have more than one trace sink component.
properties:
compatible:
const: arm,coresight-static-replicator
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port@[01]$':
description: Output connections to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
- out-ports
additionalProperties: false
examples:
- |
replicator {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&etb_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
remote-endpoint = <&funnel_out_port0>;
};
};
};
};
...

101
sys/contrib/device-tree/Bindings/arm/arm,coresight-stm.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight System Trace MacroCell
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The STM is a trace source that is integrated into a CoreSight system, designed
primarily for high-bandwidth trace of instrumentation embedded into software.
This instrumentation is made up of memory-mapped writes to the STM Advanced
eXtensible Interface (AXI) slave, which carry information about the behavior
of the software.
select:
properties:
compatible:
contains:
const: arm,coresight-stm
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-stm
- const: arm,primecell
reg:
maxItems: 2
reg-names:
items:
- const: stm-base
- const: stm-stimulus-base
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- out-ports
unevaluatedProperties: false
examples:
- |
stm@20100000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x20100000 0x1000>,
<0x28000000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port2>;
};
};
};
};
...

131
sys/contrib/device-tree/Bindings/arm/arm,coresight-tmc.yaml Normal file
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@ -0,0 +1,131 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Memory Controller
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tmc
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tmc
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
arm,buffer-size:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description:
Size of contiguous buffer space for TMC ETR (embedded trace router). The
buffer size can be configured dynamically via buffer_size property in
sysfs instead.
arm,scatter-gather:
type: boolean
description:
Indicates that the TMC-ETR can safely use the SG mode on this system.
arm,max-burst-size:
description:
The maximum burst size initiated by TMC on the AXI master interface. The
burst size can be in the range [0..15], the setting supports one data
transfer per burst up to a maximum of 16 data transfers per burst.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: AXI or ATB Master output connection. Used for ETR
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator2_out_port0>;
};
};
};
out-ports {
port {
etr_out_port: endpoint {
remote-endpoint = <&catu_in_port>;
};
};
};
};
...

91
sys/contrib/device-tree/Bindings/arm/arm,coresight-tpiu.yaml Normal file
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@ -0,0 +1,91 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm CoreSight Trace Port Interface Unit
maintainers:
- Mathieu Poirier <mathieu.poirier@linaro.org>
- Mike Leach <mike.leach@linaro.org>
- Leo Yan <leo.yan@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The CoreSight Trace Port Interface Unit captures trace data from the trace bus
and outputs it to an external trace port.
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
const: arm,coresight-tpiu
required:
- compatible
allOf:
- $ref: /schemas/arm/primecell.yaml#
properties:
compatible:
items:
- const: arm,coresight-tpiu
- const: arm,primecell
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: apb_pclk
- const: atclk
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- in-ports
unevaluatedProperties: false
examples:
- |
tpiu@e3c05000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xe3c05000 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&funnel4_out_port0>;
};
};
};
};
...

74
sys/contrib/device-tree/Bindings/arm/arm,embedded-trace-extension.yaml Normal file
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@ -0,0 +1,74 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Embedded Trace Extensions
maintainers:
- Suzuki K Poulose <suzuki.poulose@arm.com>
- Mathieu Poirier <mathieu.poirier@linaro.org>
description: |
Arm Embedded Trace Extension(ETE) is a per CPU trace component that
allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
architecture and has extended support for future architecture changes.
The trace generated by the ETE could be stored via legacy CoreSight
components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
legacy CoreSight components, a node must be listed per instance, along
with any optional connection graph as per the coresight bindings.
properties:
$nodename:
pattern: "^ete([0-9a-f]+)$"
compatible:
items:
- const: arm,embedded-trace-extension
cpu:
description: |
Handle to the cpu this ETE is bound to.
$ref: /schemas/types.yaml#/definitions/phandle
out-ports:
description: |
Output connections from the ETE to legacy CoreSight trace bus.
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection from the ETE to legacy CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- cpu
additionalProperties: false
examples:
# An ETE node without legacy CoreSight connections
- |
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_0>;
};
# An ETE node with legacy CoreSight connections
- |
ete1 {
compatible = "arm,embedded-trace-extension";
cpu = <&cpu_1>;
out-ports { /* legacy coresight connection */
port {
ete1_out_port: endpoint {
remote-endpoint = <&funnel_in_port0>;
};
};
};
};
...

49
sys/contrib/device-tree/Bindings/arm/arm,trace-buffer-extension.yaml Normal file
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Trace Buffer Extensions
maintainers:
- Anshuman Khandual <anshuman.khandual@arm.com>
description: |
Arm Trace Buffer Extension (TRBE) is a per CPU component
for storing trace generated on the CPU to memory. It is
accessed via CPU system registers. The software can verify
if it is permitted to use the component by checking the
TRBIDR register.
properties:
$nodename:
const: "trbe"
compatible:
items:
- const: arm,trace-buffer-extension
interrupts:
description: |
Exactly 1 PPI must be listed. For heterogeneous systems where
TRBE is only supported on a subset of the CPUs, please consult
the arm,gic-v3 binding for details on describing a PPI partition.
maxItems: 1
required:
- compatible
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
...

87
sys/contrib/device-tree/Bindings/arm/aspeed/aspeed.yaml Normal file
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@ -0,0 +1,87 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SoC based boards
maintainers:
- Joel Stanley <joel@jms.id.au>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: AST2400 based boards
items:
- enum:
- facebook,galaxy100-bmc
- facebook,wedge100-bmc
- facebook,wedge40-bmc
- microsoft,olympus-bmc
- quanta,q71l-bmc
- tyan,palmetto-bmc
- yadro,vesnin-bmc
- const: aspeed,ast2400
- description: AST2500 based boards
items:
- enum:
- amd,ethanolx-bmc
- ampere,mtjade-bmc
- aspeed,ast2500-evb
- asrock,e3c246d4i-bmc
- asrock,romed8hm3-bmc
- bytedance,g220a-bmc
- facebook,cmm-bmc
- facebook,minipack-bmc
- facebook,tiogapass-bmc
- facebook,yamp-bmc
- facebook,yosemitev2-bmc
- facebook,wedge400-bmc
- hxt,stardragon4800-rep2-bmc
- ibm,mihawk-bmc
- ibm,mowgli-bmc
- ibm,romulus-bmc
- ibm,swift-bmc
- ibm,witherspoon-bmc
- ingrasys,zaius-bmc
- inspur,fp5280g2-bmc
- inspur,nf5280m6-bmc
- inspur,on5263m5-bmc
- intel,s2600wf-bmc
- inventec,lanyang-bmc
- lenovo,hr630-bmc
- lenovo,hr855xg2-bmc
- portwell,neptune-bmc
- qcom,centriq2400-rep-bmc
- supermicro,x11spi-bmc
- tyan,s7106-bmc
- tyan,s8036-bmc
- yadro,nicole-bmc
- yadro,vegman-n110-bmc
- yadro,vegman-rx20-bmc
- yadro,vegman-sx20-bmc
- const: aspeed,ast2500
- description: AST2600 based boards
items:
- enum:
- aspeed,ast2600-evb
- aspeed,ast2600-evb-a1
- facebook,bletchley-bmc
- facebook,cloudripper-bmc
- facebook,elbert-bmc
- facebook,fuji-bmc
- ibm,everest-bmc
- ibm,rainier-bmc
- ibm,tacoma-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- nuvia,dc-scm-bmc
- quanta,s6q-bmc
- const: aspeed,ast2600
additionalProperties: true

6
sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
View File

@ -163,9 +163,11 @@ properties:
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip LAN9662 PCB8291 Evaluation Board.
- description: Microchip LAN9662 Evaluation Boards.
items:
- const: microchip,lan9662-pcb8291
- enum:
- microchip,lan9662-pcb8291
- microchip,lan9662-pcb8309
- const: microchip,lan9662
- const: microchip,lan966

15
sys/contrib/device-tree/Bindings/arm/atmel-sysregs.txt
View File

@ -25,21 +25,6 @@ System Timer (ST) required properties:
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
it also can be "microchip,sam9x60-rstc"
- reg: Should contain registers location and length
- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",

7
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4708.yaml
View File

@ -87,6 +87,13 @@ properties:
- const: brcm,bcm53012
- const: brcm,bcm4708
- description: BCM53015 based boards
items:
- enum:
- meraki,mr26
- const: brcm,bcm53015
- const: brcm,bcm4708
- description: BCM53016 based boards
items:
- enum:

93
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcmbca.yaml
View File

@ -28,6 +28,99 @@ properties:
- const: brcm,bcm47622
- const: brcm,bcmbca
- description: BCM4912 based boards
items:
- enum:
- asus,gt-ax6000
- brcm,bcm94912
- const: brcm,bcm4912
- const: brcm,bcmbca
- description: BCM63138 based boards
items:
- enum:
- brcm,bcm963138
- brcm,BCM963138DVT
- const: brcm,bcm63138
- const: brcm,bcmbca
- description: BCM63146 based boards
items:
- enum:
- brcm,bcm963146
- const: brcm,bcm63146
- const: brcm,bcmbca
- description: BCM63148 based boards
items:
- enum:
- brcm,bcm963148
- const: brcm,bcm63148
- const: brcm,bcmbca
- description: BCM63158 based boards
items:
- enum:
- brcm,bcm963158
- const: brcm,bcm63158
- const: brcm,bcmbca
- description: BCM63178 based boards
items:
- enum:
- brcm,bcm963178
- const: brcm,bcm63178
- const: brcm,bcmbca
- description: BCM6756 based boards
items:
- enum:
- brcm,bcm96756
- const: brcm,bcm6756
- const: brcm,bcmbca
- description: BCM6813 based boards
items:
- enum:
- brcm,bcm96813
- const: brcm,bcm6813
- const: brcm,bcmbca
- description: BCM6846 based boards
items:
- enum:
- brcm,bcm96846
- const: brcm,bcm6846
- const: brcm,bcmbca
- description: BCM6855 based boards
items:
- enum:
- brcm,bcm96855
- const: brcm,bcm6855
- const: brcm,bcmbca
- description: BCM6856 based boards
items:
- enum:
- brcm,bcm96856
- const: brcm,bcm6856
- const: brcm,bcmbca
- description: BCM6858 based boards
items:
- enum:
- brcm,bcm96858
- const: brcm,bcm6858
- const: brcm,bcmbca
- description: BCM6878 based boards
items:
- enum:
- brcm,bcm96878
- const: brcm,bcm6878
- const: brcm,bcmbca
additionalProperties: true
...

2
sys/contrib/device-tree/Bindings/arm/cpus.yaml
View File

@ -138,6 +138,7 @@ properties:
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-m0
@ -221,6 +222,7 @@ properties:
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- qcom,msm8226-smp
- qcom,msm8909-smp
# Only valid on ARM 32-bit, see above for ARM v8 64-bit
- qcom,msm8916-smp
- renesas,apmu

61
sys/contrib/device-tree/Bindings/arm/fsl.yaml
View File

@ -321,6 +321,7 @@ properties:
- enum:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
@ -670,30 +671,30 @@ properties:
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
- toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3
- toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
- toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
- toradex,colibri-imx6ull-aster # Aster Carrier Board
- toradex,colibri-imx6ull-eval # Colibri Evaluation Board V3
- toradex,colibri-imx6ull-iris # Iris Carrier Board
- toradex,colibri-imx6ull-iris-v2 # Iris V2 Carrier Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
- toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
- toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
- toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
- toradex,colibri-imx6ull-emmc-aster # Aster Carrier Board
- toradex,colibri-imx6ull-emmc-eval # Colibri Evaluation B. V3
- toradex,colibri-imx6ull-emmc-iris # Iris Carrier Board
- toradex,colibri-imx6ull-emmc-iris-v2 # Iris V2 Carrier Board
- const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
- toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
- toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
- toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
- toradex,colibri-imx6ull-wifi-eval # Colibri Eval. B. V3
- toradex,colibri-imx6ull-wifi-aster # Aster Carrier Board
- toradex,colibri-imx6ull-wifi-iris # Iris Carrier Board
- toradex,colibri-imx6ull-wifi-iris-v2 # Iris V2 Carrier Board
- const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- const: fsl,imx6ull
@ -738,6 +739,8 @@ properties:
- enum:
- toradex,colibri-imx7s-aster # Module on Aster Carrier Board
- toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3
- toradex,colibri-imx7s-iris # Module on Iris Carrier Board
- toradex,colibri-imx7s-iris-v2 # Module on Iris Carrier Board V2
- const: toradex,colibri-imx7s
- const: fsl,imx7s
@ -789,8 +792,10 @@ properties:
- description: i.MX7D Boards with Toradex Colibri i.MX7D Module
items:
- enum:
- toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-aster # Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3
- toradex,colibri-imx7d-iris # Iris Carrier Board
- toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2
- const: toradex,colibri-imx7d
- const: fsl,imx7d
@ -799,6 +804,8 @@ properties:
- enum:
- toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3
- toradex,colibri-imx7d-emmc-iris # Module on Iris Carrier Board
- toradex,colibri-imx7d-emmc-iris-v2 # Module on Iris Carrier Board V2
- const: toradex,colibri-imx7d-emmc
- const: fsl,imx7d
@ -865,6 +872,12 @@ properties:
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
- description: PHYTEC phyCORE-i.MX8MM SoM based boards
items:
- const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK
- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
- const: fsl,imx8mm
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@ -914,6 +927,8 @@ properties:
- description: i.MX8MP based Boards
items:
- enum:
- dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
- dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
@ -952,6 +967,18 @@ properties:
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
- const: fsl,imx8mp
- description:
TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip
variants. It is designed to be soldered on different carrier boards.
All CPU variants use the same device tree hence only one compatible
is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed
version as an industrial computing device.
items:
- enum:
- tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
- const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
items:
- enum:
@ -1020,6 +1047,12 @@ properties:
- fsl,imx8ulp-evk # i.MX8ULP EVK Board
- const: fsl,imx8ulp
- description: i.MX93 based Boards
items:
- enum:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings

2
sys/contrib/device-tree/Bindings/arm/marvell/ap80x-system-controller.txt
View File

@ -72,7 +72,7 @@ mpp19 19 gpio, uart0(rxd), sdio(pw_off)
GPIO:
-----
For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
Required properties:

2
sys/contrib/device-tree/Bindings/arm/marvell/cp110-system-controller.txt
View File

@ -156,7 +156,7 @@ GPIO:
-----
For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.
Required properties:

32
sys/contrib/device-tree/Bindings/arm/marvell/marvell,ac5.yaml Normal file
View File

@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Alleycat5/5X Platforms
maintainers:
- Chris Packham <chris.packham@alliedtelesis.co.nz>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Alleycat5 (98DX25xx) Reference Design
items:
- enum:
- marvell,rd-ac5
- const: marvell,ac5
- description: Alleycat5X (98DX35xx) Reference Design
items:
- enum:
- marvell,rd-ac5x
- const: marvell,ac5x
- const: marvell,ac5
additionalProperties: true
...

30
sys/contrib/device-tree/Bindings/arm/mediatek.yaml
View File

@ -131,6 +131,36 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- description: Google Hayato
items:
- const: google,hayato-rev1
- const: google,hayato
- const: mediatek,mt8192
- description: Google Spherion (Acer Chromebook 514)
items:
- const: google,spherion-rev3
- const: google,spherion-rev2
- const: google,spherion-rev1
- const: google,spherion-rev0
- const: google,spherion
- const: mediatek,mt8192
- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
items:
- enum:
- google,tomato-rev2
- google,tomato-rev1
- const: google,tomato
- const: mediatek,mt8195
- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
items:
- const: google,tomato-rev4
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8192-evb

3
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
View File

@ -39,6 +39,9 @@ properties:
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg

8
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml
View File

@ -24,7 +24,6 @@ properties:
- mediatek,mt8192-imp_iic_wrap_w
- mediatek,mt8192-imp_iic_wrap_n
- mediatek,mt8192-msdc_top
- mediatek,mt8192-msdc
- mediatek,mt8192-mfgcfg
- mediatek,mt8192-imgsys
- mediatek,mt8192-imgsys2
@ -107,13 +106,6 @@ examples:
#clock-cells = <1>;
};
- |
msdc: clock-controller@11f60000 {
compatible = "mediatek,mt8192-msdc";
reg = <0x11f60000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg";

3
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
View File

@ -29,6 +29,9 @@ properties:
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg

3
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
View File

@ -37,6 +37,9 @@ properties:
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg

1
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,pericfg.yaml
View File

@ -26,6 +26,7 @@ properties:
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon

2
sys/contrib/device-tree/Bindings/arm/msm/qcom,saw2.txt
View File

@ -10,7 +10,7 @@ system, notifying them when a low power state is entered or exited.
Multiple revisions of the SAW hardware are supported using these Device Nodes.
SAW2 revisions differ in the register offset and configuration data. Also, the
same revision of the SAW in different SoCs may have different configuration
data due the the differences in hardware capabilities. Hence the SoC name, the
data due the differences in hardware capabilities. Hence the SoC name, the
version of the SAW hardware in that SoC and the distinction between cpu (big
or Little) or cache, may be needed to uniquely identify the SAW register
configuration and initialization data. The compatible string is used to

7
sys/contrib/device-tree/Bindings/arm/npcm/npcm.yaml
View File

@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
- Tomer Maimon <tmaimon77@gmail.com>
properties:
$nodename:
@ -26,4 +27,10 @@ properties:
- nuvoton,npcm750-evb # NPCM750 evaluation board
- const: nuvoton,npcm750
- description: NPCM845 based boards
items:
- enum:
- nuvoton,npcm845-evb # NPCM845 evaluation board
- const: nuvoton,npcm845
additionalProperties: true

2
sys/contrib/device-tree/Bindings/arm/npcm/nuvoton,gcr.yaml
View File

@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
- Tomer Maimon <tmaimon77@gmail.com>
description:
The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
@ -20,6 +21,7 @@ properties:
- enum:
- nuvoton,wpcm450-gcr
- nuvoton,npcm750-gcr
- nuvoton,npcm845-gcr
- const: syscon
- const: simple-mfd

443
sys/contrib/device-tree/Bindings/arm/qcom.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: QCOM device tree bindings
maintainers:
- Stephen Boyd <sboyd@codeaurora.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Some qcom based bootloaders identify the dtb blob based on a set of
@ -38,18 +38,24 @@ description: |
msm8992
msm8994
msm8996
msm8998
qcs404
sa8155p
sa8540p
sc7180
sc7280
sc8180x
sc8280xp
sda660
sdm630
sdm632
sdm636
sdm660
sdm845
sdx55
sdx65
sm6125
sm6350
sm7225
sm8150
sm8250
@ -90,6 +96,11 @@ description: |
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
foundry 2.
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
https://docs.kernel.org/arm/google/chromebook-boot-flow.html
properties:
$nodename:
const: "/"
@ -153,28 +164,50 @@ properties:
- const: qcom,msm8974
- items:
- enum:
- alcatel,idol347
- const: qcom,msm8916-mtp/1
- const: qcom,msm8916-mtp
- const: qcom,msm8916-mtp/1
- const: qcom,msm8916
- items:
- enum:
- longcheer,l8150
- alcatel,idol347
- asus,z00l
- huawei,g7
- longcheer,l8910
- samsung,a3u-eur
- samsung,a5u-eur
- samsung,j5
- samsung,serranove
- wingtech,wt88047
- const: qcom,msm8916
- items:
- const: longcheer,l8150
- const: qcom,msm8916-v1-qrd/9-v1
- const: qcom,msm8916
- items:
- enum:
- lg,bullhead
- microsoft,talkman
- xiaomi,libra
- const: qcom,msm8992
- items:
- enum:
- sony,karin_windy
- const: qcom,apq8094
- items:
- enum:
- huawei,angler
- microsoft,cityman
- sony,ivy-row
- sony,karin-row
- sony,satsuki-row
- sony,sumire-row
- sony,suzuran-row
- qcom,msm8994
- const: qcom,apq8094
- const: qcom,msm8994
- items:
- enum:
@ -190,9 +223,24 @@ properties:
- sony,kagura-row
- sony,keyaki-row
- xiaomi,gemini
- xiaomi,natrium
- xiaomi,scorpio
- const: qcom,msm8996
- items:
- enum:
- asus,novago-tp370ql
- fxtec,pro1
- hp,envy-x2
- lenovo,miix-630
- oneplus,cheeseburger
- oneplus,dumpling
- qcom,msm8998-mtp
- sony,xperia-lilac
- sony,xperia-maple
- sony,xperia-poplar
- const: qcom,msm8998
- items:
- enum:
- qcom,ipq4019-ap-dk01.1-c1
@ -214,19 +262,317 @@ properties:
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
- items:
- description: Qualcomm Technologies, Inc. SC7180 IDP
items:
- enum:
- qcom,sc7180-idp
- const: qcom,sc7180
- items:
- enum:
- qcom,sc7280-crd
- qcom,sc7280-idp
- qcom,sc7280-idp2
- google,hoglin
- google,piglin
- google,senor
- description: HP Chromebook x2 11c (rev1 - 2)
items:
- const: google,coachz-rev1
- const: google,coachz-rev2
- const: qcom,sc7180
- description: HP Chromebook x2 11c (newest rev)
items:
- const: google,coachz
- const: qcom,sc7180
- description: HP Chromebook x2 11c with LTE (rev1 - 2)
items:
- const: google,coachz-rev1-sku0
- const: google,coachz-rev2-sku0
- const: qcom,sc7180
- description: HP Chromebook x2 11c with LTE (newest rev)
items:
- const: google,coachz-sku0
- const: qcom,sc7180
- description: Lenovo Chromebook Duet 5 13 (rev2)
items:
- const: google,homestar-rev2
- const: google,homestar-rev23
- const: qcom,sc7180
- description: Lenovo Chromebook Duet 5 13 (rev3)
items:
- const: google,homestar-rev3
- const: qcom,sc7180
- description: Lenovo Chromebook Duet 5 13 (newest rev)
items:
- const: google,homestar
- const: qcom,sc7180
- description: Google Kingoftown (rev0)
items:
- const: google,kingoftown-rev0
- const: qcom,sc7180
- description: Google Kingoftown (newest rev)
items:
- const: google,kingoftown
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (rev0)
items:
- const: google,lazor-rev0
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (rev1 - 2)
items:
- const: google,lazor-rev1
- const: google,lazor-rev2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (rev3 - 8)
items:
- const: google,lazor-rev3
- const: google,lazor-rev4
- const: google,lazor-rev5
- const: google,lazor-rev6
- const: google,lazor-rev7
- const: google,lazor-rev8
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (newest rev)
items:
- const: google,lazor
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2)
items:
- const: google,lazor-rev1-sku2
- const: google,lazor-rev2-sku2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8)
items:
- const: google,lazor-rev3-sku2
- const: google,lazor-rev4-sku2
- const: google,lazor-rev5-sku2
- const: google,lazor-rev6-sku2
- const: google,lazor-rev7-sku2
- const: google,lazor-rev8-sku2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with KB Backlight (newest rev)
items:
- const: google,lazor-sku2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with LTE (rev1 - 2)
items:
- const: google,lazor-rev1-sku0
- const: google,lazor-rev2-sku0
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with LTE (rev3 - 8)
items:
- const: google,lazor-rev3-sku0
- const: google,lazor-rev4-sku0
- const: google,lazor-rev5-sku0
- const: google,lazor-rev6-sku0
- const: google,lazor-rev7-sku0
- const: google,lazor-rev8-sku0
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with LTE (newest rev)
items:
- const: google,lazor-sku0
- const: qcom,sc7180
- description: Acer Chromebook 511 (rev4 - rev8)
items:
- const: google,lazor-rev4-sku4
- const: google,lazor-rev5-sku4
- const: google,lazor-rev6-sku4
- const: google,lazor-rev7-sku4
- const: google,lazor-rev8-sku4
- const: qcom,sc7180
- description: Acer Chromebook 511 (newest rev)
items:
- const: google,lazor-sku4
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (rev4)
items:
- const: google,lazor-rev4-sku5
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (rev5 - rev8)
items:
- const: google,lazor-rev5-sku5
- const: google,lazor-rev5-sku6
- const: google,lazor-rev6-sku6
- const: google,lazor-rev7-sku6
- const: google,lazor-rev8-sku6
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (newest rev)
items:
- const: google,lazor-sku6
- const: qcom,sc7180
- description: Google Mrbland with AUO panel (rev0)
items:
- const: google,mrbland-rev0-sku0
- const: qcom,sc7180
- description: Google Mrbland with AUO panel (newest rev)
items:
- const: google,mrbland-sku1536
- const: qcom,sc7180
- description: Google Mrbland with BOE panel (rev0)
items:
- const: google,mrbland-rev0-sku16
- const: qcom,sc7180
- description: Google Mrbland with BOE panel (newest rev)
items:
- const: google,mrbland-sku1024
- const: google,mrbland-sku768
- const: qcom,sc7180
- description: Google Pazquel with Parade (newest rev)
items:
- const: google,pazquel-sku5
- const: qcom,sc7180
- description: Google Pazquel with TI (newest rev)
items:
- const: google,pazquel-sku1
- const: qcom,sc7180
- description: Google Pazquel with LTE and Parade (newest rev)
items:
- const: google,pazquel-sku4
- const: qcom,sc7180
- description: Google Pazquel with LTE and TI (newest rev)
items:
- const: google,pazquel-sku0
- const: google,pazquel-sku2
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 (rev1)
items:
- const: google,pompom-rev1
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 (rev2)
items:
- const: google,pompom-rev2
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 (newest rev)
items:
- const: google,pompom
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 with LTE (rev1)
items:
- const: google,pompom-rev1-sku0
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 with LTE (rev2)
items:
- const: google,pompom-rev2-sku0
- const: qcom,sc7180
- description: Sharp Dynabook Chromebook C1 with LTE (newest rev)
items:
- const: google,pompom-sku0
- const: qcom,sc7180
- description: Google Quackingstick (newest rev)
items:
- const: google,quackingstick-sku1537
- const: qcom,sc7180
- description: Google Quackingstick with LTE (newest rev)
items:
- const: google,quackingstick-sku1536
- const: qcom,sc7180
- description: Google Trogdor (newest rev)
items:
- const: google,trogdor
- const: qcom,sc7180
- description: Google Trogdor with LTE (newest rev)
items:
- const: google,trogdor-sku0
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0)
items:
- const: google,wormdingler-rev0-sku16
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev)
items:
- const: google,wormdingler-sku1024
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev)
items:
- const: google,wormdingler-sku1025
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0)
items:
- const: google,wormdingler-rev0-sku0
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev)
items:
- const: google,wormdingler-sku0
- const: qcom,sc7180
- description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev)
items:
- const: google,wormdingler-sku1
- const: qcom,sc7180
- description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)
items:
- const: qcom,sc7280-crd
- const: google,hoglin-rev3
- const: google,hoglin-rev4
- const: google,piglin-rev3
- const: google,piglin-rev4
- const: qcom,sc7280
- description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev)
items:
- const: google,hoglin
- const: qcom,sc7280
- description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform
items:
- const: qcom,sc7280-idp
- const: google,senor
- const: qcom,sc7280
- description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform
items:
- const: qcom,sc7280-idp2
- const: google,piglin
- const: qcom,sc7280
- description: Google Herobrine (newest rev)
items:
- const: google,herobrine
- const: qcom,sc7280
- description: Google Villager (newest rev)
items:
- const: google,villager
- const: qcom,sc7280
- items:
@ -238,14 +584,34 @@ properties:
- items:
- enum:
- lenovo,thinkpad-x13s
- qcom,sc8280xp-crd
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
- items:
- enum:
- sony,discovery-row
- sony,kirin-row
- sony,pioneer-row
- sony,voyager-row
- const: qcom,sdm630
- items:
- enum:
- inforce,ifc6560
- const: qcom,sda660
- items:
- enum:
- fairphone,fp3
- const: qcom,sdm632
- items:
- enum:
- sony,mermaid-row
- const: qcom,sdm636
- items:
- enum:
- xiaomi,lavender
@ -269,6 +635,13 @@ properties:
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
- items:
- enum:
- qcom,qcs404-evb-1000
- qcom,qcs404-evb-4000
- const: qcom,qcs404-evb
- const: qcom,qcs404
- items:
- enum:
- qcom,sa8155p-adp
@ -279,6 +652,34 @@ properties:
- qcom,sa8295p-adp
- const: qcom,sa8540p
- items:
- enum:
- lenovo,yoga-c630
- lg,judyln
- lg,judyp
- oneplus,enchilada
- oneplus,fajita
- qcom,sdm845-mtp
- shift,axolotl
- samsung,w737
- sony,akari-row
- sony,akatsuki-row
- sony,apollo-row
- thundercomm,db845c
- xiaomi,beryllium
- xiaomi,polaris
- const: qcom,sdm845
- items:
- enum:
- sony,pdx201
- const: qcom,sm6125
- items:
- enum:
- sony,pdx213
- const: qcom,sm6350
- items:
- enum:
- fairphone,fp4
@ -286,19 +687,29 @@ properties:
- items:
- enum:
- microsoft,surface-duo
- qcom,sm8150-hdk
- qcom,sm8150-mtp
- sony,bahamut-generic
- sony,griffin-generic
- const: qcom,sm8150
- items:
- enum:
- qcom,qrb5165-rb5
- qcom,sm8250-hdk
- qcom,sm8250-mtp
- sony,pdx203-generic
- sony,pdx206-generic
- const: qcom,sm8250
- items:
- enum:
- microsoft,surface-duo2
- qcom,sm8350-hdk
- qcom,sm8350-mtp
- sony,pdx214-generic
- sony,pdx215-generic
- const: qcom,sm8350
- items:

5
sys/contrib/device-tree/Bindings/arm/rockchip.yaml
View File

@ -554,6 +554,11 @@ properties:
- const: vamrs,rk3399pro-vmarc-som
- const: rockchip,rk3399pro
- description: Radxa ROCK Pi S
items:
- const: radxa,rockpis
- const: rockchip,rk3308
- description: Radxa Rock2 Square
items:
- const: radxa,rock2-square

40
sys/contrib/device-tree/Bindings/arm/samsung/samsung-soc.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C, S5P and Exynos SoC compatibles naming convention
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Guidelines for new compatibles for SoC blocks/components.
When adding new compatibles in new bindings, use the format::
samsung,SoC-IP
For example::
samsung,exynos5433-cmu-isp
select:
properties:
compatible:
pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$"
required:
- compatible
properties:
compatible:
oneOf:
- description: Preferred naming style for compatibles of SoC components
pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$"
# Legacy compatibles with wild-cards - list cannot grow with new bindings:
- enum:
- samsung,exynos4x12-pinctrl
- samsung,exynos4x12-usb2-phy
- samsung,s3c64xx-pinctrl
- samsung,s3c64xx-wakeup-eint
additionalProperties: true

8
sys/contrib/device-tree/Bindings/arm/stm32/stm32.yaml
View File

@ -59,12 +59,18 @@ properties:
- prt,prtt1s # Protonic PRTT1S
- const: st,stm32mp151
- description: DH STM32MP153 SoM based Boards
- description: DH STM32MP153 DHCOM SoM based Boards
items:
- const: dh,stm32mp153c-dhcom-drc02
- const: dh,stm32mp153c-dhcom-som
- const: st,stm32mp153
- description: DH STM32MP153 DHCOR SoM based Boards
items:
- const: dh,stm32mp153c-dhcor-drc-compact
- const: dh,stm32mp153c-dhcor-som
- const: st,stm32mp153
- items:
- enum:
- shiratech,stm32mp157a-iot-box # IoT Box

29
sys/contrib/device-tree/Bindings/arm/sunplus,sp7021.yaml Normal file
View File

@ -0,0 +1,29 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sunplus SP7021 Boards
maintainers:
- qinjian <qinjian@cqplus1.com>
description: |
ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- sunplus,sp7021-achip
- sunplus,sp7021-demo-v3
- const: sunplus,sp7021
additionalProperties: true
...

10
sys/contrib/device-tree/Bindings/arm/sunxi.yaml
View File

@ -863,6 +863,11 @@ properties:
- const: yones-toptech,bs1078-v2
- const: allwinner,sun6i-a31s
- description: X96 Mate TV box
items:
- const: hechuang,x96-mate
- const: allwinner,sun50i-h616
- description: Xunlong OrangePi
items:
- const: xunlong,orangepi
@ -963,4 +968,9 @@ properties:
- const: xunlong,orangepi-zero-plus2-h3
- const: allwinner,sun8i-h3
- description: Xunlong OrangePi Zero 2
items:
- const: xunlong,orangepi-zero2
- const: allwinner,sun50i-h616
additionalProperties: true

24
sys/contrib/device-tree/Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
View File

@ -29,10 +29,20 @@ properties:
compatible:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-a33-mbus
- allwinner,sun8i-a50-mbus
- allwinner,sun8i-a83t-mbus
- allwinner,sun8i-h3-mbus
- allwinner,sun8i-r40-mbus
- allwinner,sun8i-v3s-mbus
- allwinner,sun8i-v536-mbus
- allwinner,sun20i-d1-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-a100-mbus
- allwinner,sun50i-h5-mbus
- allwinner,sun50i-h6-mbus
- allwinner,sun50i-h616-mbus
- allwinner,sun50i-r329-mbus
reg:
minItems: 1
@ -81,13 +91,13 @@ required:
- dma-ranges
if:
properties:
compatible:
contains:
enum:
- allwinner,sun8i-h3-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-h5-mbus
not:
properties:
compatible:
contains:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-r40-mbus
then:
properties:

1
sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
View File

@ -40,7 +40,6 @@ required:
- compatible
- reg
- nvidia,bpmp
- status
examples:
- |

40
sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NVIDIA Tegra194 AXI2APB bridge
maintainers:
- Sumit Gupta <sumitg@nvidia.com>
properties:
$nodename:
pattern: "^axi2apb@([0-9a-f]+)$"
compatible:
enum:
- nvidia,tegra194-axi2apb
reg:
maxItems: 6
description: Physical base address and length of registers for all bridges
additionalProperties: false
required:
- compatible
- reg
examples:
- |
axi2apb: axi2apb@2390000 {
compatible = "nvidia,tegra194-axi2apb";
reg = <0x02390000 0x1000>,
<0x023a0000 0x1000>,
<0x023b0000 0x1000>,
<0x023c0000 0x1000>,
<0x023d0000 0x1000>,
<0x023e0000 0x1000>;
};

97
sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra194-cbb.yaml Normal file
View File

@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NVIDIA Tegra194 CBB 1.0 bindings
maintainers:
- Sumit Gupta <sumitg@nvidia.com>
description: |+
The Control Backbone (CBB) is comprised of the physical path from an
initiator to a target's register configuration space. CBB 1.0 has
multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
initiators and targets using different bridges like AXIP2P, AXI2APB.
This driver handles errors due to illegal register accesses reported
by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
"AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
which is the main NOC.
By default, the access issuing initiator is informed about the error
using SError or Data Abort exception unless the ERD (Error Response
Disable) is enabled/set for that initiator. If the ERD is enabled, then
SError or Data Abort is masked and the error is reported with interrupt.
- For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
errors due to illegal accesses from CCPLEX are reported by interrupts.
If ERD is not set, then error is reported by SError.
- For other initiators, the ERD is disabled. So, the access issuing
initiator is informed about the illegal access by Data Abort exception.
In addition, an interrupt is also generated to CCPLEX. These initiators
include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
engine) etc which can initiate transactions.
The driver prints relevant debug information like Error Code, Error
Description, Master, Address, AXI ID, Cache, Protection, Security Group
etc on receiving error notification.
properties:
$nodename:
pattern: "^[a-z]+-noc@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra194-cbb-noc
- nvidia,tegra194-aon-noc
- nvidia,tegra194-bpmp-noc
- nvidia,tegra194-rce-noc
- nvidia,tegra194-sce-noc
reg:
maxItems: 1
interrupts:
description:
CCPLEX receives secure or nonsecure interrupt depending on error type.
A secure interrupt is received for SEC(firewall) & SLV errors and a
non-secure interrupt is received for TMO & DEC errors.
items:
- description: non-secure interrupt
- description: secure interrupt
nvidia,axi2apb:
$ref: '/schemas/types.yaml#/definitions/phandle'
description:
Specifies the node having all axi2apb bridges which need to be checked
for any error logged in their status register.
nvidia,apbmisc:
$ref: '/schemas/types.yaml#/definitions/phandle'
description:
Specifies the apbmisc node which need to be used for reading the ERD
register.
additionalProperties: false
required:
- compatible
- reg
- interrupts
- nvidia,apbmisc
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
cbb-noc@2300000 {
compatible = "nvidia,tegra194-cbb-noc";
reg = <0x02300000 0x1000>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
nvidia,axi2apb = <&axi2apb>;
nvidia,apbmisc = <&apbmisc>;
};

2
sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -208,7 +208,7 @@ properties:
"^[a-z0-9]+$":
type: object
patternProperties:
properties:
clocks:
minItems: 1
maxItems: 8

74
sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra234-cbb.yaml Normal file
View File

@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: NVIDIA Tegra CBB 2.0 bindings
maintainers:
- Sumit Gupta <sumitg@nvidia.com>
description: |+
The Control Backbone (CBB) is comprised of the physical path from an
initiator to a target's register configuration space. CBB 2.0 consists
of multiple sub-blocks connected to each other to create a topology.
The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
"CBB central fabric".
In CBB 2.0, each initiator which can issue transactions connects to a
Root Master Node (MN) before it connects to any other element of the
fabric. Each Root MN contains a Error Monitor (EM) which detects and
logs error. Interrupts from various EM blocks are collated by Error
Notifier (EN) which is per fabric and presents a single interrupt from
fabric to the SoC interrupt controller.
The driver handles errors from CBB due to illegal register accesses
and prints debug information about failed transaction on receiving
the interrupt from EN. Debug information includes Error Code, Error
Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
Security Group etc on receiving error notification.
If the Error Response Disable (ERD) is set/enabled for an initiator,
then SError or Data abort exception error response is masked and an
interrupt is used for reporting errors due to illegal accesses from
that initiator. The value returned on read failures is '0xFFFFFFFF'
for compatibility with PCIE.
properties:
$nodename:
pattern: "^[a-z]+-fabric@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra234-aon-fabric
- nvidia,tegra234-bpmp-fabric
- nvidia,tegra234-cbb-fabric
- nvidia,tegra234-dce-fabric
- nvidia,tegra234-rce-fabric
- nvidia,tegra234-sce-fabric
reg:
maxItems: 1
interrupts:
items:
- description: secure interrupt from error notifier
additionalProperties: false
required:
- compatible
- reg
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
cbb-fabric@1300000 {
compatible = "nvidia,tegra234-cbb-fabric";
reg = <0x13a00000 0x400000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};

10
sys/contrib/device-tree/Bindings/arm/vexpress-sysreg.yaml
View File

@ -29,6 +29,13 @@ properties:
ranges: true
gpio-controller:
deprecated: true
"#gpio-cells":
deprecated: true
const: 2
additionalProperties: false
patternProperties:
@ -67,8 +74,7 @@ patternProperties:
required:
- compatible
- "#address-cells"
- "#size-cells"
- reg
examples:
- |

189
sys/contrib/device-tree/Bindings/ata/ceva,ahci-1v84.yaml Normal file
View File

@ -0,0 +1,189 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some
special extensions to add functionality, is a high-performance dual-port
SATA host controller with an AHCI compliant command layer which supports
advanced features such as native command queuing and frame information
structure (FIS) based switching for systems employing port multipliers.
properties:
compatible:
const: ceva,ahci-1v84
reg:
maxItems: 1
clocks:
maxItems: 1
dma-coherent: true
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
ceva,p0-cominit-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMINIT parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
items:
- description: CINMP - COMINIT Negate Minimum Period.
- description: CIBGN - COMINIT Burst Gap Nominal.
- description: CIBGMX - COMINIT Burst Gap Maximum.
- description: CIBGMN - COMINIT Burst Gap Minimum.
ceva,p0-comwake-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMWAKE parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
items:
- description: CWBGMN - COMWAKE Burst Gap Minimum.
- description: CWBGMX - COMWAKE Burst Gap Maximum.
- description: CWBGN - COMWAKE Burst Gap Nominal.
- description: CWNMP - COMWAKE Negate Minimum Period.
ceva,p0-burst-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
Burst timing value for COM parameter for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
items:
- description: BMX - COM Burst Maximum.
- description: BNM - COM Burst Nominal.
- description: SFD - Signal Failure Detection value.
- description: PTST - Partial to Slumber timer value.
ceva,p0-retry-params:
$ref: /schemas/types.yaml#/definitions/uint16-array
description: |
Retry interval timing value for port 0.
The fields for the above parameter must be as shown below:-
ceva,p0-retry-params = /bits/ 16 <RIT RCT>;
items:
- description: RIT - Retry Interval Timer.
- description: RCT - Rate Change Timer.
ceva,p1-cominit-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMINIT parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
items:
- description: CINMP - COMINIT Negate Minimum Period.
- description: CIBGN - COMINIT Burst Gap Nominal.
- description: CIBGMX - COMINIT Burst Gap Maximum.
- description: CIBGMN - COMINIT Burst Gap Minimum.
ceva,p1-comwake-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
OOB timing value for COMWAKE parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
items:
- description: CWBGMN - COMWAKE Burst Gap Minimum.
- description: CWBGMX - COMWAKE Burst Gap Maximum.
- description: CWBGN - COMWAKE Burst Gap Nominal.
- description: CWNMP - COMWAKE Negate Minimum Period.
ceva,p1-burst-params:
$ref: /schemas/types.yaml#/definitions/uint8-array
description: |
Burst timing value for COM parameter for port 1.
The fields for the above parameter must be as shown below:-
ceva,p1-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
items:
- description: BMX - COM Burst Maximum.
- description: BNM - COM Burst Nominal.
- description: SFD - Signal Failure Detection value.
- description: PTST - Partial to Slumber timer value.
ceva,p1-retry-params:
$ref: /schemas/types.yaml#/definitions/uint16-array
description: |
Retry interval timing value for port 1.
The fields for the above parameter must be as shown below:-
ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
items:
- description: RIT - Retry Interval Timer.
- description: RCT - Rate Change Timer.
ceva,broken-gen2:
$ref: /schemas/types.yaml#/definitions/flag
description: |
limit to gen1 speed instead of gen2.
phys:
maxItems: 1
phy-names:
items:
- const: sata-phy
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- interrupts
- ceva,p0-cominit-params
- ceva,p0-comwake-params
- ceva,p0-burst-params
- ceva,p0-retry-params
- ceva,p1-cominit-params
- ceva,p1-comwake-params
- ceva,p1-burst-params
- ceva,p1-retry-params
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
#include <dt-bindings/phy/phy.h>
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
reg = <0xfd0c0000 0x200>;
interrupt-parent = <&gic>;
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk SATA_REF>;
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
};

25
sys/contrib/device-tree/Bindings/bus/qcom,ssc-block-bus.yaml
View File

@ -28,11 +28,9 @@ properties:
- const: qcom,ssc-block-bus
reg:
description: |
Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1
registers
minItems: 2
maxItems: 2
items:
- description: SSCAON_CONFIG0 registers
- description: SSCAON_CONFIG1 registers
reg-names:
items:
@ -48,7 +46,6 @@ properties:
ranges: true
clocks:
minItems: 6
maxItems: 6
clock-names:
@ -61,9 +58,9 @@ properties:
- const: ssc_ahbs
power-domains:
description: Power domain phandles for the ssc_cx and ssc_mx power domains
minItems: 2
maxItems: 2
items:
- description: CX power domain
- description: MX power domain
power-domain-names:
items:
@ -71,11 +68,11 @@ properties:
- const: ssc_mx
resets:
description: |
Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the
branch control register associated with the ssc_xo and ssc_ahbs clocks)
minItems: 2
maxItems: 2
items:
- description: Main reset
- description:
SSC Branch Control Register reset (associated with the ssc_xo and
ssc_ahbs clocks)
reset-names:
items:

15
sys/contrib/device-tree/Bindings/chrome/google,cros-ec-typec.yaml
View File

@ -20,13 +20,24 @@ properties:
compatible:
const: google,cros-ec-typec
connector:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^connector@[0-9a-f]+$':
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
required:
- compatible
additionalProperties: true #fixme
additionalProperties: false
examples:
- |+

35
sys/contrib/device-tree/Bindings/chrome/google,cros-kbd-led-backlight.yaml Normal file
View File

@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ChromeOS keyboard backlight LED driver.
maintainers:
- Tzung-Bi Shih <tzungbi@kernel.org>
properties:
compatible:
const: google,cros-kbd-led-backlight
required:
- compatible
additionalProperties: false
examples:
- |
spi0 {
#address-cells = <1>;
#size-cells = <0>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
kbd-led-backlight {
compatible = "google,cros-kbd-led-backlight";
};
};
};

3
sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
View File

@ -28,6 +28,9 @@ properties:
- items:
- const: allwinner,sun8i-r40-de2-clk
- const: allwinner,sun8i-h3-de2-clk
- items:
- const: allwinner,sun20i-d1-de2-clk
- const: allwinner,sun50i-h5-de2-clk
reg:
maxItems: 1

1
sys/contrib/device-tree/Bindings/clock/fixed-factor-clock.yaml
View File

@ -13,7 +13,6 @@ maintainers:
properties:
compatible:
enum:
- allwinner,sun4i-a10-pll3-2x-clk
- fixed-factor-clock
"#clock-cells":

43
sys/contrib/device-tree/Bindings/clock/fsl,scu-clk.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol
maintainers:
- Abel Vesa <abel.vesa@nxp.com>
description: i.MX SCU Client Device Node
Client nodes are maintained as children of the relevant IMX-SCU device node.
This binding uses the common clock binding.
(Documentation/devicetree/bindings/clock/clock-bindings.txt)
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from
include/dt-bindings/clock/imx8qxp-clock.h
properties:
compatible:
items:
- enum:
- fsl,imx8dxl-clk
- fsl,imx8qm-clk
- fsl,imx8qxp-clk
- const: fsl,scu-clk
'#clock-cells':
const: 2
required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <2>;
};

49
sys/contrib/device-tree/Bindings/clock/nuvoton,npcm845-clk.yaml Normal file
View File

@ -0,0 +1,49 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NPCM8XX Clock Controller Binding
maintainers:
- Tomer Maimon <tmaimon77@gmail.com>
description: |
Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.
properties:
compatible:
enum:
- nuvoton,npcm845-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
description:
See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
list of NPCM8XX clock IDs.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
ahb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk";
reg = <0x0 0xf0801000 0x0 0x1000>;
#clock-cells = <1>;
};
};
...

6
sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@ -4,18 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8150 and SM8250.
power domains on SM8150/SM8250/SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:
@ -23,6 +24,7 @@ properties:
- qcom,sc8180x-dispcc
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc
- qcom,sm8350-dispcc
clocks:
items:

40
sys/contrib/device-tree/Bindings/clock/qcom,gcc-apq8064.yaml
View File

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
allOf:
- $ref: qcom,gcc.yaml#
@ -23,11 +23,25 @@ description: |
properties:
compatible:
const: qcom,gcc-apq8064
oneOf:
- items:
- enum:
- qcom,gcc-apq8064
- qcom,gcc-msm8960
- const: syscon
- enum:
- qcom,gcc-apq8064
- qcom,gcc-msm8960
deprecated: true
thermal-sensor:
description: child tsens device
$ref: /schemas/thermal/qcom-tsens.yaml#
nvmem-cells:
minItems: 1
maxItems: 2
deprecated: true
description:
Qualcomm TSENS (thermal sensor device) on some devices can
be part of GCC and hence the TSENS properties can also be part
@ -37,31 +51,39 @@ properties:
nvmem-cell-names:
minItems: 1
deprecated: true
items:
- const: calib
- const: calib_backup
'#thermal-sensor-cells':
const: 1
deprecated: true
required:
- compatible
- nvmem-cells
- nvmem-cell-names
- '#thermal-sensor-cells'
unevaluatedProperties: false
examples:
- |
clock-controller@900000 {
compatible = "qcom,gcc-apq8064";
compatible = "qcom,gcc-apq8064", "syscon";
reg = <0x00900000 0x4000>;
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
#thermal-sensor-cells = <1>;
thermal-sensor {
compatible = "qcom,msm8960-tsens";
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <0 178 4>;
interrupt-names = "uplow";
#qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
};
...

5
sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml
View File

@ -24,6 +24,9 @@ properties:
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
'#reset-cells':
const: 1
@ -38,6 +41,7 @@ required:
- compatible
- reg
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
@ -48,6 +52,7 @@ examples:
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

16
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml
View File

@ -22,16 +22,32 @@ properties:
const: qcom,gcc-msm8996
clocks:
minItems: 3
items:
- description: XO source
- description: Second XO source
- description: Sleep clock source
- description: PCIe 0 PIPE clock (optional)
- description: PCIe 1 PIPE clock (optional)
- description: PCIe 2 PIPE clock (optional)
- description: USB3 PIPE clock (optional)
- description: UFS RX symbol 0 clock (optional)
- description: UFS RX symbol 1 clock (optional)
- description: UFS TX symbol 0 clock (optional)
clock-names:
minItems: 3
items:
- const: cxo
- const: cxo2
- const: sleep_clk
- const: pcie_0_pipe_clk_src
- const: pcie_1_pipe_clk_src
- const: pcie_2_pipe_clk_src
- const: usb3_phy_pipe_clk_src
- const: ufs_rx_symbol_0_clk_src
- const: ufs_rx_symbol_1_clk_src
- const: ufs_tx_symbol_0_clk_src
'#clock-cells':
const: 1

5
sys/contrib/device-tree/Bindings/clock/qcom,gcc-other.yaml
View File

@ -44,7 +44,6 @@ properties:
- qcom,gcc-msm8916
- qcom,gcc-msm8939
- qcom,gcc-msm8953
- qcom,gcc-msm8960
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
@ -58,10 +57,10 @@ required:
unevaluatedProperties: false
examples:
# Example for GCC for MSM8960:
# Example for GCC for MSM8974:
- |
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
compatible = "qcom,gcc-msm8974";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;

3
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml
View File

@ -43,6 +43,9 @@ properties:
'#reset-cells':
const: 1
power-domains:
maxItems: 1
'#power-domain-cells':
const: 1

72
sys/contrib/device-tree/Bindings/clock/qcom,gpucc-sm8350.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding
maintainers:
- Robert Foss <robert.foss@linaro.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,gpucc-sm8350.h
properties:
compatible:
enum:
- qcom,sm8350-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d90000 {
compatible = "qcom,sm8350-gpucc";
reg = <0 0x03d90000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

85
sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.yaml
View File

@ -49,15 +49,86 @@ properties:
const: 1
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
const: xo
minItems: 1
maxItems: 2
required:
- compatible
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,rpmcc-apq8060
- qcom,rpmcc-ipq806x
- qcom,rpmcc-msm8660
then:
properties:
clocks:
items:
- description: pxo clock
clock-names:
items:
- const: pxo
- if:
properties:
compatible:
contains:
const: qcom,rpmcc-apq8064
then:
properties:
clocks:
items:
- description: pxo clock
- description: cxo clock
clock-names:
items:
- const: pxo
- const: cxo
- if:
properties:
compatible:
contains:
enum:
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
- qcom,rpmcc-msm8992
- qcom,rpmcc-msm8994
- qcom,rpmcc-msm8996
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
then:
properties:
clocks:
items:
- description: xo clock
clock-names:
items:
- const: xo
additionalProperties: false
examples:
@ -73,3 +144,13 @@ examples:
};
};
};
- |
rpm {
clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&pxo_board>;
clock-names = "pxo";
};
};

80
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml Normal file
View File

@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SM8450.
See also include/dt-bindings/clock/qcom,sm8450-camcc.h
properties:
compatible:
const: qcom,sm8450-camcc
clocks:
items:
- description: Camera AHB clock from GCC
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ade0000 {
compatible = "qcom,sm8450-camcc";
reg = <0xade0000 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

7
sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml
View File

@ -45,10 +45,9 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/r9a0*-cpg.h>
<dt-bindings/clock/r9a0*-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
<dt-bindings/clock/r9a09g011-cpg.h>.
a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
const: 2
'#power-domain-cells':
@ -62,7 +61,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
<dt-bindings/clock/r9a0*-cpg.h>.
const: 1
required:

27
sys/contrib/device-tree/Bindings/clock/samsung,exynos7885-clock.yaml
View File

@ -33,6 +33,7 @@ properties:
enum:
- samsung,exynos7885-cmu-top
- samsung,exynos7885-cmu-core
- samsung,exynos7885-cmu-fsys
- samsung,exynos7885-cmu-peri
clocks:
@ -88,6 +89,32 @@ allOf:
- const: dout_core_cci
- const: dout_core_g3d
- if:
properties:
compatible:
contains:
const: samsung,exynos7885-cmu-fsys
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS bus clock (from CMU_TOP)
- description: MMC_CARD clock (from CMU_TOP)
- description: MMC_EMBD clock (from CMU_TOP)
- description: MMC_SDIO clock (from CMU_TOP)
- description: USB30DRD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_fsys_bus
- const: dout_fsys_mmc_card
- const: dout_fsys_mmc_embd
- const: dout_fsys_mmc_sdio
- const: dout_fsys_usb30drd
- if:
properties:
compatible:

71
sys/contrib/device-tree/Bindings/clock/sprd,ums512-clk.yaml Normal file
View File

@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: UMS512 Soc clock controller
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
compatible:
enum:
- sprd,ums512-apahb-gate
- sprd,ums512-ap-clk
- sprd,ums512-aonapb-clk
- sprd,ums512-pmu-gate
- sprd,ums512-g0-pll
- sprd,ums512-g2-pll
- sprd,ums512-g3-pll
- sprd,ums512-gc-pll
- sprd,ums512-aon-gate
- sprd,ums512-audcpapb-gate
- sprd,ums512-audcpahb-gate
- sprd,ums512-gpu-clk
- sprd,ums512-mm-clk
- sprd,ums512-mm-gate-clk
- sprd,ums512-apapb-gate
"#clock-cells":
const: 1
clocks:
minItems: 1
maxItems: 4
description: |
The input parent clock(s) phandle for the clock, only list
fixed clocks which are declared in devicetree.
clock-names:
minItems: 1
items:
- const: ext-26m
- const: ext-32k
- const: ext-4m
- const: rco-100m
reg:
maxItems: 1
required:
- compatible
- '#clock-cells'
- reg
additionalProperties: false
examples:
- |
ap_clk: clock-controller@20200000 {
compatible = "sprd,ums512-ap-clk";
reg = <0x20200000 0x1000>;
clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
...

1
sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml
View File

@ -78,6 +78,7 @@ if:
contains:
enum:
- st,stm32mp1-rcc-secure
- st,stm32mp13-rcc
then:
properties:
clocks:

2
sys/contrib/device-tree/Bindings/clock/st/st,flexgen.txt
View File

@ -78,7 +78,7 @@ Required properties:
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
outputs).
- clocks : must be set to the parent's phandle. it's could be output clocks of
- clocks : must be set to the parent's phandle. it could be output clocks of
a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
- clock-output-names : List of strings used to name the clock outputs.

52
sys/contrib/device-tree/Bindings/clock/sunplus,sp7021-clkc.yaml Normal file
View File

@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sunplus SP7021 SoC Clock Controller
maintainers:
- Qin Jian <qinjian@cqplus1.com>
properties:
compatible:
const: sunplus,sp7021-clkc
reg:
maxItems: 3
clocks:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
extclk: osc0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "extclk";
};
clkc: clock-controller@9c000004 {
compatible = "sunplus,sp7021-clkc";
reg = <0x9c000004 0x28>,
<0x9c000200 0x44>,
<0x9c000268 0x08>;
clocks = <&extclk>;
#clock-cells = <1>;
};
...

2
sys/contrib/device-tree/Bindings/clock/ti/davinci/pll.txt
View File

@ -15,7 +15,7 @@ Required properties:
- for "ti,da850-pll1", shall be "clksrc"
Optional properties:
- ti,clkmode-square-wave: Indicates that the the board is supplying a square
- ti,clkmode-square-wave: Indicates that the board is supplying a square
wave input on the OSCIN pin instead of using a crystal oscillator.
This property is only valid when compatible = "ti,da850-pll0".

2
sys/contrib/device-tree/Bindings/clock/ti/dra7-atl.txt
View File

@ -6,7 +6,7 @@ functional clock but can be configured to provide different clocks.
ATL can maintain a clock averages to some desired frequency based on the bws/aws
signals - can compensate the drift between the two ws signal.
In order to provide the support for ATL and it's output clocks (which can be used
In order to provide the support for ATL and its output clocks (which can be used
internally within the SoC or external components) two sets of bindings is needed:
Clock tree binding:

152
sys/contrib/device-tree/Bindings/connector/usb-connector.yaml
View File

@ -263,11 +263,11 @@ examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
- |
muic-max77843 {
usb_con1: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
usb_con1: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
# USB-C connector attached to CC controller (s2mm005), HS lines routed
@ -275,34 +275,34 @@ examples:
# DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
- |
ccic: s2mm005 {
usb_con2: connector {
compatible = "usb-c-connector";
label = "USB-C";
usb_con2: connector {
compatible = "usb-c-connector";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&max77865_usbc_hs>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&max77865_usbc_hs>;
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&usbdrd_phy_ss>;
};
};
port@2 {
reg = <2>;
usb_con_sbu: endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&usbdrd_phy_ss>;
};
};
port@2 {
reg = <2>;
usb_con_sbu: endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};
# USB-C connector attached to a typec port controller(ptn5110), which has
@ -310,16 +310,16 @@ examples:
- |
#include <dt-bindings/usb/pd.h>
typec: ptn5110 {
usb_con3: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 12000, 2000)>;
op-sink-microwatt = <10000000>;
};
usb_con3: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 12000, 2000)>;
op-sink-microwatt = <10000000>;
};
};
# USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
@ -332,20 +332,20 @@ examples:
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
@ -354,12 +354,12 @@ examples:
#include <dt-bindings/gpio/gpio.h>
usb {
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
vbus-supply = <&usb_p0_vbus>;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
vbus-supply = <&usb_p0_vbus>;
};
};
# Micro-USB connector with HS lines routed via controller (MUIC) and MHL
@ -367,27 +367,27 @@ examples:
# mobile phone
- |
muic-max77843 {
usb_con4: connector {
compatible = "samsung,usb-connector-11pin", "usb-b-connector";
label = "micro-USB";
type = "micro";
usb_con4: connector {
compatible = "samsung,usb-connector-11pin", "usb-b-connector";
label = "micro-USB";
type = "micro";
ports {
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
muic_to_usb: endpoint {
remote-endpoint = <&usb_to_muic>;
port@0 {
reg = <0>;
muic_to_usb: endpoint {
remote-endpoint = <&usb_to_muic>;
};
};
port@3 {
reg = <3>;
usb_con_mhl: endpoint {
remote-endpoint = <&sii8620_mhl>;
};
};
};
};
port@3 {
reg = <3>;
usb_con_mhl: endpoint {
remote-endpoint = <&sii8620_mhl>;
};
};
};
};
};

1
sys/contrib/device-tree/Bindings/cpufreq/cpufreq-qcom-hw.yaml
View File

@ -25,6 +25,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
- qcom,sm6375-cpufreq-epss
- qcom,sm8250-cpufreq-epss
- const: qcom,cpufreq-epss

11
sys/contrib/device-tree/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
View File

@ -22,6 +22,13 @@ select:
compatible:
contains:
enum:
- qcom,apq8064
- qcom,apq8096
- qcom,ipq8064
- qcom,msm8939
- qcom,msm8960
- qcom,msm8974
- qcom,msm8996
- qcom,qcs404
required:
- compatible
@ -63,8 +70,8 @@ additionalProperties: true
examples:
- |
/ {
model = "Qualcomm Technologies, Inc. QCS404";
compatible = "qcom,qcs404";
model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
#address-cells = <2>;
#size-cells = <2>;

4
sys/contrib/device-tree/Bindings/display/allwinner,sun4i-a10-tcon.yaml
View File

@ -233,6 +233,7 @@ allOf:
- allwinner,sun8i-a83t-tcon-lcd
- allwinner,sun8i-v3s-tcon
- allwinner,sun9i-a80-tcon-lcd
- allwinner,sun20i-d1-tcon-lcd
then:
properties:
@ -252,6 +253,7 @@ allOf:
- allwinner,sun8i-a83t-tcon-tv
- allwinner,sun8i-r40-tcon-tv
- allwinner,sun9i-a80-tcon-tv
- allwinner,sun20i-d1-tcon-tv
then:
properties:
@ -278,6 +280,7 @@ allOf:
- allwinner,sun9i-a80-tcon-lcd
- allwinner,sun4i-a10-tcon
- allwinner,sun8i-a83t-tcon-lcd
- allwinner,sun20i-d1-tcon-lcd
then:
required:
@ -294,6 +297,7 @@ allOf:
- allwinner,sun8i-a23-tcon
- allwinner,sun8i-a33-tcon
- allwinner,sun8i-a83t-tcon-lcd
- allwinner,sun20i-d1-tcon-lcd
then:
properties:

2
sys/contrib/device-tree/Bindings/display/amlogic,meson-dw-hdmi.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Neil Armstrong <neil.armstrong@linaro.org>
allOf:
- $ref: /schemas/sound/name-prefix.yaml#

2
sys/contrib/device-tree/Bindings/display/amlogic,meson-vpu.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson Display Controller
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Amlogic Meson Display controller is composed of several components

15
sys/contrib/device-tree/Bindings/display/arm,pl11x.yaml
View File

@ -159,25 +159,12 @@ examples:
};
panel {
compatible = "arm,rtsm-display", "panel-dpi";
power-supply = <&vcc_supply>;
compatible = "arm,rtsm-display";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
...

1
sys/contrib/device-tree/Bindings/display/atmel,lcdc.txt
View File

@ -9,7 +9,6 @@ Required properties:
"atmel,at91sam9g45-lcdc" ,
"atmel,at91sam9g45es-lcdc" ,
"atmel,at91sam9rl-lcdc" ,
"atmel,at32ap-lcdc"
- reg : Should contain 1 register ranges(address and length).
Can contain an additional register range(address and length)
for fixed framebuffer memory. Useful for dedicated memories.

19
sys/contrib/device-tree/Bindings/display/bridge/analogix,anx7625.yaml
View File

@ -94,7 +94,22 @@ properties:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Video port for MIPI DSI input.
MIPI DSI/DPI input.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
type: object
additionalProperties: false
properties:
remote-endpoint: true
bus-type:
enum: [7]
default: 1
data-lanes: true
port@1:
$ref: /schemas/graph.yaml#/properties/port
@ -143,6 +158,8 @@ examples:
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&mipi_dsi>;
bus-type = <7>;
data-lanes = <0 1 2 3>;
};
};

2
sys/contrib/device-tree/Bindings/display/bridge/analogix,anx7814.yaml
View File

@ -8,7 +8,7 @@ title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
maintainers:
- Andrzej Hajda <andrzej.hajda@intel.com>
- Neil Armstrong <narmstrong@baylibre.com>
- Neil Armstrong <neil.armstrong@linaro.org>
- Robert Foss <robert.foss@linaro.org>
properties:

173
sys/contrib/device-tree/Bindings/display/bridge/fsl,imx8qxp-ldb.yaml Normal file
View File

@ -0,0 +1,173 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp LVDS Display Bridge
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
The CSR module, as a system controller, contains the LDB's configuration
registers.
For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
format and can map the input to VESA or JEIDA standards. The two channels
cannot be used simultaneously, that is to say, the user should pick one of
them to use. Two LDB channels from two LDB instances can work together in
LDB split mode to support a dual link LVDS display. The channel indexes
have to be different. Channel0 outputs odd pixels and channel1 outputs
even pixels.
For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
input color format. The two channels can be used simultaneously, either
in dual mode or split mode. In dual mode, the two channels output identical
data. In split mode, channel0 outputs odd pixels and channel1 outputs even
pixels.
A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
consistency, this binding calls it LDB.
properties:
compatible:
enum:
- fsl,imx8qm-ldb
- fsl,imx8qxp-ldb
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
items:
- description: pixel clock
- description: bypass clock
clock-names:
items:
- const: pixel
- const: bypass
power-domains:
maxItems: 1
fsl,companion-ldb:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
A phandle which points to companion LDB which is used in LDB split mode.
patternProperties:
"^channel@[0-1]$":
type: object
description: Represents a channel of LDB.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
description: The channel index.
enum: [ 0, 1 ]
phys:
description: A phandle to the phy module representing the LVDS PHY.
maxItems: 1
phy-names:
const: lvds_phy
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input port of the channel.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output port of the channel.
required:
- "#address-cells"
- "#size-cells"
- reg
- phys
- phy-names
additionalProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- power-domains
- channel@0
- channel@1
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-ldb
then:
properties:
fsl,companion-ldb: false
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
ldb {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8qxp-ldb";
clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
clock-names = "pixel", "bypass";
power-domains = <&pd IMX_SC_R_LVDS_0>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
};
};
};
channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&mipi_lvds_0_phy>;
phy-names = "lvds_phy";
port@0 {
reg = <0>;
mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
};
};
};
};

144
sys/contrib/device-tree/Bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml Normal file
View File

@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Pixel Combiner
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
single display controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
either one screen, two screens, or virtual screens. The pixel combiner is
also responsible for generating some of the control signals for the pixel link
output channel.
properties:
compatible:
enum:
- fsl,imx8qm-pixel-combiner
- fsl,imx8qxp-pixel-combiner
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: apb
power-domains:
maxItems: 1
patternProperties:
"^channel@[0-1]$":
type: object
description: Represents a display stream of pixel combiner.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
description: The display stream index.
enum: [ 0, 1 ]
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input endpoint of the display stream.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the display stream.
required:
- "#address-cells"
- "#size-cells"
- reg
- port@0
- port@1
additionalProperties: false
required:
- compatible
- "#address-cells"
- "#size-cells"
- reg
- clocks
- clock-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
pixel-combiner@56020000 {
compatible = "fsl,imx8qxp-pixel-combiner";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x56020000 0x10000>;
clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
clock-names = "apb";
power-domains = <&pd IMX_SC_R_DC_0>;
channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
};
};
port@1 {
reg = <1>;
dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
};
};
};
channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
port@0 {
reg = <0>;
dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
};
};
port@1 {
reg = <1>;
dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
};
};
};
};

144
sys/contrib/device-tree/Bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml Normal file
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@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Display Pixel Link
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
asynchronous linkage between pixel sources(display controller or
camera module) and pixel consumers(imaging or displays).
It consists of two distinct functions, a pixel transfer function and a
control interface. Multiple pixel channels can exist per one control channel.
This binding documentation is only for pixel links whose pixel sources are
display controllers.
The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
firmware.
properties:
compatible:
enum:
- fsl,imx8qm-dc-pixel-link
- fsl,imx8qxp-dc-pixel-link
fsl,dc-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller index that the pixel link
connects to.
fsl,dc-stream-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller stream index that the pixel
link connects to.
enum: [0, 1]
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link input port node from upstream video source.
patternProperties:
"^port@[1-4]$":
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link output port node to downstream bridge.
required:
- port@0
- port@1
- port@2
- port@3
- port@4
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qxp-dc-pixel-link
then:
properties:
fsl,dc-id:
const: 0
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-dc-pixel-link
then:
properties:
fsl,dc-id:
enum: [0, 1]
required:
- compatible
- fsl,dc-id
- fsl,dc-stream-id
- ports
additionalProperties: false
examples:
- |
dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";
fsl,dc-id = /bits/ 8 <0>;
fsl,dc-stream-id = /bits/ 8 <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* from dc0 pixel combiner channel0 */
port@0 {
reg = <0>;
dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
};
};
/* to PXL2DPIs in MIPI/LVDS combo subsystems */
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
};
dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
};
};
/* unused */
port@2 {
reg = <2>;
};
/* unused */
port@3 {
reg = <3>;
};
/* to imaging subsystem */
port@4 {
reg = <4>;
};
};
};

108
sys/contrib/device-tree/Bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml Normal file
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@ -0,0 +1,108 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
interfaces the pixel link 36-bit data output and the DSI controller’s
MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
used in LVDS mode, to remap the pixel color codings between those modules.
This module is purely combinatorial.
The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
The CSR module, as a system controller, contains the PXL2DPI's configuration
register.
properties:
compatible:
const: fsl,imx8qxp-pxl2dpi
fsl,sc-resource:
$ref: /schemas/types.yaml#/definitions/uint32
description: The SCU resource ID associated with this PXL2DPI instance.
power-domains:
maxItems: 1
fsl,companion-pxl2dpi:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
A phandle which points to companion PXL2DPI which is used by downstream
LVDS Display Bridge(LDB) in split mode.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The PXL2DPI input port node from pixel link.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: The PXL2DPI output port node to downstream bridge.
required:
- port@0
- port@1
required:
- compatible
- fsl,sc-resource
- power-domains
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
pxl2dpi {
compatible = "fsl,imx8qxp-pxl2dpi";
fsl,sc-resource = <IMX_SC_R_MIPI_0>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
reg = <0>;
remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
reg = <1>;
remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
};
mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
};
};
};
};

16
sys/contrib/device-tree/Bindings/display/bridge/fsl,ldb.yaml
View File

@ -24,6 +24,15 @@ properties:
clock-names:
const: ldb
reg:
minItems: 2
maxItems: 2
reg-names:
items:
- const: ldb
- const: lvds
ports:
$ref: /schemas/graph.yaml#/properties/ports
@ -56,10 +65,15 @@ examples:
#include <dt-bindings/clock/imx8mp-clock.h>
blk-ctrl {
bridge {
#address-cells = <1>;
#size-cells = <1>;
bridge@5c {
compatible = "fsl,imx8mp-ldb";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
ports {
#address-cells = <1>;

1
sys/contrib/device-tree/Bindings/display/bridge/ingenic,jz4780-hdmi.yaml
View File

@ -55,7 +55,6 @@ examples:
compatible = "ingenic,jz4780-dw-hdmi";
reg = <0x10180000 0x8000>;
reg-io-width = <4>;
ddc-i2c-bus = <&i2c4>;
interrupt-parent = <&intc>;
interrupts = <3>;
clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;

2
sys/contrib/device-tree/Bindings/display/bridge/ite,it66121.yaml
View File

@ -8,7 +8,7 @@ title: ITE it66121 HDMI bridge Device Tree Bindings
maintainers:
- Phong LE <ple@baylibre.com>
- Neil Armstrong <narmstrong@baylibre.com>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The IT66121 is a high-performance and low-power single channel HDMI

131
sys/contrib/device-tree/Bindings/display/bridge/sil,sii9022.yaml Normal file
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@ -0,0 +1,131 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Image sii902x HDMI bridge
maintainers:
- Boris Brezillon <bbrezillon@kernel.org>
properties:
compatible:
oneOf:
- items:
- enum:
- sil,sii9022-cpi # CEC Programming Interface
- sil,sii9022-tpi # Transmitter Programming Interface
- const: sil,sii9022
- const: sil,sii9022
reg:
maxItems: 1
interrupts:
maxItems: 1
description: Interrupt line used to inform the host about hotplug events.
reset-gpios:
maxItems: 1
iovcc-supply:
description: I/O Supply Voltage (1.8V or 3.3V)
cvcc12-supply:
description: Digital Core Supply Voltage (1.2V)
'#sound-dai-cells':
enum: [ 0, 1 ]
description: |
<0> if only I2S or S/PDIF pin is wired,
<1> if both are wired.
HDMI audio is configured only if this property is found.
If HDMI audio is configured, the sii902x device becomes an I2S and/or
S/PDIF audio codec component (e.g. a digital audio sink), that can be
used in configuring full audio devices with simple-card or
audio-graph-card bindings. See their binding documents on how to describe
the way the
sii902x device is connected to the rest of the audio system:
Documentation/devicetree/bindings/sound/simple-card.yaml
Documentation/devicetree/bindings/sound/audio-graph-card.yaml
Note: In case of the audio-graph-card binding the used port index should
be 3.
sil,i2s-data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 4
uniqueItems: true
items:
enum: [ 0, 1, 2, 3 ]
description:
Each integer indicates which I2S pin is connected to which audio FIFO.
The first integer selects the I2S audio pin for the first audio FIFO#0
(HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be
connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
default value is <0>, describing SD0 pin being routed to HDMI audio
FIFO#0.
clocks:
maxItems: 1
description: MCLK input. MCLK can be used to produce HDMI audio CTS values.
clock-names:
const: mclk
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Parallel RGB input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI output port
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: Sound input port
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi-bridge@39 {
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&pioA 1 0>;
iovcc-supply = <&v3v3_hdmi>;
cvcc12-supply = <&v1v2_hdmi>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 1 2 >;
clocks = <&mclk>;
clock-names = "mclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dc_out>;
};
};
};
};
};

117
sys/contrib/device-tree/Bindings/display/bridge/ti,dlpc3433.yaml Normal file
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@ -0,0 +1,117 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DLPC3433 MIPI DSI to DMD bridge
maintainers:
- Jagan Teki <jagan@amarulasolutions.com>
- Christopher Vollo <chris@renewoutreach.org>
description: |
TI DLPC3433 is a MIPI DSI based display controller bridge
for processing high resolution DMD based projectors.
It has a flexible configuration of MIPI DSI and DPI signal
input that produces a DMD output in RGB565, RGB666, RGB888
formats.
It supports upto 720p resolution with 60 and 120 Hz refresh
rates.
properties:
compatible:
const: ti,dlpc3433
reg:
enum:
- 0x1b
- 0x1d
enable-gpios:
description: PROJ_ON pin, chip powers up PROJ_ON is high.
vcc_intf-supply:
description: A 1.8V/3.3V supply that power the Host I/O.
vcc_flsh-supply:
description: A 1.8V/3.3V supply that power the Flash I/O.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Video port for MIPI DSI input.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Video port for DMD output.
required:
- port@0
- port@1
required:
- compatible
- reg
- enable-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c1 {
#address-cells = <1>;
#size-cells = <0>;
bridge@1b {
compatible = "ti,dlpc3433";
reg = <0x1b>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi: endpoint {
remote-endpoint = <&dsi_out_bridge>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
bridge_out_panel: endpoint {
remote-endpoint = <&panel_out_bridge>;
};
};
};
};
};

1
sys/contrib/device-tree/Bindings/display/fsl,lcdif.yaml
View File

@ -20,6 +20,7 @@ properties:
- fsl,imx23-lcdif
- fsl,imx28-lcdif
- fsl,imx6sx-lcdif
- fsl,imx8mp-lcdif
- items:
- enum:
- fsl,imx6sl-lcdif

11
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dpi.yaml
View File

@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: mediatek DPI Controller Device Tree Bindings
title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu <ck.hu@mediatek.com>
- Jitao shi <jitao.shi@mediatek.com>
description: |
The Mediatek DPI function block is a sink of the display subsystem and
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
output bus.
The MediaTek DPI and DP_INTF function blocks are a sink of the display
subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
parallel output bus.
properties:
compatible:
@ -24,6 +24,7 @@ properties:
- mediatek,mt8183-dpi
- mediatek,mt8186-dpi
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
reg:
maxItems: 1
@ -55,7 +56,7 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port should be connected to the input port of an
attached HDMI or LVDS encoder chip.
attached HDMI, LVDS or DisplayPort encoder chip.
required:
- compatible

116
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.yaml Normal file
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@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek DSI Controller Device Tree Bindings
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
- Jitao Shi <jitao.shi@mediatek.com>
- Xinlei Lee <xinlei.lee@mediatek.com>
description: |
The MediaTek DSI function block is a sink of the display subsystem and can
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
channel output.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
properties:
compatible:
enum:
- mediatek,mt2701-dsi
- mediatek,mt7623-dsi
- mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
- mediatek,mt8186-dsi
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: Engine Clock
- description: Digital Clock
- description: HS Clock
clock-names:
items:
- const: engine
- const: digital
- const: hs
resets:
maxItems: 1
phys:
maxItems: 1
phy-names:
items:
- const: dphy
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port should be connected to the input
port of an attached DSI panel or DSI-to-eDP encoder chip.
required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt8183-resets.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DSI0_MM>,
<&mmsys CLK_MM_DSI0_IF>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
...

88
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,mdp-rdma.yaml Normal file
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@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MDP RDMA
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description:
The MediaTek MDP RDMA stands for Read Direct Memory Access.
It provides real time data to the back-end panel driver, such as DSI,
DPI and DP_INTF.
It contains one line buffer to store the sufficient pixel data.
RDMA device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
properties:
compatible:
const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: RDMA Clock
iommus:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- iommus
- mediatek,gce-client-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
rdma@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
};
};

8
sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: MSM Display Port Controller
maintainers:
- Kuogee Hsieh <khsieh@codeaurora.org>
- Kuogee Hsieh <quic_khsieh@quicinc.com>
description: |
Device tree bindings for DisplayPort host controller for MSM targets
@ -76,6 +76,9 @@ properties:
"#sound-dai-cells":
const: 0
vdda-0p9-supply: true
vdda-1p2-supply: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
@ -137,6 +140,9 @@ examples:
power-domains = <&rpmhpd SC7180_CX>;
vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
ports {
#address-cells = <1>;
#size-cells = <0>;

232
sys/contrib/device-tree/Bindings/display/msm/hdmi.yaml Normal file
View File

@ -0,0 +1,232 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Adreno/Snapdragon HDMI output
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
enum:
- qcom,hdmi-tx-8084
- qcom,hdmi-tx-8660
- qcom,hdmi-tx-8960
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
reg:
minItems: 1
maxItems: 3
reg-names:
minItems: 1
items:
- const: core_physical
- const: qfprom_physical
- const: hdcp_physical
interrupts:
maxItems: 1
phys:
maxItems: 1
phy-names:
enum:
- hdmi_phy
- hdmi-phy
deprecated: true
core-vdda-supply:
description: phandle to VDDA supply regulator
hdmi-mux-supply:
description: phandle to mux regulator
deprecated: true
core-vcc-supply:
description: phandle to VCC supply regulator
hpd-gpios:
maxItems: 1
description: hpd pin
qcom,hdmi-tx-mux-en-gpios:
maxItems: 1
deprecated: true
description: HDMI mux enable pin
qcom,hdmi-tx-mux-sel-gpios:
maxItems: 1
deprecated: true
description: HDMI mux select pin
qcom,hdmi-tx-mux-lpm-gpios:
maxItems: 1
deprecated: true
description: HDMI mux lpm pin
'#sound-dai-cells':
const: 1
ports:
type: object
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: |
Input endpoints of the controller.
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
description: |
Output endpoints of the controller.
required:
- port@0
required:
- compatible
- clocks
- clock-names
- reg
- reg-names
- interrupts
- phys
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-tx-8960
- qcom,hdmi-tx-8660
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: core
- const: master_iface
- const: slave_iface
core-vcc-supplies: false
- if:
properties:
compatible:
contains:
enum:
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8084
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
then:
properties:
clocks:
minItems: 5
clock-names:
items:
- const: mdp_core
- const: iface
- const: core
- const: alt_iface
- const: extp
hdmi-mux-supplies: false
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi: hdmi@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg-names = "core_physical";
reg = <0x04a00000 0x2f0>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core",
"master_iface",
"slave_iface";
clocks = <&clk 61>,
<&clk 72>,
<&clk 98>;
hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
hdmi-mux-supply = <&ext_3p3v>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
phys = <&hdmi_phy>;
};
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names = "mdp_core",
"iface",
"core",
"alt_iface",
"extp";
phys = <&hdmi_phy>;
#sound-dai-cells = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
core-vdda-supply = <&vreg_l12a_1p8>;
core-vcc-supply = <&vreg_s4a_1p8>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
};
...

27
sys/contrib/device-tree/Bindings/display/panel/arm,rtsm-display.yaml Normal file
View File

@ -0,0 +1,27 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/arm,rtsm-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm RTSM Virtual Platforms Display
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
const: arm,rtsm-display
port: true
required:
- compatible
- port
additionalProperties: false
...

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