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Add a new disassembler that improves over the previous disassembler

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in that it provides an abstract (intermediate) representation for
instructions. This significantly improves working with instructions
such as emulation of instructions that are not implemented by the
hardware (e.g. long branch) or enhancing implemented instructions
(e.g. handling of misaligned memory accesses). Not to mention that
it's much easier to print instructions.

Functions are included that provide a textual representation for
opcodes, completers and operands.

The disassembler supports all ia64 instructions defined by revision
2.1 of the SDM (Oct 2002).
This commit is contained in:
Marcel Moolenaar 2003-10-23 06:01:52 +00:00
parent 042093540c
commit b9eabb421b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=121404
5 changed files with 5915 additions and 0 deletions
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/*
* Copyright (c) 2000-2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DISASM_H_
#define _DISASM_H_
#ifndef _DISASM_INT_H_
#define ASM_ADDITIONAL_OPCODES ASM_OP_NUMBER_OF_OPCODES
#endif
/* Application registers. */
#define AR_K0 0
#define AR_K1 1
#define AR_K2 2
#define AR_K3 3
#define AR_K4 4
#define AR_K5 5
#define AR_K6 6
#define AR_K7 7
#define AR_RSC 16
#define AR_BSP 17
#define AR_BSPSTORE 18
#define AR_RNAT 19
#define AR_FCR 21
#define AR_EFLAG 24
#define AR_CSD 25
#define AR_SSD 26
#define AR_CFLG 27
#define AR_FSR 28
#define AR_FIR 29
#define AR_FDR 30
#define AR_CCV 32
#define AR_UNAT 36
#define AR_FPSR 40
#define AR_ITC 44
#define AR_PFS 64
#define AR_LC 65
#define AR_EC 66
/* Control registers. */
#define CR_DCR 0
#define CR_ITM 1
#define CR_IVA 2
#define CR_PTA 8
#define CR_IPSR 16
#define CR_ISR 17
#define CR_IIP 19
#define CR_IFA 20
#define CR_ITIR 21
#define CR_IIPA 22
#define CR_IFS 23
#define CR_IIM 24
#define CR_IHA 25
#define CR_LID 64
#define CR_IVR 65
#define CR_TPR 66
#define CR_EOI 67
#define CR_IRR0 68
#define CR_IRR1 69
#define CR_IRR2 70
#define CR_IRR3 71
#define CR_ITV 72
#define CR_PMV 73
#define CR_CMCV 74
#define CR_LRR0 80
#define CR_LRR1 81
enum asm_cmpltr_class {
ASM_CC_NONE,
ASM_CC_ACLR,
ASM_CC_BSW, ASM_CC_BTYPE, ASM_CC_BWH,
ASM_CC_CHK, ASM_CC_CLRRRB, ASM_CC_CREL, ASM_CC_CTYPE,
ASM_CC_DEP, ASM_CC_DH,
ASM_CC_FC, ASM_CC_FCREL, ASM_CC_FCTYPE, ASM_CC_FCVT, ASM_CC_FLDTYPE,
ASM_CC_FMERGE, ASM_CC_FREL, ASM_CC_FSWAP,
ASM_CC_GETF,
ASM_CC_IH, ASM_CC_INVALA, ASM_CC_IPWH, ASM_CC_ITC, ASM_CC_ITR,
ASM_CC_LDHINT, ASM_CC_LDTYPE, ASM_CC_LFETCH, ASM_CC_LFHINT,
ASM_CC_LFTYPE, ASM_CC_LR,
ASM_CC_MF, ASM_CC_MOV, ASM_CC_MWH,
ASM_CC_PAVG, ASM_CC_PC, ASM_CC_PH, ASM_CC_PREL, ASM_CC_PRTYPE,
ASM_CC_PTC, ASM_CC_PTR, ASM_CC_PVEC,
ASM_CC_SAT, ASM_CC_SEM, ASM_CC_SETF, ASM_CC_SF, ASM_CC_SRLZ,
ASM_CC_STHINT, ASM_CC_STTYPE, ASM_CC_SYNC,
ASM_CC_RW,
ASM_CC_TREL, ASM_CC_TRUNC,
ASM_CC_UNIT, ASM_CC_UNPACK, ASM_CC_UNS,
ASM_CC_XMA
};
enum asm_cmpltr_type {
ASM_CT_NONE,
ASM_CT_COND = ASM_CT_NONE,
ASM_CT_0, ASM_CT_1,
ASM_CT_A, ASM_CT_ACQ, ASM_CT_AND,
ASM_CT_B, ASM_CT_BIAS,
ASM_CT_C_CLR, ASM_CT_C_CLR_ACQ, ASM_CT_C_NC, ASM_CT_CALL,
ASM_CT_CEXIT, ASM_CT_CLOOP, ASM_CT_CLR, ASM_CT_CTOP,
ASM_CT_D, ASM_CT_DC_DC, ASM_CT_DC_NT, ASM_CT_DPNT, ASM_CT_DPTK,
ASM_CT_E, ASM_CT_EQ, ASM_CT_EXCL, ASM_CT_EXIT, ASM_CT_EXP,
ASM_CT_F, ASM_CT_FAULT, ASM_CT_FEW, ASM_CT_FILL, ASM_CT_FX, ASM_CT_FXU,
ASM_CT_G, ASM_CT_GA, ASM_CT_GE, ASM_CT_GT,
ASM_CT_H, ASM_CT_HU,
ASM_CT_I, ASM_CT_IA, ASM_CT_IMP,
ASM_CT_L, ASM_CT_LE, ASM_CT_LOOP, ASM_CT_LR, ASM_CT_LT, ASM_CT_LTU,
ASM_CT_M, ASM_CT_MANY,
ASM_CT_NC, ASM_CT_NE, ASM_CT_NEQ, ASM_CT_NL, ASM_CT_NLE, ASM_CT_NLT,
ASM_CT_NM, ASM_CT_NR, ASM_CT_NS, ASM_CT_NT_DC, ASM_CT_NT_NT,
ASM_CT_NT_TK, ASM_CT_NT1, ASM_CT_NT2, ASM_CT_NTA, ASM_CT_NZ,
ASM_CT_OR, ASM_CT_OR_ANDCM, ASM_CT_ORD,
ASM_CT_PR,
ASM_CT_R, ASM_CT_RAZ, ASM_CT_REL, ASM_CT_RET, ASM_CT_RW,
ASM_CT_S, ASM_CT_S0, ASM_CT_S1, ASM_CT_S2, ASM_CT_S3, ASM_CT_SA,
ASM_CT_SE, ASM_CT_SIG, ASM_CT_SPILL, ASM_CT_SPNT, ASM_CT_SPTK,
ASM_CT_SSS,
ASM_CT_TK_DC, ASM_CT_TK_NT, ASM_CT_TK_TK, ASM_CT_TRUNC,
ASM_CT_U, ASM_CT_UNC, ASM_CT_UNORD, ASM_CT_USS, ASM_CT_UUS, ASM_CT_UUU,
ASM_CT_W, ASM_CT_WEXIT, ASM_CT_WTOP,
ASM_CT_X, ASM_CT_XF,
ASM_CT_Z,
};
/* Completer. */
struct asm_cmpltr {
enum asm_cmpltr_class c_class;
enum asm_cmpltr_type c_type;
};
/* Operand types. */
enum asm_oper_type {
ASM_OPER_NONE,
ASM_OPER_AREG, /* = ar# */
ASM_OPER_BREG, /* = b# */
ASM_OPER_CPUID, /* = cpuid[r#] */
ASM_OPER_CREG, /* = cr# */
ASM_OPER_DBR, /* = dbr[r#] */
ASM_OPER_DISP, /* IP relative displacement. */
ASM_OPER_DTR, /* = dtr[r#] */
ASM_OPER_FREG, /* = f# */
ASM_OPER_GREG, /* = r# */
ASM_OPER_IBR, /* = ibr[r#] */
ASM_OPER_IMM, /* Immediate */
ASM_OPER_IP, /* = ip */
ASM_OPER_ITR, /* = itr[r#] */
ASM_OPER_MEM, /* = [r#] */
ASM_OPER_MSR, /* = msr[r#] */
ASM_OPER_PKR, /* = pkr[r#] */
ASM_OPER_PMC, /* = pmc[r#] */
ASM_OPER_PMD, /* = pmd[r#] */
ASM_OPER_PR, /* = pr */
ASM_OPER_PR_ROT, /* = pr.rot */
ASM_OPER_PREG, /* = p# */
ASM_OPER_PSR, /* = psr */
ASM_OPER_PSR_L, /* = psr.l */
ASM_OPER_PSR_UM, /* = psr.um */
ASM_OPER_RR /* = rr[r#] */
};
/* Operand */
struct asm_oper {
enum asm_oper_type o_type;
int o_read:1;
int o_write:1;
uint64_t o_value;
};
/* Instruction formats. */
enum asm_fmt {
ASM_FMT_NONE,
ASM_FMT_A = 0x0100,
ASM_FMT_A1, ASM_FMT_A2, ASM_FMT_A3, ASM_FMT_A4,
ASM_FMT_A5, ASM_FMT_A6, ASM_FMT_A7, ASM_FMT_A8,
ASM_FMT_A9, ASM_FMT_A10,
ASM_FMT_B = 0x0200,
ASM_FMT_B1, ASM_FMT_B2, ASM_FMT_B3, ASM_FMT_B4,
ASM_FMT_B5, ASM_FMT_B6, ASM_FMT_B7, ASM_FMT_B8,
ASM_FMT_B9,
ASM_FMT_F = 0x0300,
ASM_FMT_F1, ASM_FMT_F2, ASM_FMT_F3, ASM_FMT_F4,
ASM_FMT_F5, ASM_FMT_F6, ASM_FMT_F7, ASM_FMT_F8,
ASM_FMT_F9, ASM_FMT_F10, ASM_FMT_F11, ASM_FMT_F12,
ASM_FMT_F13, ASM_FMT_F14, ASM_FMT_F15,
ASM_FMT_I = 0x0400,
ASM_FMT_I1, ASM_FMT_I2, ASM_FMT_I3, ASM_FMT_I4,
ASM_FMT_I5, ASM_FMT_I6, ASM_FMT_I7, ASM_FMT_I8,
ASM_FMT_I9, ASM_FMT_I10, ASM_FMT_I11, ASM_FMT_I12,
ASM_FMT_I13, ASM_FMT_I14, ASM_FMT_I15, ASM_FMT_I16,
ASM_FMT_I17, ASM_FMT_I19, ASM_FMT_I20, ASM_FMT_I21,
ASM_FMT_I22, ASM_FMT_I23, ASM_FMT_I24, ASM_FMT_I25,
ASM_FMT_I26, ASM_FMT_I27, ASM_FMT_I28, ASM_FMT_I29,
ASM_FMT_M = 0x0500,
ASM_FMT_M1, ASM_FMT_M2, ASM_FMT_M3, ASM_FMT_M4,
ASM_FMT_M5, ASM_FMT_M6, ASM_FMT_M7, ASM_FMT_M8,
ASM_FMT_M9, ASM_FMT_M10, ASM_FMT_M11, ASM_FMT_M12,
ASM_FMT_M13, ASM_FMT_M14, ASM_FMT_M15, ASM_FMT_M16,
ASM_FMT_M17, ASM_FMT_M18, ASM_FMT_M19, ASM_FMT_M20,
ASM_FMT_M21, ASM_FMT_M22, ASM_FMT_M23, ASM_FMT_M24,
ASM_FMT_M25, ASM_FMT_M26, ASM_FMT_M27, ASM_FMT_M28,
ASM_FMT_M29, ASM_FMT_M30, ASM_FMT_M31, ASM_FMT_M32,
ASM_FMT_M33, ASM_FMT_M34, ASM_FMT_M35, ASM_FMT_M36,
ASM_FMT_M37, ASM_FMT_M38, ASM_FMT_M39, ASM_FMT_M40,
ASM_FMT_M41, ASM_FMT_M42, ASM_FMT_M43, ASM_FMT_M44,
ASM_FMT_M45, ASM_FMT_M46,
ASM_FMT_X = 0x0600,
ASM_FMT_X1, ASM_FMT_X2, ASM_FMT_X3, ASM_FMT_X4
};
/* Instruction opcodes. */
enum asm_op {
ASM_OP_NONE,
ASM_OP_ADD, ASM_OP_ADDL, ASM_OP_ADDP4, ASM_OP_ADDS, ASM_OP_ALLOC,
ASM_OP_AND, ASM_OP_ANDCM,
ASM_OP_BR, ASM_OP_BREAK, ASM_OP_BRL, ASM_OP_BRP, ASM_OP_BSW,
ASM_OP_CHK, ASM_OP_CLRRRB, ASM_OP_CMP, ASM_OP_CMP4, ASM_OP_CMP8XCHG16,
ASM_OP_CMPXCHG1, ASM_OP_CMPXCHG2, ASM_OP_CMPXCHG4, ASM_OP_CMPXCHG8,
ASM_OP_COVER, ASM_OP_CZX1, ASM_OP_CZX2,
ASM_OP_DEP,
ASM_OP_EPC, ASM_OP_EXTR,
ASM_OP_FAMAX, ASM_OP_FAMIN, ASM_OP_FAND, ASM_OP_FANDCM, ASM_OP_FC,
ASM_OP_FCHKF, ASM_OP_FCLASS, ASM_OP_FCLRF, ASM_OP_FCMP, ASM_OP_FCVT,
ASM_OP_FETCHADD4, ASM_OP_FETCHADD8, ASM_OP_FLUSHRS, ASM_OP_FMA,
ASM_OP_FMAX, ASM_OP_FMERGE, ASM_OP_FMIN, ASM_OP_FMIX, ASM_OP_FMS,
ASM_OP_FNMA, ASM_OP_FOR, ASM_OP_FPACK, ASM_OP_FPAMAX, ASM_OP_FPAMIN,
ASM_OP_FPCMP, ASM_OP_FPCVT, ASM_OP_FPMA, ASM_OP_FPMAX, ASM_OP_FPMERGE,
ASM_OP_FPMIN, ASM_OP_FPMS, ASM_OP_FPNMA, ASM_OP_FPRCPA,
ASM_OP_FPRSQRTA, ASM_OP_FRCPA, ASM_OP_FRSQRTA, ASM_OP_FSELECT,
ASM_OP_FSETC, ASM_OP_FSWAP, ASM_OP_FSXT, ASM_OP_FWB, ASM_OP_FXOR,
ASM_OP_GETF,
ASM_OP_INVALA, ASM_OP_ITC, ASM_OP_ITR,
ASM_OP_LD1, ASM_OP_LD16, ASM_OP_LD2, ASM_OP_LD4, ASM_OP_LD8,
ASM_OP_LDF, ASM_OP_LDF8, ASM_OP_LDFD, ASM_OP_LDFE, ASM_OP_LDFP8,
ASM_OP_LDFPD, ASM_OP_LDFPS, ASM_OP_LDFS, ASM_OP_LFETCH, ASM_OP_LOADRS,
ASM_OP_MF, ASM_OP_MIX1, ASM_OP_MIX2, ASM_OP_MIX4, ASM_OP_MOV,
ASM_OP_MOVL, ASM_OP_MUX1, ASM_OP_MUX2,
ASM_OP_NOP,
ASM_OP_OR,
ASM_OP_PACK2, ASM_OP_PACK4, ASM_OP_PADD1, ASM_OP_PADD2, ASM_OP_PADD4,
ASM_OP_PAVG1, ASM_OP_PAVG2, ASM_OP_PAVGSUB1, ASM_OP_PAVGSUB2,
ASM_OP_PCMP1, ASM_OP_PCMP2, ASM_OP_PCMP4, ASM_OP_PMAX1, ASM_OP_PMAX2,
ASM_OP_PMIN1, ASM_OP_PMIN2, ASM_OP_PMPY2, ASM_OP_PMPYSHR2,
ASM_OP_POPCNT, ASM_OP_PROBE, ASM_OP_PSAD1, ASM_OP_PSHL2, ASM_OP_PSHL4,
ASM_OP_PSHLADD2, ASM_OP_PSHR2, ASM_OP_PSHR4, ASM_OP_PSHRADD2,
ASM_OP_PSUB1, ASM_OP_PSUB2, ASM_OP_PSUB4, ASM_OP_PTC, ASM_OP_PTR,
ASM_OP_RFI, ASM_OP_RSM, ASM_OP_RUM,
ASM_OP_SETF, ASM_OP_SHL, ASM_OP_SHLADD, ASM_OP_SHLADDP4, ASM_OP_SHR,
ASM_OP_SHRP, ASM_OP_SRLZ, ASM_OP_SSM, ASM_OP_ST1, ASM_OP_ST16,
ASM_OP_ST2, ASM_OP_ST4, ASM_OP_ST8, ASM_OP_STF, ASM_OP_STF8,
ASM_OP_STFD, ASM_OP_STFE, ASM_OP_STFS, ASM_OP_SUB, ASM_OP_SUM,
ASM_OP_SXT1, ASM_OP_SXT2, ASM_OP_SXT4, ASM_OP_SYNC,
ASM_OP_TAK, ASM_OP_TBIT, ASM_OP_THASH, ASM_OP_TNAT, ASM_OP_TPA,
ASM_OP_TTAG,
ASM_OP_UNPACK1, ASM_OP_UNPACK2, ASM_OP_UNPACK4,
ASM_OP_XCHG1, ASM_OP_XCHG2, ASM_OP_XCHG4, ASM_OP_XCHG8, ASM_OP_XMA,
ASM_OP_XOR,
ASM_OP_ZXT1, ASM_OP_ZXT2, ASM_OP_ZXT4,
/* Additional opcodes used only internally. */
ASM_ADDITIONAL_OPCODES
};
/* Instruction. */
struct asm_inst {
uint64_t i_bits;
struct asm_oper i_oper[7];
struct asm_cmpltr i_cmpltr[5];
enum asm_fmt i_format;
enum asm_op i_op;
int i_ncmpltrs;
int i_srcidx;
};
struct asm_bundle {
const char *b_templ;
struct asm_inst b_inst[3];
};
/* Functional units. */
enum asm_unit {
ASM_UNIT_NONE,
ASM_UNIT_A = 0x0100, /* A unit. */
ASM_UNIT_B = 0x0200, /* B unit. */
ASM_UNIT_F = 0x0300, /* F unit. */
ASM_UNIT_I = 0x0400, /* I unit. */
ASM_UNIT_M = 0x0500, /* M unit. */
ASM_UNIT_X = 0x0600 /* X unit. */
};
#ifdef _DISASM_INT_H_
int asm_extract(enum asm_op, enum asm_fmt, uint64_t, struct asm_bundle *, int);
#endif
int asm_decode(uint64_t, struct asm_bundle *);
void asm_completer(const struct asm_cmpltr *, char *);
void asm_mnemonic(const enum asm_op, char *);
void asm_operand(const struct asm_oper *, char *, uint64_t);
void asm_print_bundle(const struct asm_bundle *, uint64_t);
void asm_print_inst(const struct asm_bundle *, int, uint64_t);
#endif /* _DISASM_H_ */

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/*
* Copyright (c) 2000-2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <ia64/disasm/disasm_int.h>
#include <ia64/disasm/disasm.h>
/*
* Mnemonics (keep in sync with enum asm_op).
*/
static const char *asm_mnemonics[] = {
NULL,
"add", "addl", "addp4", "adds", "alloc", "and", "andcm",
"br", "break", "brl", "brp", "bsw",
"chk", "clrrrb", "cmp", "cmp4", "cmp8xchg16", "cmpxchg1", "cmpxchg2",
"cmpxchg4", "cmpxchg8", "cover", "czx1", "czx2",
"dep",
"epc", "extr",
"famax", "famin", "fand", "fandcm", "fc", "fchkf", "fclass", "fclrf",
"fcmp", "fcvt", "fetchadd4", "fetchadd8", "flushrs", "fma", "fmax",
"fmerge", "fmin", "fmix", "fms", "fnma", "for", "fpack", "fpamax",
"fpamin", "fpcmp", "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin",
"fpms", "fpnma", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect",
"fsetc", "fswap", "fsxt", "fwb", "fxor",
"getf",
"invala", "itc", "itr",
"ld1", "ld16", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe",
"ldfp8", "ldfpd", "ldfps", "ldfs", "lfetch", "loadrs",
"mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2",
"nop",
"or",
"pack2", "pack4", "padd1", "padd2", "padd4", "pavg1", "pavg2",
"pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", "pmax2",
"pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "probe", "psad1",
"pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2", "psub1",
"psub2", "psub4", "ptc", "ptr",
"rfi", "rsm", "rum",
"setf", "shl", "shladd", "shladdp4", "shr", "shrp", "srlz", "ssm",
"st1", "st16", "st2", "st4", "st8", "stf", "stf8", "stfd", "stfe",
"stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync",
"tak", "tbit", "thash", "tnat", "tpa", "ttag",
"unpack1", "unpack2", "unpack4",
"xchg1", "xchg2", "xchg4", "xchg8", "xma", "xor",
"zxt1", "zxt2", "zxt4"
};
/*
* Completers (keep in sync with enum asm_cmpltr_type).
*/
static const char *asm_completers[] = {
"",
".0", ".1",
".a", ".acq", ".and",
".b", ".bias",
".c.clr", ".c.clr.acq", ".c.nc", ".call", ".cexit", ".cloop", ".clr",
".ctop",
".d", ".dc.dc", ".dc.nt", ".dpnt", ".dptk",
".e", ".eq", ".excl", ".exit", ".exp",
".f", ".fault", ".few", ".fill", ".fx", ".fxu",
".g", ".ga", ".ge", ".gt",
".h", ".hu",
".i", ".ia", ".imp",
".l", ".le", ".loop", ".lr", ".lt", ".ltu",
".m", ".many",
".nc", ".ne", ".neq", ".nl", ".nle", ".nlt", ".nm", ".nr", ".ns",
".nt.dc", ".nt.nt", ".nt.tk", ".nt1", ".nt2", ".nta", ".nz",
".or", ".or.andcm", ".ord",
".pr",
".r", ".raz", ".rel", ".ret", ".rw",
".s", ".s0", ".s1", ".s2", ".s3", ".sa", ".se", ".sig", ".spill",
".spnt", ".sptk", ".sss",
".tk.dc", ".tk.nt", ".tk.tk", ".trunc",
".u", ".unc", ".unord", ".uss", ".uus", ".uuu",
".w", ".wexit", ".wtop",
".x", ".xf",
".z"
};
void
asm_completer(const struct asm_cmpltr *c, char *buf)
{
strcpy(buf, asm_completers[c->c_type]);
}
void
asm_mnemonic(enum asm_op op, char *buf)
{
strcpy(buf, asm_mnemonics[(op < ASM_OP_INTERNAL_OPCODES) ? op : 0]);
}
void
asm_operand(const struct asm_oper *o, char *buf, uint64_t ip)
{
const char *n;
n = NULL;
switch (o->o_type) {
case ASM_OPER_AREG:
switch ((int)o->o_value) {
case AR_K0: n = "k0"; break;
case AR_K1: n = "k1"; break;
case AR_K2: n = "k2"; break;
case AR_K3: n = "k3"; break;
case AR_K4: n = "k4"; break;
case AR_K5: n = "k5"; break;
case AR_K6: n = "k6"; break;
case AR_K7: n = "k7"; break;
case AR_RSC: n = "rsc"; break;
case AR_BSP: n = "bsp"; break;
case AR_BSPSTORE: n = "bspstore"; break;
case AR_RNAT: n = "rnat"; break;
case AR_FCR: n = "fcr"; break;
case AR_EFLAG: n = "eflag"; break;
case AR_CSD: n = "csd"; break;
case AR_SSD: n = "ssd"; break;
case AR_CFLG: n = "cflg"; break;
case AR_FSR: n = "fsr"; break;
case AR_FIR: n = "fir"; break;
case AR_FDR: n = "fdr"; break;
case AR_CCV: n = "ccv"; break;
case AR_UNAT: n = "unat"; break;
case AR_FPSR: n = "fpsr"; break;
case AR_ITC: n = "itc"; break;
case AR_PFS: n = "pfs"; break;
case AR_LC: n = "lc"; break;
case AR_EC: n = "ec"; break;
default:
sprintf(buf, "ar%d", (int)o->o_value);
return;
}
sprintf(buf, "ar.%s", n);
return;
case ASM_OPER_BREG:
if (o->o_value != 0)
sprintf(buf, "b%d", (int)o->o_value);
else
strcpy(buf, "rp");
return;
case ASM_OPER_CPUID:
n = "cpuid";
break;
case ASM_OPER_CREG:
switch ((int)o->o_value) {
case CR_DCR: n = "dcr"; break;
case CR_ITM: n = "itm"; break;
case CR_IVA: n = "iva"; break;
case CR_PTA: n = "pta"; break;
case CR_IPSR: n = "ipsr"; break;
case CR_ISR: n = "isr"; break;
case CR_IIP: n = "iip"; break;
case CR_IFA: n = "ifa"; break;
case CR_ITIR: n = "itir"; break;
case CR_IIPA: n = "iipa"; break;
case CR_IFS: n = "ifs"; break;
case CR_IIM: n = "iim"; break;
case CR_IHA: n = "iha"; break;
case CR_LID: n = "lid"; break;
case CR_IVR: n = "ivr"; break;
case CR_TPR: n = "tpr"; break;
case CR_EOI: n = "eoi"; break;
case CR_IRR0: n = "irr0"; break;
case CR_IRR1: n = "irr1"; break;
case CR_IRR2: n = "irr2"; break;
case CR_IRR3: n = "irr3"; break;
case CR_ITV: n = "itv"; break;
case CR_PMV: n = "pmv"; break;
case CR_CMCV: n = "cmcv"; break;
case CR_LRR0: n = "lrr0"; break;
case CR_LRR1: n = "lrr1"; break;
default:
sprintf(buf, "cr%d", (int)o->o_value);
return;
}
sprintf(buf, "cr.%s", n);
return;
case ASM_OPER_DBR:
n = "dbr";
break;
case ASM_OPER_DISP:
sprintf(buf, "%lx", ip + o->o_value);
return;
case ASM_OPER_DTR:
n = "dtr";
break;
case ASM_OPER_FREG:
sprintf(buf, "f%d", (int)o->o_value);
return;
case ASM_OPER_GREG:
break;
case ASM_OPER_IBR:
n = "ibr";
break;
case ASM_OPER_IMM:
sprintf(buf, "0x%lx", o->o_value);
return;
case ASM_OPER_IP:
strcpy(buf, "ip");
return;
case ASM_OPER_ITR:
n = "itr";
break;
case ASM_OPER_MEM:
n = "";
break;
case ASM_OPER_MSR:
n = "msr";
break;
case ASM_OPER_PKR:
n = "pkr";
break;
case ASM_OPER_PMC:
n = "pmc";
break;
case ASM_OPER_PMD:
n = "pmd";
break;
case ASM_OPER_PR:
strcpy(buf, "pr");
return;
case ASM_OPER_PR_ROT:
strcpy(buf, "pr.rot");
return;
case ASM_OPER_PREG:
sprintf(buf, "p%d", (int)o->o_value);
return;
case ASM_OPER_PSR:
strcpy(buf, "psr");
return;
case ASM_OPER_PSR_L:
strcpy(buf, "psr.l");
return;
case ASM_OPER_PSR_UM:
strcpy(buf, "psr.um");
return;
case ASM_OPER_RR:
n = "rr";
break;
case ASM_OPER_NONE:
KASSERT(0, ("foo"));
break;
}
if (n != NULL)
buf += sprintf(buf, "%s[", n);
switch ((int)o->o_value) {
case 1: strcpy(buf, "gp"); buf += 2; break;
case 12: strcpy(buf, "sp"); buf += 2; break;
case 13: strcpy(buf, "tp"); buf += 2; break;
default: buf += sprintf(buf, "r%d", (int)o->o_value); break;
}
if (n != NULL)
strcpy(buf, "]");
}
void
asm_print_bundle(const struct asm_bundle *b, uint64_t ip)
{
asm_print_inst(b, 0, ip);
asm_print_inst(b, 1, ip);
asm_print_inst(b, 2, ip);
}
void
asm_print_inst(const struct asm_bundle *b, int slot, uint64_t ip)
{
char buf[32];
const struct asm_inst *i;
const char *tmpl;
int n, w;
tmpl = b->b_templ + slot;
if (*tmpl == ';' || (slot == 2 && b->b_templ[1] == ';'))
tmpl++;
i = b->b_inst + slot;
if (*tmpl == 'L' || i->i_op == ASM_OP_NONE)
return;
/* Address + slot. */
printf("%lx[%c] ", ip + slot, *tmpl);
/* Predicate. */
if (i->i_oper[0].o_value != 0) {
asm_operand(i->i_oper+0, buf, ip);
w = printf("(%s)", buf);
} else
w = 0;
while (w++ < 8)
printf(" ");
/* Mnemonic & completers. */
asm_mnemonic(i->i_op, buf);
w = printf(buf);
n = 0;
while (n < i->i_ncmpltrs) {
asm_completer(i->i_cmpltr + n, buf);
w += printf(buf);
n++;
}
while (w++ < 15)
printf(" ");
printf(" ");
/* Operands. */
n = 1;
while (n < 7 && i->i_oper[n].o_type != ASM_OPER_NONE) {
if (n > 1) {
if (n == i->i_srcidx)
printf(" = ");
else
printf(", ");
}
asm_operand(i->i_oper + n, buf, ip);
printf(buf);
n++;
}
printf("\n");
}

216
sys/ia64/disasm/disasm_int.h Normal file
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@ -0,0 +1,216 @@
/*
* Copyright (c) 2000-2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DISASM_INT_H_
#define _DISASM_INT_H_
#ifdef _DISASM_H_
#error Include disasm_int.h before disasm.h
#endif
/*
* Instruction bundle specifics.
*/
#define TMPL_BITS 5
#define SLOT_BITS 41
#define SLOT_COUNT 3
#define BUNDLE_SIZE (SLOT_COUNT * SLOT_BITS + TMPL_BITS)
#define BUNDLE_BYTES ((BUNDLE_SIZE+7) >> 3)
#define TMPL_MASK ((1 << TMPL_BITS) - 1)
#define SLOT_MASK ((1ULL << SLOT_BITS) - 1ULL)
#define TMPL(p) (*(const uint8_t*)(p) & TMPL_MASK)
#define _U32(p,i) ((uint64_t)(((const uint32_t*)(p))[i]))
#define _SLOT(p,i) (_U32(p,i) | (_U32(p,(i)+1)<<32))
#define SLOT(p,i) ((_SLOT(p,i) >> (TMPL_BITS+((i)<<3)+(i))) & SLOT_MASK)
/*
* Instruction specifics
*/
#define _FLD64(i,o,l) ((i >> o) & ((1LL << l) - 1LL))
#define FIELD(i,o,l) ((uint32_t)_FLD64(i,o,l))
#define OPCODE(i) FIELD(i, 37, 4)
#define QP_BITS 6
#define QP(i) FIELD(i, 0, QP_BITS)
#define REG_BITS 7
#define REG(i,r) FIELD(i, ((r) - 1) * REG_BITS + QP_BITS, REG_BITS)
/*
* Opcodes used internally as sentinels to denote either a lack of more
* specific information or to preserve the additional state/information
* we already have and need to pass around for later use.
*/
#define ASM_ADDITIONAL_OPCODES \
ASM_OP_INTERNAL_OPCODES, \
ASM_OP_BR_CALL, ASM_OP_BR_CEXIT, ASM_OP_BR_CLOOP, \
ASM_OP_BR_COND, ASM_OP_BR_CTOP, ASM_OP_BR_IA, ASM_OP_BR_RET, \
ASM_OP_BR_WEXIT, ASM_OP_BR_WTOP, \
ASM_OP_BREAK_B, ASM_OP_BREAK_F, ASM_OP_BREAK_I, ASM_OP_BREAK_M, \
ASM_OP_BREAK_X, \
ASM_OP_BRL_COND, ASM_OP_BRL_CALL, \
ASM_OP_BRP_, ASM_OP_BRP_RET, \
ASM_OP_BSW_0, ASM_OP_BSW_1, \
ASM_OP_CHK_A_CLR, ASM_OP_CHK_A_NC, ASM_OP_CHK_S, \
ASM_OP_CHK_S_I, ASM_OP_CHK_S_M, \
ASM_OP_CLRRRB_, ASM_OP_CLRRRB_PR, \
ASM_OP_CMP_EQ, ASM_OP_CMP_EQ_AND, ASM_OP_CMP_EQ_OR, \
ASM_OP_CMP_EQ_OR_ANDCM, ASM_OP_CMP_EQ_UNC, ASM_OP_CMP_GE_AND, \
ASM_OP_CMP_GE_OR, ASM_OP_CMP_GE_OR_ANDCM, ASM_OP_CMP_GT_AND, \
ASM_OP_CMP_GT_OR, ASM_OP_CMP_GT_OR_ANDCM, ASM_OP_CMP_LE_AND, \
ASM_OP_CMP_LE_OR, ASM_OP_CMP_LE_OR_ANDCM, ASM_OP_CMP_LT, \
ASM_OP_CMP_LT_AND, ASM_OP_CMP_LT_OR, ASM_OP_CMP_LT_OR_ANDCM, \
ASM_OP_CMP_LT_UNC, ASM_OP_CMP_LTU, ASM_OP_CMP_LTU_UNC, \
ASM_OP_CMP_NE_AND, ASM_OP_CMP_NE_OR, ASM_OP_CMP_NE_OR_ANDCM, \
ASM_OP_CMP4_EQ, ASM_OP_CMP4_EQ_AND, ASM_OP_CMP4_EQ_OR, \
ASM_OP_CMP4_EQ_OR_ANDCM, ASM_OP_CMP4_EQ_UNC, ASM_OP_CMP4_GE_AND,\
ASM_OP_CMP4_GE_OR, ASM_OP_CMP4_GE_OR_ANDCM, ASM_OP_CMP4_GT_AND, \
ASM_OP_CMP4_GT_OR, ASM_OP_CMP4_GT_OR_ANDCM, ASM_OP_CMP4_LE_AND, \
ASM_OP_CMP4_LE_OR, ASM_OP_CMP4_LE_OR_ANDCM, ASM_OP_CMP4_LT, \
ASM_OP_CMP4_LT_AND, ASM_OP_CMP4_LT_OR, ASM_OP_CMP4_LT_OR_ANDCM, \
ASM_OP_CMP4_LT_UNC, ASM_OP_CMP4_LTU, ASM_OP_CMP4_LTU_UNC, \
ASM_OP_CMP4_NE_AND, ASM_OP_CMP4_NE_OR, ASM_OP_CMP4_NE_OR_ANDCM, \
ASM_OP_CMP8XCHG16_ACQ, ASM_OP_CMP8XCHG16_REL, \
ASM_OP_CMPXCHG1_ACQ, ASM_OP_CMPXCHG1_REL, \
ASM_OP_CMPXCHG2_ACQ, ASM_OP_CMPXCHG2_REL, \
ASM_OP_CMPXCHG4_ACQ, ASM_OP_CMPXCHG4_REL, \
ASM_OP_CMPXCHG8_ACQ, ASM_OP_CMPXCHG8_REL, \
ASM_OP_CZX1_L, ASM_OP_CZX1_R, \
ASM_OP_CZX2_L, ASM_OP_CZX2_R, \
ASM_OP_DEP_, ASM_OP_DEP_Z, \
ASM_OP_FC_, ASM_OP_FC_I, \
ASM_OP_FCLASS_M, \
ASM_OP_FCVT_FX, ASM_OP_FCVT_FX_TRUNC, ASM_OP_FCVT_FXU, \
ASM_OP_FCVT_FXU_TRUNC, ASM_OP_FCVT_XF, \
ASM_OP_FETCHADD4_ACQ, ASM_OP_FETCHADD4_REL, \
ASM_OP_FETCHADD8_ACQ, ASM_OP_FETCHADD8_REL, \
ASM_OP_FMA_, ASM_OP_FMA_D, ASM_OP_FMA_S, \
ASM_OP_FMERGE_NS, ASM_OP_FMERGE_S, ASM_OP_FMERGE_SE, \
ASM_OP_FMIX_L, ASM_OP_FMIX_LR, ASM_OP_FMIX_R, \
ASM_OP_FMS_, ASM_OP_FMS_D, ASM_OP_FMS_S, \
ASM_OP_FNMA_, ASM_OP_FNMA_D, ASM_OP_FNMA_S, \
ASM_OP_FPCMP_EQ, ASM_OP_FPCMP_LE, ASM_OP_FPCMP_LT, \
ASM_OP_FPCMP_NEQ, ASM_OP_FPCMP_NLE, ASM_OP_FPCMP_NLT, \
ASM_OP_FPCMP_ORD, ASM_OP_FPCMP_UNORD, \
ASM_OP_FPCVT_FX, ASM_OP_FPCVT_FX_TRUNC, ASM_OP_FPCVT_FXU, \
ASM_OP_FPCVT_FXU_TRUNC, \
ASM_OP_FPMERGE_NS, ASM_OP_FPMERGE_S, ASM_OP_FPMERGE_SE, \
ASM_OP_FSWAP_, ASM_OP_FSWAP_NL, ASM_OP_FSWAP_NR, \
ASM_OP_FSXT_L, ASM_OP_FSXT_R, \
ASM_OP_GETF_D, ASM_OP_GETF_EXP, ASM_OP_GETF_S, ASM_OP_GETF_SIG, \
ASM_OP_INVALA_, ASM_OP_INVALA_E, \
ASM_OP_ITC_D, ASM_OP_ITC_I, \
ASM_OP_ITR_D, ASM_OP_ITR_I, \
ASM_OP_LD1_, ASM_OP_LD1_A, ASM_OP_LD1_ACQ, ASM_OP_LD1_BIAS, \
ASM_OP_LD1_C_CLR, ASM_OP_LD1_C_CLR_ACQ, ASM_OP_LD1_C_NC, \
ASM_OP_LD1_S, ASM_OP_LD1_SA, \
ASM_OP_LD16_, ASM_OP_LD16_ACQ, \
ASM_OP_LD2_, ASM_OP_LD2_A, ASM_OP_LD2_ACQ, ASM_OP_LD2_BIAS, \
ASM_OP_LD2_C_CLR, ASM_OP_LD2_C_CLR_ACQ, ASM_OP_LD2_C_NC, \
ASM_OP_LD2_S, ASM_OP_LD2_SA, \
ASM_OP_LD4_, ASM_OP_LD4_A, ASM_OP_LD4_ACQ, ASM_OP_LD4_BIAS, \
ASM_OP_LD4_C_CLR, ASM_OP_LD4_C_CLR_ACQ, ASM_OP_LD4_C_NC, \
ASM_OP_LD4_S, ASM_OP_LD4_SA, \
ASM_OP_LD8_, ASM_OP_LD8_A, ASM_OP_LD8_ACQ, ASM_OP_LD8_BIAS, \
ASM_OP_LD8_C_CLR, ASM_OP_LD8_C_CLR_ACQ, ASM_OP_LD8_C_NC, \
ASM_OP_LD8_FILL, ASM_OP_LD8_S, ASM_OP_LD8_SA, \
ASM_OP_LDF_FILL, \
ASM_OP_LDF8_, ASM_OP_LDF8_A, ASM_OP_LDF8_C_CLR, \
ASM_OP_LDF8_C_NC, ASM_OP_LDF8_S, ASM_OP_LDF8_SA, \
ASM_OP_LDFD_, ASM_OP_LDFD_A, ASM_OP_LDFD_C_CLR, \
ASM_OP_LDFD_C_NC, ASM_OP_LDFD_S, ASM_OP_LDFD_SA, \
ASM_OP_LDFE_, ASM_OP_LDFE_A, ASM_OP_LDFE_C_CLR, \
ASM_OP_LDFE_C_NC, ASM_OP_LDFE_S, ASM_OP_LDFE_SA, \
ASM_OP_LDFP8_, ASM_OP_LDFP8_A, ASM_OP_LDFP8_C_CLR, \
ASM_OP_LDFP8_C_NC, ASM_OP_LDFP8_S, ASM_OP_LDFP8_SA, \
ASM_OP_LDFPD_, ASM_OP_LDFPD_A, ASM_OP_LDFPD_C_CLR, \
ASM_OP_LDFPD_C_NC, ASM_OP_LDFPD_S, ASM_OP_LDFPD_SA, \
ASM_OP_LDFPS_, ASM_OP_LDFPS_A, ASM_OP_LDFPS_C_CLR, \
ASM_OP_LDFPS_C_NC, ASM_OP_LDFPS_S, ASM_OP_LDFPS_SA, \
ASM_OP_LDFS_, ASM_OP_LDFS_A, ASM_OP_LDFS_C_CLR, \
ASM_OP_LDFS_C_NC, ASM_OP_LDFS_S, ASM_OP_LDFS_SA, \
ASM_OP_LFETCH_, ASM_OP_LFETCH_EXCL, ASM_OP_LFETCH_FAULT, \
ASM_OP_LFETCH_FAULT_EXCL, \
ASM_OP_MF_, ASM_OP_MF_A, \
ASM_OP_MIX1_L, ASM_OP_MIX1_R, \
ASM_OP_MIX2_L, ASM_OP_MIX2_R, \
ASM_OP_MIX4_L, ASM_OP_MIX4_R, \
ASM_OP_MOV_, ASM_OP_MOV_CPUID, ASM_OP_MOV_DBR, ASM_OP_MOV_I, \
ASM_OP_MOV_IBR, ASM_OP_MOV_IP, ASM_OP_MOV_M, ASM_OP_MOV_MSR, \
ASM_OP_MOV_PKR, ASM_OP_MOV_PMC, ASM_OP_MOV_PMD, ASM_OP_MOV_PR, \
ASM_OP_MOV_PSR, ASM_OP_MOV_PSR_L, ASM_OP_MOV_PSR_UM, \
ASM_OP_MOV_RET, ASM_OP_MOV_RR, \
ASM_OP_NOP_B, ASM_OP_NOP_F, ASM_OP_NOP_I, ASM_OP_NOP_M, \
ASM_OP_NOP_X, \
ASM_OP_PACK2_SSS, ASM_OP_PACK2_USS, \
ASM_OP_PACK4_SSS, \
ASM_OP_PADD1_, ASM_OP_PADD1_SSS, ASM_OP_PADD1_UUS, \
ASM_OP_PADD1_UUU, \
ASM_OP_PADD2_, ASM_OP_PADD2_SSS, ASM_OP_PADD2_UUS, \
ASM_OP_PADD2_UUU, \
ASM_OP_PAVG1_, ASM_OP_PAVG1_RAZ, \
ASM_OP_PAVG2_, ASM_OP_PAVG2_RAZ, \
ASM_OP_PCMP1_EQ, ASM_OP_PCMP1_GT, \
ASM_OP_PCMP2_EQ, ASM_OP_PCMP2_GT, \
ASM_OP_PCMP4_EQ, ASM_OP_PCMP4_GT, \
ASM_OP_PMAX1_U, \
ASM_OP_PMIN1_U, \
ASM_OP_PMPY2_L, ASM_OP_PMPY2_R, \
ASM_OP_PMPYSHR2_, ASM_OP_PMPYSHR2_U, \
ASM_OP_PROBE_R, ASM_OP_PROBE_R_FAULT, ASM_OP_PROBE_RW_FAULT, \
ASM_OP_PROBE_W, ASM_OP_PROBE_W_FAULT, \
ASM_OP_PSHR2_, ASM_OP_PSHR2_U, \
ASM_OP_PSHR4_, ASM_OP_PSHR4_U, \
ASM_OP_PSUB1_, ASM_OP_PSUB1_SSS, ASM_OP_PSUB1_UUS, \
ASM_OP_PSUB1_UUU, \
ASM_OP_PSUB2_, ASM_OP_PSUB2_SSS, ASM_OP_PSUB2_UUS, \
ASM_OP_PSUB2_UUU, \
ASM_OP_PTC_E, ASM_OP_PTC_G, ASM_OP_PTC_GA, ASM_OP_PTC_L, \
ASM_OP_PTR_D, ASM_OP_PTR_I, \
ASM_OP_SETF_EXP, ASM_OP_SETF_D, ASM_OP_SETF_S, ASM_OP_SETF_SIG, \
ASM_OP_SHR_, ASM_OP_SHR_U, \
ASM_OP_SRLZ_D, ASM_OP_SRLZ_I, \
ASM_OP_ST1_, ASM_OP_ST1_REL, \
ASM_OP_ST16_, ASM_OP_ST16_REL, \
ASM_OP_ST2_, ASM_OP_ST2_REL, \
ASM_OP_ST4_, ASM_OP_ST4_REL, \
ASM_OP_ST8_, ASM_OP_ST8_REL, ASM_OP_ST8_SPILL, \
ASM_OP_STF_SPILL, \
ASM_OP_SYNC_I, \
ASM_OP_TBIT_NZ_AND, ASM_OP_TBIT_NZ_OR, ASM_OP_TBIT_NZ_OR_ANDCM, \
ASM_OP_TBIT_Z, ASM_OP_TBIT_Z_AND, ASM_OP_TBIT_Z_OR, \
ASM_OP_TBIT_Z_OR_ANDCM, ASM_OP_TBIT_Z_UNC, \
ASM_OP_TNAT_NZ_AND, ASM_OP_TNAT_NZ_OR, ASM_OP_TNAT_NZ_OR_ANDCM, \
ASM_OP_TNAT_Z, ASM_OP_TNAT_Z_AND, ASM_OP_TNAT_Z_OR, \
ASM_OP_TNAT_Z_OR_ANDCM, ASM_OP_TNAT_Z_UNC, \
ASM_OP_UNPACK1_H, ASM_OP_UNPACK1_L, \
ASM_OP_UNPACK2_H, ASM_OP_UNPACK2_L, \
ASM_OP_UNPACK4_H, ASM_OP_UNPACK4_L, \
ASM_OP_XMA_H, ASM_OP_XMA_HU, ASM_OP_XMA_L, \
ASM_OP_NUMBER_OF_OPCODES
#endif /* _DISASM_INT_H_ */