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The memory type bits (PAT, PCD, PWT) associated with a nested PTE or PDE

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are identical to the traditional x86 page tables.
This commit is contained in:
Neel Natu 2014-09-21 06:36:17 +00:00
parent 8f02c5e456
commit ba28c094bb
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/bhyve_svm/; revision=271922
1 changed files with 5 additions and 14 deletions
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15
sys/amd64/amd64/pmap.c
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@ -1115,6 +1115,7 @@ pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
switch (pmap->pm_type) {
case PT_X86:
case PT_RVI:
/* Verify that both PAT bits are not set at the same time */
KASSERT((entry & x86_pat_bits) != x86_pat_bits,
("Invalid PAT bits in entry %#lx", entry));
@ -1123,9 +1124,6 @@ pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
if ((entry & x86_pat_bits) != 0)
entry ^= x86_pat_bits;
break;
case PT_RVI:
/* XXX: PAT support. */
break;
case PT_EPT:
/*
* Nothing to do - the memory attributes are represented
@ -1153,6 +1151,7 @@ pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
switch (pmap->pm_type) {
case PT_X86:
case PT_RVI:
/* The PAT bit is different for PTE's and PDE's. */
pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
@ -1169,11 +1168,6 @@ pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
cache_bits |= PG_NC_PWT;
break;
case PT_RVI:
/* XXX: PAT support. */
cache_bits = 0;
break;
case PT_EPT:
cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
break;
@ -1192,11 +1186,8 @@ pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
switch (pmap->pm_type) {
case PT_X86:
mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
break;
case PT_RVI:
/* XXX: PAT support. */
mask = 0;
mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
break;
case PT_EPT:
mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);