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Modify the pci_cfgdisable() routine to bring it more in line with

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other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0
to the config address register when using config mechanism 1 to turn
off config access. In fact, it can be downright troublesome, since it
seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause
it to sporadically botch reads from some devices. This is the cause
of the missing USP ports problem I was experiencing with my Sun Opteron
system.

Also correct the case for mechanism 2: it's only necessary to write
a 0 to the ENABLE port.
This commit is contained in:
Bill Paul 2005-10-25 04:53:29 +00:00
parent f5c5d122f6
commit ba3af76df7
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=151643
2 changed files with 13 additions and 5 deletions
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8
sys/amd64/pci/pci_cfgreg.c
View File

@ -139,11 +139,15 @@ pci_cfgdisable(void)
{
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT, 0);
/*
* Do nothing for the config mechanism 1 case.
* Writing a 0 to the address port can apparently
* confuse some bridges and cause spurious
* access failures.
*/
break;
case 2:
outb(CONF2_ENABLE_PORT, 0);
outb(CONF2_FORWARD_PORT, 0);
break;
}
}

10
sys/i386/pci/pci_cfgreg.c
View File

@ -237,11 +237,15 @@ pci_cfgdisable(void)
{
switch (cfgmech) {
case CFGMECH_1:
outl(CONF1_ADDR_PORT, 0);
break;
/*
* Do nothing for the config mechanism 1 case.
* Writing a 0 to the address port can apparently
* confuse some bridges and cause spurious
* access failures.
*/
break;
case CFGMECH_2:
outb(CONF2_ENABLE_PORT, 0);
outb(CONF2_FORWARD_PORT, 0);
break;
}
}