cxgbe/iw_cxgbe: Replace a magic constant with something more readable

(and accurate).

T4 and later have an extra bit for page shift so the maximum page size
is 8TB (shift of 12 + 31) instead of 128MB (12 + 15).  This saves space
in the chip's PBL (physical buffer list) when registering very large
memory regions.

MFC after:	3 days
Sponsored by:	Chelsio Communications

sys/dev/cxgbe/iw_cxgbe/mem.c

@@ -345,7 +345,8 @@ static int build_phys_page_list(struct ib_phys_buf *buffer_list,
 	}
 
 	/* Find largest page shift we can use to cover buffers */
-	for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift))
+	for (*shift = PAGE_SHIFT; *shift < PAGE_SHIFT + M_FW_RI_TPTE_PS;
+	    ++(*shift))
 		if ((1ULL << *shift) & mask)
 			break;