Remove MACHINE_ARCH arm where appropriate from the tables to reflect armv5's
retirement.
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parent
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commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=356265
@ -26,7 +26,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd November 20, 2019
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.Dd January 2, 2020
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.Dt ARCH 7
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.Os
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.Sh NAME
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@ -199,8 +199,8 @@ Machine-dependent type sizes:
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.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
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.It aarch64 Ta 8 Ta 16 Ta 8
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.It amd64 Ta 8 Ta 16 Ta 8
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.It arm Ta 4 Ta 8 Ta 8
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.It armv6 Ta 4 Ta 8 Ta 8
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.It armv7 Ta 4 Ta 8 Ta 8
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.It i386 Ta 4 Ta 12 Ta 4
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.It mips Ta 4 Ta 8 Ta 8
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.It mipsel Ta 4 Ta 8 Ta 8
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@ -226,7 +226,6 @@ is 8 bytes on all supported architectures except i386.
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.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
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.It aarch64 Ta little Ta unsigned
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.It amd64 Ta little Ta signed
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.It arm Ta little Ta unsigned
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.It armv6 Ta little Ta unsigned
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.It armv7 Ta little Ta unsigned
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.It i386 Ta little Ta signed
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@ -251,7 +250,6 @@ is 8 bytes on all supported architectures except i386.
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.It Sy Architecture Ta Sy Page Sizes
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.It aarch64 Ta 4K, 2M, 1G
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.It amd64 Ta 4K, 2M, 1G
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.It arm Ta 4K
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.It armv6 Ta 4K, 1M
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.It armv7 Ta 4K, 1M
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.It i386 Ta 4K, 2M (PAE), 4M
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@ -276,7 +274,6 @@ is 8 bytes on all supported architectures except i386.
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.It Sy Architecture Ta Sy float, double Ta Sy long double
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.It aarch64 Ta hard Ta soft, quad precision
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.It amd64 Ta hard Ta hard, 80 bit
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.It arm Ta soft Ta soft, double precision
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.It armv6 Ta hard Ta hard, double precision
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.It armv7 Ta hard Ta hard, double precision
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.It i386 Ta hard Ta hard, 80 bit
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@ -313,7 +310,6 @@ This table shows the default tool chain for each architecture.
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.It Sy Architecture Ta Sy Compiler Ta Sy Linker
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.It aarch64 Ta Clang Ta lld
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.It amd64 Ta Clang Ta lld
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.It arm Ta Clang Ta GNU ld 2.17.50
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.It armv6 Ta Clang Ta lld
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.It armv7 Ta Clang Ta lld
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.It i386 Ta Clang Ta lld
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@ -360,7 +356,7 @@ or similar things like boot sequences.
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.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
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.It arm64 Ta aarch64 Ta aarch64
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.It amd64 Ta amd64 Ta amd64
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.It arm Ta arm Ta arm, armv6, armv7
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.It arm Ta arm Ta armv6, armv7
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.It i386 Ta i386 Ta i386
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.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
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.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64
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@ -394,7 +390,6 @@ Architecture-specific macros:
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.It Sy Architecture Ta Sy Predefined macros
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.It aarch64 Ta Dv __aarch64__
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.It amd64 Ta Dv __amd64__, Dv __x86_64__
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.It arm Ta Dv __arm__
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.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
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.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
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.It i386 Ta Dv __i386__
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@ -484,7 +479,7 @@ combinations encoding pointer size, endian and hard versus soft float (for
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all these).
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Generally, the plain CPU name specifies the most common (or at least
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first) variant of the CPU.
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This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7'
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This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7'
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imply little endian.
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If we ever were to support the so-called x32 ABI (using 32-bit
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pointers on the amd64 architecture), it would most likely be encoded
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