x86: Fetch and save standard CPUID leaf 6 in identcpu
Rather than a few scattered places in the tree. Organize flag names in a contiguous region of specialreg.h. While here, delete deprecated PCOMMIT from leaf 7. No functional change.
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869fe6d515
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=353712
@ -183,21 +183,6 @@
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#define CPUID2_RDRAND 0x40000000
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#define CPUID2_HV 0x80000000
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/*
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* Important bits in the Thermal and Power Management flags
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* CPUID.6 EAX and ECX.
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*/
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#define CPUTPM1_SENSOR 0x00000001
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#define CPUTPM1_TURBO 0x00000002
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#define CPUTPM1_ARAT 0x00000004
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#define CPUTPM1_HWP 0x00000080
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#define CPUTPM1_HWP_NOTIFICATION 0x00000100
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#define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
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#define CPUTPM1_HWP_PERF_PREF 0x00000400
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#define CPUTPM1_HWP_PKG 0x00000800
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#define CPUTPM1_HWP_FLEXIBLE 0x00020000
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#define CPUTPM2_EFFREQ 0x00000001
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/* Intel Processor Trace CPUID. */
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/* Leaf 0 ebx. */
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@ -326,10 +311,34 @@
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#define MWAIT_INTRBREAK 0x00000001
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/*
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* CPUID instruction 6 ecx info
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* CPUID leaf 6: Thermal and Power management.
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*/
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#define CPUID_PERF_STAT 0x00000001
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#define CPUID_PERF_BIAS 0x00000008
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/* Eax. */
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#define CPUTPM1_SENSOR 0x00000001
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#define CPUTPM1_TURBO 0x00000002
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#define CPUTPM1_ARAT 0x00000004
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#define CPUTPM1_PLN 0x00000010
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#define CPUTPM1_ECMD 0x00000020
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#define CPUTPM1_PTM 0x00000040
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#define CPUTPM1_HWP 0x00000080
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#define CPUTPM1_HWP_NOTIFICATION 0x00000100
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#define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
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#define CPUTPM1_HWP_PERF_PREF 0x00000400
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#define CPUTPM1_HWP_PKG 0x00000800
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#define CPUTPM1_HDC 0x00002000
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#define CPUTPM1_TURBO30 0x00004000
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#define CPUTPM1_HWP_CAPABILITIES 0x00008000
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#define CPUTPM1_HWP_PECI_OVR 0x00010000
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#define CPUTPM1_HWP_FLEXIBLE 0x00020000
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#define CPUTPM1_HWP_FAST_MSR 0x00040000
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#define CPUTPM1_HWP_IGN_IDLE 0x00100000
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/* Ebx. */
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#define CPUTPM_B_NSENSINTTHRESH 0x0000000f
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/* Ecx. */
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#define CPUID_PERF_STAT 0x00000001
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#define CPUID_PERF_BIAS 0x00000008
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/*
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* CPUID instruction 0xb ebx info.
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@ -419,7 +428,7 @@
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#define CPUID_STDEXT_ADX 0x00080000
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#define CPUID_STDEXT_SMAP 0x00100000
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#define CPUID_STDEXT_AVX512IFMA 0x00200000
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#define CPUID_STDEXT_PCOMMIT 0x00400000
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/* Formerly PCOMMIT */
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#define CPUID_STDEXT_CLFLUSHOPT 0x00800000
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#define CPUID_STDEXT_CLWB 0x01000000
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#define CPUID_STDEXT_PROCTRACE 0x02000000
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@ -67,6 +67,10 @@ extern u_int cpu_mon_mwait_flags;
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extern u_int cpu_mon_min_size;
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extern u_int cpu_mon_max_size;
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extern u_int cpu_maxphyaddr;
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extern u_int cpu_power_eax;
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extern u_int cpu_power_ebx;
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extern u_int cpu_power_ecx;
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extern u_int cpu_power_edx;
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extern char ctx_switch_xsave[];
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extern u_int hv_base;
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extern u_int hv_high;
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@ -118,6 +118,10 @@ u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
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u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
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u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
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u_int cpu_maxphyaddr; /* Max phys addr width in bits */
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u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
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u_int cpu_power_ebx; /* 06H: Power management leaf, %eax */
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u_int cpu_power_ecx; /* 06H: Power management leaf, %eax */
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u_int cpu_power_edx; /* 06H: Power management leaf, %eax */
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char machine[] = MACHINE;
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SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
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@ -960,7 +964,8 @@ printcpuinfo(void)
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/* Supervisor Mode Access Prevention */
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"\025SMAP"
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"\026AVX512IFMA"
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"\027PCOMMIT"
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/* Formerly PCOMMIT */
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"\027<b22>"
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"\030CLFLUSHOPT"
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"\031CLWB"
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"\032PROCTRACE"
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@ -1551,6 +1556,14 @@ identify_cpu2(void)
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{
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u_int regs[4], cpu_stdext_disable;
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if (cpu_high >= 6) {
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cpuid_count(6, 0, regs);
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cpu_power_eax = regs[0];
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cpu_power_ebx = regs[1];
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cpu_power_ecx = regs[2];
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cpu_power_edx = regs[3];
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}
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if (cpu_high >= 7) {
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cpuid_count(7, 0, regs);
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cpu_stdext_feature = regs[1];
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@ -480,8 +480,8 @@ native_lapic_init(vm_paddr_t addr)
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uint64_t r, r1, r2, rx;
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#endif
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uint32_t ver;
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u_int regs[4];
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int i, arat;
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int i;
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bool arat;
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/*
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* Enable x2APIC mode if possible. Map the local APIC
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@ -526,16 +526,9 @@ native_lapic_init(vm_paddr_t addr)
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SDT_APIC, SEL_KPL, GSEL_APIC);
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if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) {
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arat = 0;
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/* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */
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if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) {
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do_cpuid(0x06, regs);
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if ((regs[0] & CPUTPM1_ARAT) != 0)
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arat = 1;
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} else if (cpu_vendor_id == CPU_VENDOR_AMD &&
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CPUID_TO_FAMILY(cpu_id) >= 0x12) {
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arat = 1;
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}
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/* Set if APIC timer runs in C3. */
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arat = (cpu_power_eax & CPUTPM1_ARAT);
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bzero(&lapic_et, sizeof(lapic_et));
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lapic_et.et_name = "LAPIC";
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lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
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@ -232,20 +232,16 @@ probe_tsc_freq(void)
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uint64_t tsc1, tsc2;
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uint16_t bootflags;
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if (cpu_high >= 6) {
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do_cpuid(6, regs);
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if ((regs[2] & CPUID_PERF_STAT) != 0) {
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/*
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* XXX Some emulators expose host CPUID without actual
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* support for these MSRs. We must test whether they
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* really work.
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*/
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wrmsr(MSR_MPERF, 0);
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wrmsr(MSR_APERF, 0);
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DELAY(10);
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if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
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tsc_perf_stat = 1;
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}
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if (cpu_power_ecx & CPUID_PERF_STAT) {
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/*
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* XXX Some emulators expose host CPUID without actual support
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* for these MSRs. We must test whether they really work.
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*/
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wrmsr(MSR_MPERF, 0);
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wrmsr(MSR_APERF, 0);
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DELAY(10);
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if (rdmsr(MSR_MPERF) > 0 && rdmsr(MSR_APERF) > 0)
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tsc_perf_stat = 1;
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}
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if (vm_guest == VM_GUEST_VMWARE) {
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