Whitespace cleanup:
o Wrap sentences on to new lines o Rewrap lines where possible while trying to keep the diff to a minimum Found with: textproc/igor MFC after: 1 week X-MFC-With: r232157
This commit is contained in:
Glen Barber
parent
9d496f5ab6
commit
bb374ac283
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=232159
@ -92,15 +92,17 @@ Configure the Off-core Response bits.
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.It Li DMND_DATA_RD
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Counts the number of demand and DCU prefetch data reads of full
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and partial cachelines as well as demand data page table entry
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cacheline reads. Does not count L2 data read prefetches or
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cacheline reads.
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Does not count L2 data read prefetches or
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instruction fetches.
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.It Li DMND_RFO
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Counts the number of demand and DCU prefetch reads for ownership
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(RFO) requests generated by a write to data cacheline. Does not
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count L2 RFO.
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(RFO) requests generated by a write to data cacheline.
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Does not count L2 RFO.
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.It Li DMND_IFETCH
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Counts the number of demand and DCU prefetch instruction cacheline
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reads. Does not count L2 code read prefetches.
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reads.
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Does not count L2 code read prefetches.
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WB
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Counts the number of writeback (modified to exclusive) transactions.
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.It Li PF_DATA_RD
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@ -181,7 +183,8 @@ All Store buffer stall cycles
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All store referenced with misaligned address
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.It Li STORE_BLOCKS.AT_RET
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.Pq Event 06H , Umask 04H
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Counts number of loads delayed with at-Retirement block code. The following
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Counts number of loads delayed with at-Retirement block code.
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The following
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loads need to be executed at retirement and wait for all senior stores on
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the same thread to be drained: load splitting across 4K boundary (page
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split), load accessing uncacheable (UC or USWC) memory, load lock, and load
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@ -225,9 +228,10 @@ ld_lat facility.
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In conjunction with ld_lat facility
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.It Li MEM_STORE_RETIRED.DTLB_MISS
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.Pq Event 0CH , Umask 01H
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The event counts the number of retired stores that missed the DTLB. The DTLB
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miss is not counted if the store operation causes a fault. Does not counter
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prefetches. Counts both primary and secondary misses to the TLB
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The event counts the number of retired stores that missed the DTLB.
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The DTLB miss is not counted if the store operation causes a fault.
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Does not counter prefetches.
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Counts both primary and secondary misses to the TLB
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.It Li UOPS_ISSUED.ANY
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.Pq Event 0EH , Umask 01H
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Counts the number of Uops issued by the Register Allocation Table to the
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@ -264,9 +268,11 @@ Load instructions retired remote DRAM and remote home-remote cache HITM
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Load instructions retired I/O (Precise Event)
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.It Li FP_COMP_OPS_EXE.X87
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.Pq Event 10H , Umask 01H
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Counts the number of FP Computational Uops Executed. The number of FADD,
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Counts the number of FP Computational Uops Executed.
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The number of FADD,
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FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer
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DIVs, and IDIVs. This event does not distinguish an FADD used in the middle
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DIVs, and IDIVs.
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This event does not distinguish an FADD used in the middle
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of a transcendental flow from a separate FADD instruction.
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.It Li FP_COMP_OPS_EXE.MMX
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.Pq Event 10H , Umask 02H
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@ -316,9 +322,9 @@ Counts number of loads dispatched from the Reservation Station that bypass
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the Memory Order Buffer.
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.It Li LOAD_DISPATCH.RS_DELAYED
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.Pq Event 13H , Umask 02H
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Counts the number of delayed RS dispatches at the stage latch. If an RS
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dispatch can not bypass to LB, it has another chance to dispatch from the
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one-cycle delayed staging latch before it is written into the LB.
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Counts the number of delayed RS dispatches at the stage latch.
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If an RS dispatch can not bypass to LB, it has another chance to dispatch
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from the one-cycle delayed staging latch before it is written into the LB.
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.It Li LOAD_DISPATCH.MOB
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.Pq Event 13H , Umask 04H
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Counts the number of loads dispatched from the Reservation Station to the
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@ -329,13 +335,15 @@ Counts all loads dispatched from the Reservation Station.
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.It Li ARITH.CYCLES_DIV_BUSY
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.Pq Event 14H , Umask 01H
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Counts the number of cycles the divider is busy executing divide or square
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root operations. The divide can be integer, X87 or Streaming SIMD Extensions
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(SSE). The square root operation can be either X87 or SSE.
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root operations.
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The divide can be integer, X87 or Streaming SIMD Extensions (SSE).
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The square root operation can be either X87 or SSE.
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Set 'edge =1, invert=1, cmask=1' to count the number of divides.
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Count may be incorrect When SMT is on
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.It Li ARITH.MUL
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.Pq Event 14H , Umask 02H
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Counts the number of multiply operations executed. This includes integer as
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Counts the number of multiply operations executed.
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This includes integer as
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well as floating point multiply operations but excludes DPPS mul and MPSAD.
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Count may be incorrect When SMT is on
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.It Li INST_QUEUE_WRITES
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@ -344,64 +352,72 @@ Counts the number of instructions written into the instruction queue every
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cycle.
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.It Li INST_DECODED.DEC0
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.Pq Event 18H , Umask 01H
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Counts number of instructions that require decoder 0 to be decoded. Usually,
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this means that the instruction maps to more than 1 uop
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Counts number of instructions that require decoder 0 to be decoded.
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Usually, this means that the instruction maps to more than 1 uop
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.It Li TWO_UOP_INSTS_DECODED
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.Pq Event 19H , Umask 01H
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An instruction that generates two uops was decoded
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.It Li INST_QUEUE_WRITE_CYCLES
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.Pq Event 1EH , Umask 01H
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This event counts the number of cycles during which instructions are written
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to the instruction queue. Dividing this counter by the number of
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to the instruction queue.
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Dividing this counter by the number of
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instructions written to the instruction queue (INST_QUEUE_WRITES) yields the
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average number of instructions decoded each cycle. If this number is less
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average number of instructions decoded each cycle.
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If this number is less
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than four and the pipe stalls, this indicates that the decoder is failing to
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decode enough instructions per cycle to sustain the 4-wide pipeline.
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If SSE* instructions that are 6 bytes or longer arrive one after another,
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then front end throughput may limit execution speed. In such case,
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then front end throughput may limit execution speed.
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In such case,
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.It Li LSD_OVERFLOW
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.Pq Event 20H , Umask 01H
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Number of loops that can not stream from the instruction queue.
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.It Li L2_RQSTS.LD_HIT
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.Pq Event 24H , Umask 01H
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Counts number of loads that hit the L2 cache. L2 loads include both L1D
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demand misses as well as L1D prefetches. L2 loads can be rejected for
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various reasons. Only non rejected loads are counted.
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Counts number of loads that hit the L2 cache.
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L2 loads include both L1D demand misses as well as L1D prefetches.
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L2 loads can be rejected for various reasons.
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Only non rejected loads are counted.
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.It Li L2_RQSTS.LD_MISS
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.Pq Event 24H , Umask 02H
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Counts the number of loads that miss the L2 cache. L2 loads include both L1D
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demand misses as well as L1D prefetches.
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Counts the number of loads that miss the L2 cache.
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L2 loads include both L1D demand misses as well as L1D prefetches.
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.It Li L2_RQSTS.LOADS
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.Pq Event 24H , Umask 03H
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Counts all L2 load requests. L2 loads include both L1D demand misses as well
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as L1D prefetches.
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Counts all L2 load requests.
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L2 loads include both L1D demand misses as well as L1D prefetches.
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.It Li L2_RQSTS.RFO_HIT
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.Pq Event 24H , Umask 04H
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Counts the number of store RFO requests that hit the L2 cache. L2 RFO
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requests include both L1D demand RFO misses as well as L1D RFO prefetches.
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Counts the number of store RFO requests that hit the L2 cache.
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L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
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prefetches.
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Count includes WC memory requests, where the data is not fetched but the
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permission to write the line is required.
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.It Li L2_RQSTS.RFO_MISS
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.Pq Event 24H , Umask 08H
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Counts the number of store RFO requests that miss the L2 cache. L2 RFO
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requests include both L1D demand RFO misses as well as L1D RFO prefetches.
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Counts the number of store RFO requests that miss the L2 cache.
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L2 RFO requests include both L1D demand RFO misses as well as L1D RFO
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prefetches.
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.It Li L2_RQSTS.RFOS
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.Pq Event 24H , Umask 0CH
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Counts all L2 store RFO requests. L2 RFO requests include both L1D demand
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Counts all L2 store RFO requests.
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L2 RFO requests include both L1D demand
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RFO misses as well as L1D RFO prefetches.
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.It Li L2_RQSTS.IFETCH_HIT
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.Pq Event 24H , Umask 10H
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Counts number of instruction fetches that hit the L2 cache. L2 instruction
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fetches include both L1I demand misses as well as L1I instruction
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prefetches.
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Counts number of instruction fetches that hit the L2 cache.
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L2 instruction fetches include both L1I demand misses as well as L1I
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instruction prefetches.
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.It Li L2_RQSTS.IFETCH_MISS
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.Pq Event 24H , Umask 20H
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Counts number of instruction fetches that miss the L2 cache. L2 instruction
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fetches include both L1I demand misses as well as L1I instruction
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prefetches.
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Counts number of instruction fetches that miss the L2 cache.
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L2 instruction fetches include both L1I demand misses as well as L1I
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instruction prefetches.
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.It Li L2_RQSTS.IFETCHES
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.Pq Event 24H , Umask 30H
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Counts all instruction fetches. L2 instruction fetches include both L1I
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Counts all instruction fetches.
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L2 instruction fetches include both L1I
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demand misses as well as L1I instruction prefetches.
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.It Li L2_RQSTS.PREFETCH_HIT
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.Pq Event 24H , Umask 40H
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@ -421,26 +437,30 @@ Counts all L2 requests for both code and data.
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.It Li L2_DATA_RQSTS.DEMAND.I_STATE
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.Pq Event 26H , Umask 01H
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Counts number of L2 data demand loads where the cache line to be loaded is
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in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D
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demand misses and L1D prefetches.
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in the I (invalid) state, i.e. a cache miss.
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L2 demand loads are both L1D demand misses and L1D prefetches.
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.It Li L2_DATA_RQSTS.DEMAND.S_STATE
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.Pq Event 26H , Umask 02H
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Counts number of L2 data demand loads where the cache line to be loaded is
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in the S (shared) state. L2 demand loads are both L1D demand misses and L1D
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in the S (shared) state.
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L2 demand loads are both L1D demand misses and L1D
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prefetches.
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.It Li L2_DATA_RQSTS.DEMAND.E_STATE
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.Pq Event 26H , Umask 04H
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Counts number of L2 data demand loads where the cache line to be loaded is
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in the E (exclusive) state. L2 demand loads are both L1D demand misses and
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in the E (exclusive) state.
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L2 demand loads are both L1D demand misses and
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L1D prefetches.
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.It Li L2_DATA_RQSTS.DEMAND.M_STATE
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.Pq Event 26H , Umask 08H
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Counts number of L2 data demand loads where the cache line to be loaded is
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in the M (modified) state. L2 demand loads are both L1D demand misses and
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in the M (modified) state.
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L2 demand loads are both L1D demand misses and
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L1D prefetches.
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.It Li L2_DATA_RQSTS.DEMAND.MESI
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.Pq Event 26H , Umask 0FH
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Counts all L2 data demand requests. L2 demand loads are both L1D demand
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Counts all L2 data demand requests.
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L2 demand loads are both L1D demand
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misses and L1D prefetches.
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.It Li L2_DATA_RQSTS.PREFETCH.I_STATE
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.Pq Event 26H , Umask 10H
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@ -449,7 +469,8 @@ in the I (invalid) state, i.e. a cache miss.
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.It Li L2_DATA_RQSTS.PREFETCH.S_STATE
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.Pq Event 26H , Umask 20H
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Counts number of L2 prefetch data loads where the cache line to be loaded is
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in the S (shared) state. A prefetch RFO will miss on an S state line, while
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in the S (shared) state.
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A prefetch RFO will miss on an S state line, while
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a prefetch read will hit on an S state line.
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.It Li L2_DATA_RQSTS.PREFETCH.E_STATE
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.Pq Event 26H , Umask 40H
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@ -468,23 +489,27 @@ Counts all L2 data requests.
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.It Li L2_WRITE.RFO.I_STATE
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.Pq Event 27H , Umask 01H
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Counts number of L2 demand store RFO requests where the cache line to be
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loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher
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loaded is in the I (invalid) state, i.e, a cache miss.
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The L1D prefetcher
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does not issue a RFO prefetch.
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This is a demand RFO request
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.It Li L2_WRITE.RFO.S_STATE
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.Pq Event 27H , Umask 02H
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Counts number of L2 store RFO requests where the cache line to be loaded is
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in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch.
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in the S (shared) state.
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The L1D prefetcher does not issue a RFO prefetch.
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This is a demand RFO request.
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.It Li L2_WRITE.RFO.M_STATE
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.Pq Event 27H , Umask 08H
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Counts number of L2 store RFO requests where the cache line to be loaded is
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in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch.
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in the M (modified) state.
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The L1D prefetcher does not issue a RFO prefetch.
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This is a demand RFO request.
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.It Li L2_WRITE.RFO.HIT
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.Pq Event 27H , Umask 0EH
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Counts number of L2 store RFO requests where the cache line to be loaded is
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in either the S, E or M states. The L1D prefetcher does not issue a RFO
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in either the S, E or M states.
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The L1D prefetcher does not issue a RFO
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prefetch.
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This is a demand RFO request
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.It Li L2_WRITE.RFO.MESI
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@ -536,21 +561,23 @@ is in the M (modified) state.
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Counts all L1 writebacks to the L2.
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.It Li L3_LAT_CACHE.REFERENCE
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.Pq Event 2EH , Umask 02H
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Counts uncore Last Level Cache references. Because cache hierarchy, cache
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Counts uncore Last Level Cache references.
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Because cache hierarchy, cache
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sizes and other implementation-specific characteristics; value comparison to
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estimate performance differences is not recommended.
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See Table A-1.
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.It Li L3_LAT_CACHE.MISS
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.Pq Event 2EH , Umask 01H
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Counts uncore Last Level Cache misses. Because cache hierarchy, cache sizes
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Counts uncore Last Level Cache misses.
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Because cache hierarchy, cache sizes
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and other implementation-specific characteristics; value comparison to
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estimate performance differences is not recommended.
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See Table A-1.
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.It Li CPU_CLK_UNHALTED.THREAD_P
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.Pq Event 3CH , Umask 00H
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Counts the number of thread cycles while the thread is not in a halt state.
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The thread enters the halt state when it is running the HLT instruction. The
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core frequency may change from time to time due to power or thermal
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The thread enters the halt state when it is running the HLT instruction.
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The core frequency may change from time to time due to power or thermal
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throttling.
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see Table A-1
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.It Li CPU_CLK_UNHALTED.REF_P
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@ -569,7 +596,8 @@ Counts cycles of page walk due to misses in the STLB.
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.It Li DTLB_MISSES.STLB_HIT
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.Pq Event 49H , Umask 10H
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Counts the number of DTLB first level misses that hit in the second level
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TLB. This event is only relevant if the core contains multiple DTLB levels.
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TLB.
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This event is only relevant if the core contains multiple DTLB levels.
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.It Li DTLB_MISSES.LARGE_WALK_COMPLETED
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.Pq Event 49H , Umask 80H
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Counts number of completed large page walks due to misses in the STLB.
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@ -584,17 +612,22 @@ Counts number of hardware prefetch requests dispatched out of the prefetch
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FIFO.
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.It Li L1D_PREFETCH.MISS
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.Pq Event 4EH , Umask 02H
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Counts number of hardware prefetch requests that miss the L1D. There are two
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prefetchers in the L1D. A streamer, which predicts lines sequentially after
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Counts number of hardware prefetch requests that miss the L1D.
|
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There are two
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prefetchers in the L1D.
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A streamer, which predicts lines sequentially after
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this one should be fetched, and the IP prefetcher that remembers access
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patterns for the current instruction. The streamer prefetcher stops on an
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patterns for the current instruction.
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The streamer prefetcher stops on an
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L1D hit, while the IP prefetcher does not.
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.It Li L1D_PREFETCH.TRIGGERS
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.Pq Event 4EH , Umask 04H
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Counts number of prefetch requests triggered by the Finite State Machine and
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pushed into the prefetch FIFO. Some of the prefetch requests are dropped due
|
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pushed into the prefetch FIFO.
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Some of the prefetch requests are dropped due
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to overwrites or competition between the IP index prefetcher and streamer
|
||||
prefetcher. The prefetch FIFO contains 4 entries.
|
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prefetcher.
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The prefetch FIFO contains 4 entries.
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.It Li EPT.WALK_CYCLES
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.Pq Event 4FH , Umask 10H
|
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Counts Extended Page walk cycles.
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@ -626,31 +659,33 @@ Counts the number of cacheable load lock speculated or retired instructions
|
||||
accepted into the fill buffer.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA
|
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.Pq Event 60H , Umask 01H
|
||||
Counts weighted cycles of offcore demand data read requests. Does not
|
||||
include L2 prefetch requests.
|
||||
Counts weighted cycles of offcore demand data read requests.
|
||||
Does not include L2 prefetch requests.
|
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Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE
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.Pq Event 60H , Umask 02H
|
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Counts weighted cycles of offcore demand code read requests. Does not
|
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include L2 prefetch requests.
|
||||
Counts weighted cycles of offcore demand code read requests.
|
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Does not include L2 prefetch requests.
|
||||
Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO
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.Pq Event 60H , Umask 04H
|
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Counts weighted cycles of offcore demand RFO requests. Does not include L2
|
||||
prefetch requests.
|
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Counts weighted cycles of offcore demand RFO requests.
|
||||
Does not include L2 prefetch requests.
|
||||
Counter 0.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ
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.Pq Event 60H , Umask 08H
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Counts weighted cycles of offcore read requests of any kind. Include L2
|
||||
prefetch requests.
|
||||
Counts weighted cycles of offcore read requests of any kind.
|
||||
Include L2 prefetch requests.
|
||||
Counter 0.
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.It Li CACHE_LOCK_CYCLES.L1D_L2
|
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.Pq Event 63H , Umask 01H
|
||||
Cycle count during which the L1D and L2 are locked. A lock is asserted when
|
||||
Cycle count during which the L1D and L2 are locked.
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||||
A lock is asserted when
|
||||
there is a locked memory access, due to uncacheable memory, a locked
|
||||
operation that spans two cache lines, or a page walk from an uncacheable
|
||||
page table.
|
||||
Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and
|
||||
Counter 0, 1 only.
|
||||
L1D and L2 locks have a very high performance penalty and
|
||||
it is highly recommended to avoid such accesses.
|
||||
.It Li CACHE_LOCK_CYCLES.L1D
|
||||
.Pq Event 63H , Umask 02H
|
||||
@ -665,9 +700,11 @@ Counts the number of completed I/O transactions.
|
||||
Counts all instruction fetches that hit the L1 instruction cache.
|
||||
.It Li L1I.MISSES
|
||||
.Pq Event 80H , Umask 02H
|
||||
Counts all instruction fetches that miss the L1I cache. This includes
|
||||
Counts all instruction fetches that miss the L1I cache.
|
||||
This includes
|
||||
instruction cache misses, streaming buffer misses, victim cache misses and
|
||||
uncacheable fetches. An instruction fetch miss is counted only once and not
|
||||
uncacheable fetches.
|
||||
An instruction fetch miss is counted only once and not
|
||||
once for every cycle it is outstanding.
|
||||
.It Li L1I.READS
|
||||
.Pq Event 80H , Umask 03H
|
||||
@ -747,10 +784,10 @@ Counts all near call branches executed, but not necessarily retired.
|
||||
Counts taken near branches executed, but not necessarily retired.
|
||||
.It Li BR_INST_EXEC.ANY
|
||||
.Pq Event 88H , Umask 7FH
|
||||
Counts all near executed branches (not necessarily retired). This includes
|
||||
only instructions and not micro-op branches. Frequent branching is not
|
||||
necessarily a major performance issue. However frequent branch
|
||||
mispredictions may be a problem.
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
This includes only instructions and not micro-op branches.
|
||||
Frequent branching is not necessarily a major performance issue.
|
||||
However frequent branch mispredictions may be a problem.
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Counts the number of mispredicted conditional near branch instructions
|
||||
@ -791,9 +828,10 @@ Counts the number of mispredicted near branch instructions that were
|
||||
executed, but not necessarily retired.
|
||||
.It Li RESOURCE_STALLS.ANY
|
||||
.Pq Event A2H , Umask 01H
|
||||
Counts the number of Allocator resource related stalls. Includes register
|
||||
renaming buffer entries, memory buffer entries. In addition to resource
|
||||
related stalls, this event counts some other events. Includes stalls arising
|
||||
Counts the number of Allocator resource related stalls.
|
||||
Includes register renaming buffer entries, memory buffer entries.
|
||||
In addition to resource related stalls, this event counts some other events.
|
||||
Includes stalls arising
|
||||
during branch misprediction recovery, such as if retirement of the
|
||||
mispredicted branch is delayed and stalls arising while store buffer is
|
||||
draining from synchronizing operations.
|
||||
@ -806,7 +844,8 @@ Counts the cycles of stall due to lack of load buffer for load operation.
|
||||
.Pq Event A2H , Umask 04H
|
||||
This event counts the number of cycles when the number of instructions in
|
||||
the pipeline waiting for execution reaches the limit the processor can
|
||||
handle. A high count of this event indicates that there are long latency
|
||||
handle.
|
||||
A high count of this event indicates that there are long latency
|
||||
operations in the pipe (possibly load and store operations that miss the L2
|
||||
cache, or instructions dependent upon instructions further down the pipeline
|
||||
that have yet to retire.
|
||||
@ -816,7 +855,8 @@ start execution.
|
||||
.Pq Event A2H , Umask 08H
|
||||
This event counts the number of cycles that a resource related stall will
|
||||
occur due to the number of store instructions reaching the limit of the
|
||||
pipeline, (i.e. all store buffers are used). The stall ends when a store
|
||||
pipeline, (i.e. all store buffers are used).
|
||||
The stall ends when a store
|
||||
instruction commits its data to the cache or memory.
|
||||
.It Li RESOURCE_STALLS.ROB_FULL
|
||||
.Pq Event A2H , Umask 10H
|
||||
@ -828,7 +868,8 @@ floating-point unit (FPU) control word.
|
||||
.It Li RESOURCE_STALLS.MXCSR
|
||||
.Pq Event A2H , Umask 40H
|
||||
Stalls due to the MXCSR register rename occurring to close to a previous
|
||||
MXCSR rename. The MXCSR provides control and status for the MMX registers.
|
||||
MXCSR rename.
|
||||
The MXCSR provides control and status for the MMX registers.
|
||||
.It Li RESOURCE_STALLS.OTHER
|
||||
.Pq Event A2H , Umask 80H
|
||||
Counts the number of cycles while execution was stalled due to other
|
||||
@ -839,12 +880,14 @@ Counts the number of instructions decoded that are macro-fused but not
|
||||
necessarily executed or retired.
|
||||
.It Li BACLEAR_FORCE_IQ
|
||||
.Pq Event A7H , Umask 01H
|
||||
Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ
|
||||
is also responsible for providing conditional branch prediction direction
|
||||
based on a static scheme and dynamic data provided by the L2 Branch
|
||||
Prediction Unit. If the conditional branch target is not found in the Target
|
||||
Counts number of times a BACLEAR was forced by the Instruction Queue.
|
||||
The IQ is also responsible for providing conditional branch prediction
|
||||
direction based on a static scheme and dynamic data provided by the L2
|
||||
Branch Prediction Unit.
|
||||
If the conditional branch target is not found in the Target
|
||||
Array and the IQ predicts that the branch is taken, then the IQ will force
|
||||
the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by
|
||||
the Branch Address Calculator to issue a BACLEAR.
|
||||
Each BACLEAR asserted by
|
||||
the BAC generates approximately an 8 cycle bubble in the instruction fetch
|
||||
pipeline.
|
||||
.It Li LSD.UOPS
|
||||
@ -856,22 +899,24 @@ Use cmask=1 and invert to count cycles
|
||||
Counts the number of ITLB flushes
|
||||
.It Li OFFCORE_REQUESTS.DEMAND.READ_DATA
|
||||
.Pq Event B0H , Umask 01H
|
||||
Counts number of offcore demand data read requests. Does not count L2
|
||||
prefetch requests.
|
||||
Counts number of offcore demand data read requests.
|
||||
Does not count L2 prefetch requests.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE
|
||||
.Pq Event B0H , Umask 02H
|
||||
Counts number of offcore demand code read requests. Does not count L2
|
||||
prefetch requests.
|
||||
Counts number of offcore demand code read requests.
|
||||
Does not count L2 prefetch requests.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND.RFO
|
||||
.Pq Event B0H , Umask 04H
|
||||
Counts number of offcore demand RFO requests. Does not count L2 prefetch
|
||||
requests.
|
||||
Counts number of offcore demand RFO requests.
|
||||
Does not count L2 prefetch requests.
|
||||
.It Li OFFCORE_REQUESTS.ANY.READ
|
||||
.Pq Event B0H , Umask 08H
|
||||
Counts number of offcore read requests. Includes L2 prefetch requests.
|
||||
Counts number of offcore read requests.
|
||||
Includes L2 prefetch requests.
|
||||
.It Li OFFCORE_REQUESTS.ANY.RFO
|
||||
.Pq Event 80H , Umask 10H
|
||||
Counts number of offcore RFO requests. Includes L2 prefetch requests.
|
||||
Counts number of offcore RFO requests.
|
||||
Includes L2 prefetch requests.
|
||||
.It Li OFFCORE_REQUESTS.L1D_WRITEBACK
|
||||
.Pq Event B0H , Umask 40H
|
||||
Counts number of L1D writebacks to the uncore.
|
||||
@ -880,38 +925,42 @@ Counts number of L1D writebacks to the uncore.
|
||||
Counts all offcore requests.
|
||||
.It Li UOPS_EXECUTED.PORT0
|
||||
.Pq Event B1H , Umask 01H
|
||||
Counts number of Uops executed that were issued on port 0. Port 0 handles
|
||||
integer arithmetic, SIMD and FP add Uops.
|
||||
Counts number of Uops executed that were issued on port 0.
|
||||
Port 0 handles integer arithmetic, SIMD and FP add Uops.
|
||||
.It Li UOPS_EXECUTED.PORT1
|
||||
.Pq Event B1H , Umask 02H
|
||||
Counts number of Uops executed that were issued on port 1. Port 1 handles
|
||||
integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops.
|
||||
Counts number of Uops executed that were issued on port 1.
|
||||
Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and
|
||||
FP divide Uops.
|
||||
.It Li UOPS_EXECUTED.PORT2_CORE
|
||||
.Pq Event B1H , Umask 04H
|
||||
Counts number of Uops executed that were issued on port 2. Port 2 handles
|
||||
the load Uops. This is a core count only and can not be collected per
|
||||
Counts number of Uops executed that were issued on port 2.
|
||||
Port 2 handles the load Uops.
|
||||
This is a core count only and can not be collected per
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED.PORT3_CORE
|
||||
.Pq Event B1H , Umask 08H
|
||||
Counts number of Uops executed that were issued on port 3. Port 3 handles
|
||||
store Uops. This is a core count only and can not be collected per thread.
|
||||
Counts number of Uops executed that were issued on port 3.
|
||||
Port 3 handles store Uops.
|
||||
This is a core count only and can not be collected per thread.
|
||||
.It Li UOPS_EXECUTED.PORT4_CORE
|
||||
.Pq Event B1H , Umask 10H
|
||||
Counts number of Uops executed that where issued on port 4. Port 4 handles
|
||||
the value to be stored for the store Uops issued on port 3. This is a core
|
||||
count only and can not be collected per thread.
|
||||
Counts number of Uops executed that where issued on port 4.
|
||||
Port 4 handles the value to be stored for the store Uops issued on port 3.
|
||||
This is a core count only and can not be collected per thread.
|
||||
.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5
|
||||
.Pq Event B1H , Umask 1FH
|
||||
Counts number of cycles there are one or more uops being executed and were
|
||||
issued on ports 0-4. This is a core count only and can not be collected per
|
||||
thread.
|
||||
issued on ports 0-4.
|
||||
This is a core count only and can not be collected per thread.
|
||||
.It Li UOPS_EXECUTED.PORT5
|
||||
.Pq Event B1H , Umask 20H
|
||||
Counts number of Uops executed that where issued on port 5.
|
||||
.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES
|
||||
.Pq Event B1H , Umask 3FH
|
||||
Counts number of cycles there are one or more uops being executed on any
|
||||
ports. This is a core count only and can not be collected per thread.
|
||||
ports.
|
||||
This is a core count only and can not be collected per thread.
|
||||
.It Li UOPS_EXECUTED.PORT015
|
||||
.Pq Event B1H , Umask 40H
|
||||
Counts number of Uops executed that where issued on port 0, 1, or 5.
|
||||
@ -924,15 +973,18 @@ Counts number of Uops executed that where issued on port 2, 3, or 4.
|
||||
Counts number of cycles the SQ is full to handle off-core requests.
|
||||
.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA
|
||||
.Pq Event B3H , Umask 01H
|
||||
Counts weighted cycles of snoopq requests for data. Counter 0 only
|
||||
Counts weighted cycles of snoopq requests for data.
|
||||
Counter 0 only
|
||||
Use cmask=1 to count cycles not empty.
|
||||
.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE
|
||||
.Pq Event B3H , Umask 02H
|
||||
Counts weighted cycles of snoopq invalidate requests. Counter 0 only.
|
||||
Counts weighted cycles of snoopq invalidate requests.
|
||||
Counter 0 only.
|
||||
Use cmask=1 to count cycles not empty.
|
||||
.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE
|
||||
.Pq Event B3H , Umask 04H
|
||||
Counts weighted cycles of snoopq requests for code. Counter 0 only.
|
||||
Counts weighted cycles of snoopq requests for code.
|
||||
Counter 0 only.
|
||||
Use cmask=1 to count cycles not empty.
|
||||
.It Li SNOOPQ_REQUESTS.CODE
|
||||
.Pq Event B4H , Umask 01H
|
||||
@ -970,7 +1022,8 @@ Use MSR 01A7H.
|
||||
See Table A-1
|
||||
Notes: INST_RETIRED.ANY is counted by a designated fixed counter.
|
||||
INST_RETIRED.ANY_P is counted by a programmable counter and is an
|
||||
architectural performance event. Event is supported if CPUID.A.EBX[1] = 0.
|
||||
architectural performance event.
|
||||
Event is supported if CPUID.A.EBX[1] = 0.
|
||||
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not
|
||||
count as retired instructions.
|
||||
.It Li INST_RETIRED.X87
|
||||
@ -985,8 +1038,9 @@ Counts the number of retired: MMX instructions.
|
||||
.It Li UOPS_RETIRED.ANY
|
||||
.Pq Event C2H , Umask 01H
|
||||
Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
|
||||
others=1; maximum count of 8 per cycle). Most instructions are composed of
|
||||
one or two micro-ops. Some instructions are decoded into longer sequences
|
||||
others=1; maximum count of 8 per cycle).
|
||||
Most instructions are composed of one or two micro-ops.
|
||||
Some instructions are decoded into longer sequences
|
||||
such as repeat instructions, floating point transcendental instructions, and
|
||||
assists.
|
||||
Use cmask=1 and invert to count active cycles or stalled cycles
|
||||
@ -1006,7 +1060,8 @@ Counts the number of machine clears due to memory order conflicts.
|
||||
.Pq Event C3H , Umask 04H
|
||||
Counts the number of times that a program writes to a code section.
|
||||
Self-modifying code causes a sever penalty in all Intel 64 and IA-32
|
||||
processors. The modified cache line is written back to the L2 and L3caches.
|
||||
processors.
|
||||
The modified cache line is written back to the L2 and L3caches.
|
||||
.It Li BR_INST_RETIRED.ANY_P
|
||||
.Pq Event C4H , Umask 00H
|
||||
See Table A-1.
|
||||
@ -1063,23 +1118,25 @@ cache.
|
||||
.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM
|
||||
.Pq Event CBH , Umask 08H
|
||||
Counts number of retired loads that hit in a sibling core's L2 (on die
|
||||
core). Since the L3 is inclusive of all cores on the package, this is an L3
|
||||
hit. This counts both clean or modified hits.
|
||||
core).
|
||||
Since the L3 is inclusive of all cores on the package, this is an L3 hit.
|
||||
This counts both clean or modified hits.
|
||||
.It Li MEM_LOAD_RETIRED.L3_MISS
|
||||
.Pq Event CBH , Umask 10H
|
||||
Counts number of retired loads that miss the L3 cache. The load was
|
||||
satisfied by a remote socket, local memory or an IOH.
|
||||
Counts number of retired loads that miss the L3 cache.
|
||||
The load was satisfied by a remote socket, local memory or an IOH.
|
||||
.It Li MEM_LOAD_RETIRED.HIT_LFB
|
||||
.Pq Event CBH , Umask 40H
|
||||
Counts number of retired loads that miss the L1D and the address is located
|
||||
in an allocated line fill buffer and will soon be committed to cache. This
|
||||
is counting secondary L1D misses.
|
||||
in an allocated line fill buffer and will soon be committed to cache.
|
||||
This is counting secondary L1D misses.
|
||||
.It Li MEM_LOAD_RETIRED.DTLB_MISS
|
||||
.Pq Event CBH , Umask 80H
|
||||
Counts the number of retired loads that missed the DTLB. The DTLB miss is
|
||||
not counted if the load operation causes a fault. This event counts loads
|
||||
from cacheable memory only. The event does not count loads by software
|
||||
prefetches. Counts both primary and secondary misses to the TLB.
|
||||
Counts the number of retired loads that missed the DTLB.
|
||||
The DTLB miss is not counted if the load operation causes a fault.
|
||||
This event counts loads from cacheable memory only.
|
||||
The event does not count loads by software prefetches.
|
||||
Counts both primary and secondary misses to the TLB.
|
||||
.It Li FP_MMX_TRANS.TO_FP
|
||||
.Pq Event CCH , Umask 01H
|
||||
Counts the first floating-point instruction following any MMX instruction.
|
||||
@ -1087,15 +1144,15 @@ You can use this event to estimate the penalties for the transitions between
|
||||
floating-point and MMX technology states.
|
||||
.It Li FP_MMX_TRANS.TO_MMX
|
||||
.Pq Event CCH , Umask 02H
|
||||
Counts the first MMX instruction following a floating-point instruction. You
|
||||
can use this event to estimate the penalties for the transitions between
|
||||
Counts the first MMX instruction following a floating-point instruction.
|
||||
You can use this event to estimate the penalties for the transitions between
|
||||
floating-point and MMX technology states.
|
||||
.It Li FP_MMX_TRANS.ANY
|
||||
.Pq Event CCH , Umask 03H
|
||||
Counts all transitions from floating point to MMX instructions and from MMX
|
||||
instructions to floating point instructions. You can use this event to
|
||||
estimate the penalties for the transitions between floating-point and MMX
|
||||
technology states.
|
||||
instructions to floating point instructions.
|
||||
You can use this event to estimate the penalties for the transitions between
|
||||
floating-point and MMX technology states.
|
||||
.It Li MACRO_INSTS.DECODED
|
||||
.Pq Event D0H , Umask 01H
|
||||
Counts the number of instructions decoded, (but not necessarily executed or
|
||||
@ -1105,14 +1162,15 @@ retired).
|
||||
Counts the cycles of decoder stalls.
|
||||
.It Li UOPS_DECODED.MS
|
||||
.Pq Event D1H , Umask 02H
|
||||
Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS
|
||||
delivers uops when the instruction is more than 4 uops long or a microcode
|
||||
assist is occurring.
|
||||
Counts the number of Uops decoded by the Microcode Sequencer, MS.
|
||||
The MS delivers uops when the instruction is more than 4 uops long or a
|
||||
microcode assist is occurring.
|
||||
.It Li UOPS_DECODED.ESP_FOLDING
|
||||
.Pq Event D1H , Umask 04H
|
||||
Counts number of stack pointer (ESP) instructions decoded: push , pop , call
|
||||
, ret, etc. ESP instructions do not generate a Uop to increment or decrement
|
||||
ESP. Instead, they update an ESP_Offset register that keeps track of the
|
||||
ESP.
|
||||
Instead, they update an ESP_Offset register that keeps track of the
|
||||
delta to the current value of the ESP register.
|
||||
.It Li UOPS_DECODED.ESP_SYNC
|
||||
.Pq Event D1H , Umask 08H
|
||||
@ -1122,7 +1180,8 @@ value of the ESP register.
|
||||
.It Li RAT_STALLS.FLAGS
|
||||
.Pq Event D2H , Umask 01H
|
||||
Counts the number of cycles during which execution stalled due to several
|
||||
reasons, one of which is a partial flag register stall. A partial register
|
||||
reasons, one of which is a partial flag register stall.
|
||||
A partial register
|
||||
stall may occur when two conditions are met: 1) an instruction modifies
|
||||
some, but not all, of the flags in the flag register and 2) the next
|
||||
instruction, which depends on flags, depends on flags that were not modified
|
||||
@ -1135,28 +1194,34 @@ was partially written by previous instruction.
|
||||
.It Li RAT_STALLS.ROB_READ_PORT
|
||||
.Pq Event D2H , Umask 04H
|
||||
Counts the number of cycles when ROB read port stalls occurred, which did
|
||||
not allow new micro-ops to enter the out-of-order pipeline. Note that, at
|
||||
not allow new micro-ops to enter the out-of-order pipeline.
|
||||
Note that, at
|
||||
this stage in the pipeline, additional stalls may occur at the same cycle
|
||||
and prevent the stalled micro-ops from entering the pipe. In such a case,
|
||||
and prevent the stalled micro-ops from entering the pipe.
|
||||
In such a case,
|
||||
micro-ops retry entering the execution pipe in the next cycle and the
|
||||
ROB-read port stall is counted again.
|
||||
.It Li RAT_STALLS.SCOREBOARD
|
||||
.Pq Event D2H , Umask 08H
|
||||
Counts the cycles where we stall due to microarchitecturally required
|
||||
serialization. Microcode scoreboarding stalls.
|
||||
serialization.
|
||||
Microcode scoreboarding stalls.
|
||||
.It Li RAT_STALLS.ANY
|
||||
.Pq Event D2H , Umask 0FH
|
||||
Counts all Register Allocation Table stall cycles due to: Cycles when ROB
|
||||
read port stalls occurred, which did not allow new micro-ops to enter the
|
||||
execution pipe. Cycles when partial register stalls occurred Cycles when
|
||||
execution pipe.
|
||||
Cycles when partial register stalls occurred Cycles when
|
||||
flag stalls occurred Cycles floating-point unit (FPU) status word stalls
|
||||
occurred. To count each of these conditions separately use the events:
|
||||
occurred.
|
||||
To count each of these conditions separately use the events:
|
||||
RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and
|
||||
RAT_STALLS.FPSW.
|
||||
.It Li SEG_RENAME_STALLS
|
||||
.Pq Event D4H , Umask 01H
|
||||
Counts the number of stall cycles due to the lack of renaming resources for
|
||||
the ES, DS, FS, and GS segment registers. If a segment is renamed but not
|
||||
the ES, DS, FS, and GS segment registers.
|
||||
If a segment is renamed but not
|
||||
retired and a second update to the same segment occurs, a stall occurs in
|
||||
the front- end of the pipeline until the renamed segment retires.
|
||||
.It Li ES_REG_RENAMES
|
||||
@ -1176,16 +1241,18 @@ or return branch.
|
||||
.Pq Event E6H , Umask 01H
|
||||
Counts the number of times the front end is resteered, mainly when the
|
||||
Branch Prediction Unit cannot provide a correct prediction and this is
|
||||
corrected by the Branch Address Calculator at the front end. This can occur
|
||||
corrected by the Branch Address Calculator at the front end.
|
||||
This can occur
|
||||
if the code has many branches such that they cannot be consumed by the BPU.
|
||||
Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble
|
||||
in the instruction fetch pipeline. The effect on total execution time
|
||||
depends on the surrounding code.
|
||||
in the instruction fetch pipeline.
|
||||
The effect on total execution time depends on the surrounding code.
|
||||
.It Li BACLEAR.BAD_TARGET
|
||||
.Pq Event E6H , Umask 02H
|
||||
Counts number of Branch Address Calculator clears (BACLEAR) asserted due to
|
||||
conditional branch instructions in which there was a target hit but the
|
||||
direction was wrong. Each BACLEAR asserted by the BAC generates
|
||||
direction was wrong.
|
||||
Each BACLEAR asserted by the BAC generates
|
||||
approximately an 8 cycle bubble in the instruction fetch pipeline.
|
||||
.It Li BPU_CLEARS.EARLY
|
||||
.Pq Event E8H , Umask 01H
|
||||
@ -1195,7 +1262,8 @@ The BPU clear leads to 2 cycle bubble in the Front End.
|
||||
.It Li BPU_CLEARS.LATE
|
||||
.Pq Event E8H , Umask 02H
|
||||
Counts late Branch Prediction Unit clears due to Most Recently Used
|
||||
conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.
|
||||
conflicts.
|
||||
The PBU clear leads to a 3 cycle bubble in the Front End.
|
||||
.It Li THREAD_ACTIVE
|
||||
.Pq Event ECH , Umask 01H
|
||||
Counts cycles threads are active.
|
||||
@ -1258,12 +1326,13 @@ Counts number of Super Queue LRU hints sent to L3.
|
||||
Counts the number of SQ lock splits across a cache line.
|
||||
.It Li SQ_FULL_STALL_CYCLES
|
||||
.Pq Event F6H , Umask 01H
|
||||
Counts cycles the Super Queue is full. Neither of the threads on this core
|
||||
will be able to access the uncore.
|
||||
Counts cycles the Super Queue is full.
|
||||
Neither of the threads on this core will be able to access the uncore.
|
||||
.It Li FP_ASSIST.ALL
|
||||
.Pq Event F7H , Umask 01H
|
||||
Counts the number of floating point operations executed that required
|
||||
micro-code assist intervention. Assists are required in the following cases:
|
||||
micro-code assist intervention.
|
||||
Assists are required in the following cases:
|
||||
SSE instructions, (Denormal input when the DAZ flag is off or Underflow
|
||||
result when the FTZ flag is off): x87 instructions, (NaN or denormal are
|
||||
loaded to a register or used as input from memory, Division by 0 or
|
||||
|
||||
Loading…
Reference in New Issue
Block a user