hwpmc: add initial Intel Broadwell support.
The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month
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03a24b7026
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=281102
@ -574,7 +574,8 @@ struct iap_event_descr {
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#define IAP_F_HW (1 << 10) /* CPU: Haswell */
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#define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */
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#define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */
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#define IAP_F_FM (1 << 13) /* Fixed mask */
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#define IAP_F_BW (1 << 13) /* CPU: Broadwell */
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#define IAP_F_FM (1 << 14) /* Fixed mask */
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#define IAP_F_ALLCPUSCORE2 \
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(IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
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@ -2074,6 +2075,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
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if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
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return (EINVAL);
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break;
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE:
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@ -2106,6 +2108,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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cpuflag = IAP_F_CAS;
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break;
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case PMC_CPU_INTEL_BROADWELL:
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cpuflag = IAP_F_BW;
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break;
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case PMC_CPU_INTEL_CORE:
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cpuflag = IAP_F_CC;
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break;
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@ -179,6 +179,10 @@ pmc_intel_initialize(void)
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cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
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nclasses = 3;
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break;
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case 0x3D:
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cputype = PMC_CPU_INTEL_BROADWELL;
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nclasses = 3;
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break;
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case 0x3F: /* Per Intel document 325462-045US 09/2014. */
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case 0x46: /* Per Intel document 325462-045US 09/2014. */
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/* Should 46 be XEON. probably its own? */
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@ -227,6 +231,7 @@ pmc_intel_initialize(void)
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*/
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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@ -295,6 +300,7 @@ pmc_intel_initialize(void)
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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case PMC_CPU_INTEL_BROADWELL:
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error = pmc_uncore_initialize(pmc_mdep, ncpus);
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break;
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default:
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@ -319,6 +325,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
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#if defined(__i386__) || defined(__amd64__)
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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@ -360,6 +367,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
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*/
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#if defined(__i386__) || defined(__amd64__)
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switch (md->pmd_cputype) {
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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@ -1554,6 +1554,11 @@ __PMC_EV_ALIAS("BACLEARS.RETURN", IAP_EVENT_E6H_08H) \
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__PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \
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__PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H)
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/*
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* Aliases for Broadwell PMC events.
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*/
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#define __PMC_EV_ALIAS_BROADWELL() \
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__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()
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/*
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* Aliases for Core PMC events.
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@ -4228,6 +4233,11 @@ __PMC_EV(UCP, EVENT_86H_01H)
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#define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H
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#define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H
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/*
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* Aliases for Broadwell uncore PMC events
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*/
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#define __PMC_EV_ALIAS_BROADWELLUC()
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#define __PMC_EV_ALIAS_COREI7UC() \
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__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \
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__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \
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@ -96,6 +96,7 @@
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__PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
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__PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
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__PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
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__PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \
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__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
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__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
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__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
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