hwpmc: add initial Intel Broadwell support.

The full list of aliases and events will follow in a subsequent
commit.

MFC after:	1 month

sys/dev/hwpmc/hwpmc_core.c

@@ -574,7 +574,8 @@ struct iap_event_descr {
 #define	IAP_F_HW	(1 << 10)	/* CPU: Haswell */
 #define	IAP_F_CAS	(1 << 11)	/* CPU: Atom Silvermont */
 #define	IAP_F_HWX	(1 << 12)	/* CPU: Haswell Xeon */
-#define	IAP_F_FM	(1 << 13)	/* Fixed mask */
+#define	IAP_F_BW	(1 << 13)	/* CPU: Broadwell */
+#define	IAP_F_FM	(1 << 14)	/* Fixed mask */
 
 #define	IAP_F_ALLCPUSCORE2					\
     (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
@@ -2074,6 +2075,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 		if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
 			return (EINVAL);
 		break;
+	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 	case PMC_CPU_INTEL_IVYBRIDGE:
@@ -2106,6 +2108,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 	case PMC_CPU_INTEL_ATOM_SILVERMONT:
 		cpuflag = IAP_F_CAS;
 		break;
+	case PMC_CPU_INTEL_BROADWELL:
+		cpuflag = IAP_F_BW;
+		break;
 	case PMC_CPU_INTEL_CORE:
 		cpuflag = IAP_F_CC;
 		break;

sys/dev/hwpmc/hwpmc_intel.c

@@ -179,6 +179,10 @@ pmc_intel_initialize(void)
 			cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
 			nclasses = 3;
 			break;
+		case 0x3D:
+			cputype = PMC_CPU_INTEL_BROADWELL;
+			nclasses = 3;
+			break;
 		case 0x3F:	/* Per Intel document 325462-045US 09/2014. */
 		case 0x46:	/* Per Intel document 325462-045US 09/2014. */
 			        /* Should 46 be XEON. probably its own? */
@@ -227,6 +231,7 @@ pmc_intel_initialize(void)
 		 */
 	case PMC_CPU_INTEL_ATOM:
 	case PMC_CPU_INTEL_ATOM_SILVERMONT:
+	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_CORE:
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
@@ -295,6 +300,7 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_HASWELL:
 	case PMC_CPU_INTEL_SANDYBRIDGE:
 	case PMC_CPU_INTEL_WESTMERE:
+	case PMC_CPU_INTEL_BROADWELL:
 		error = pmc_uncore_initialize(pmc_mdep, ncpus);
 		break;
 	default:
@@ -319,6 +325,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
 #if	defined(__i386__) || defined(__amd64__)
 	case PMC_CPU_INTEL_ATOM:
 	case PMC_CPU_INTEL_ATOM_SILVERMONT:
+	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_CORE:
 	case PMC_CPU_INTEL_CORE2:
 	case PMC_CPU_INTEL_CORE2EXTREME:
@@ -360,6 +367,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
 	 */
 #if	defined(__i386__) || defined(__amd64__)
 	switch (md->pmd_cputype) {
+	case PMC_CPU_INTEL_BROADWELL:
 	case PMC_CPU_INTEL_COREI7:
 	case PMC_CPU_INTEL_HASWELL:
 	case PMC_CPU_INTEL_SANDYBRIDGE:

sys/dev/hwpmc/pmc_events.h

@@ -1554,6 +1554,11 @@ __PMC_EV_ALIAS("BACLEARS.RETURN",		    IAP_EVENT_E6H_08H)	\
 __PMC_EV_ALIAS("BACLEARS.COND",			    IAP_EVENT_E6H_10H)	\
 __PMC_EV_ALIAS("MS_DECODED.MS_ENTRY",		    IAP_EVENT_E7H_01H)
 
+/*
+ * Aliases for Broadwell PMC events.
+ */
+#define __PMC_EV_ALIAS_BROADWELL()					\
+__PMC_EV_ALIAS_INTEL_ARCHITECTURAL()
 
 /*
  * Aliases for Core PMC events.
@@ -4228,6 +4233,11 @@ __PMC_EV(UCP, EVENT_86H_01H)
 #define	PMC_EV_UCP_FIRST	PMC_EV_UCP_EVENT_00H_01H
 #define	PMC_EV_UCP_LAST		PMC_EV_UCP_EVENT_86H_01H
 
+/*
+ * Aliases for Broadwell uncore PMC events
+ */
+#define __PMC_EV_ALIAS_BROADWELLUC()
+
 #define	__PMC_EV_ALIAS_COREI7UC()					\
 __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H)	\
 __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H)	\

sys/sys/pmc.h

@@ -96,6 +96,7 @@
 	__PMC_CPU(INTEL_NEHALEM_EX, 0x93,   "Intel Nehalem Xeon 7500")	\
 	__PMC_CPU(INTEL_WESTMERE_EX, 0x94,   "Intel Westmere Xeon E7")	\
 	__PMC_CPU(INTEL_HASWELL_XEON, 0x95,   "Intel Haswell Xeon E5 v3") \
+	__PMC_CPU(INTEL_BROADWELL, 0x96,   "Intel Broadwell") \
 	__PMC_CPU(INTEL_XSCALE,	0x100,	"Intel XScale")		\
 	__PMC_CPU(MIPS_24K,     0x200,  "MIPS 24K")		\
 	__PMC_CPU(MIPS_OCTEON,  0x201,  "Cavium Octeon")	\