Add hypervisor interfaces for logical domain channels from the hypervisor API docs
remove bogus CDDL
This commit is contained in:
Kip Macy
parent
185877cc43
commit
bcbf936a19
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=164540
@ -1,40 +1,10 @@
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/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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* $FreeBSD$
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*/
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/*
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* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
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* Use is subject to license terms.
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*/
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#ifndef _MACHINE_HYPERVISOR_API_H
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#define _MACHINE_HYPERVISOR_API_H
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/*
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* sun4v Hypervisor API
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*
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* Reference: api.pdf Revision 0.12 dated May 12, 2004.
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* io-api.txt version 1.11 dated 10/19/2004
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*/
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#include <machine/hypervisorvar.h>
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#ifndef _ASM
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@ -79,6 +49,15 @@ typedef struct trap_trace_entry {
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uint64_t tte_f4; /* Entry specific. */
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} trap_trace_entry_t;
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typedef struct ldc_state_info {
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uint64_t lsi_head_offset;
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uint64_t lsi_tail_offset;
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uint64_t lse_channel_state;
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} ldc_state_info_t;
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#define LDC_CHANNEL_DOWN 0
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#define LDC_CHANNEL_UP 1
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extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int);
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extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int);
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extern uint64_t hv_set_ctx0(uint64_t, uint64_t);
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@ -136,7 +115,14 @@ extern uint64_t hvio_peek(devhandle_t dev_hdl, uint64_t r_addr, uint64_t size,
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uint32_t *err_flag, uint64_t *data);
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extern uint64_t hvio_poke(devhandle_t dev_hdl, uint64_t r_addr, uint64_t size,
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uint64_t data, uint64_t pcidev, uint32_t *err_flag);
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extern uint64_t hvio_ldc_tx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
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extern uint64_t hvio_ldc_tx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
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extern uint64_t hvio_ldc_tx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
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extern uint64_t hvio_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
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extern uint64_t hvio_ldc_rx_get_state(uint64_t ldc_id, ldc_state_info_t *info);
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extern uint64_t hvio_ldc_rx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
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extern uint64_t hvio_ldc_rx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
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extern uint64_t hvio_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
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extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t pci_device,
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pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data);
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extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t pci_device,
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@ -149,6 +149,16 @@
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#define HVIO_MSG_GETVALID 0xd2
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#define HVIO_MSG_SETVALID 0xd3
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#define HVIO_LDC_TX_QCONF 0xe0
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#define HVIO_LDC_TX_QINFO 0xe1
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#define HVIO_LDC_TX_GET_STATE 0xe2
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#define HVIO_LDC_TX_SET_QTAIL 0xe3
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#define HVIO_LDC_RX_QCONF 0xe4
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#define HVIO_LDC_RX_QINFO 0xe5
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#define HVIO_LDC_RX_GET_STATE 0xe6
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#define HVIO_LDC_RX_SET_QHEAD 0xe7
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#define HVIO_SIM_READ 0xf0
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#define HVIO_SIM_WRITE 0xf1
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@ -156,7 +156,160 @@ ENTRY(hv_cpu_mondo_send)
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retl
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membar #Sync
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END(hv_cpu_mondo_send)
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/*
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* configure ldc tx queue
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* arg0 ldc_id (%o0)
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* arg1 base_raddr (%o1)
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* arg2 nentries (%o2)
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*
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* ret0 status (%o0)
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*
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*/
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ENTRY(hvio_ldc_tx_qconf)
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mov HVIO_LDC_TX_QCONF, %o5
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ta FAST_TRAP
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retl
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nop
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END(hvio_ldc_tx_qconf)
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/*
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* return configuration info for ldc tx queue
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* arg0 ldc_id (%o0)
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*
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* ret0 status (%o0)
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* ret1 base_raddr (%o1)
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* ret2 nentries (%o2)
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*
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*/
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ENTRY(hvio_ldc_tx_qinfo)
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mov %o1, %o3
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mov %o2, %o4
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mov HVIO_LDC_TX_QINFO, %o5
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ta FAST_TRAP
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brnz %o0, 1f
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nop
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stx %o1, [%o3]
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stx %o2, [%o4]
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1: retl
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nop
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END(hvio_ldc_tx_qinfo)
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/*
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* get the state of the ldc tx queue
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* arg0 ldc_id (%o0)
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*
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* ret0 status (%o0)
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* ret1 head_offset (%o1)
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* ret2 tail_offset (%o2)
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* ret3 channel_state (%o3)
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*
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*/
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ENTRY(hvio_ldc_tx_get_state)
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mov %o1, %o4
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mov HVIO_LDC_TX_GET_STATE, %o5
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ta FAST_TRAP
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brnz %o0, 1f
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nop
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stx %o1, [%o4]
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stx %o2, [%o4 + 8]
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stx %o3, [%o4 + 16]
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1: retl
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nop
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END(hvio_ldc_tx_get_state)
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/*
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* update the tail pointer of the ldc tx queue
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* arg0 ldc_id (%o0)
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* arg1 tail_offset (%o1)
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*
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* ret0 status (%o0)
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*
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*/
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ENTRY(hvio_ldc_tx_set_qtail)
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mov HVIO_LDC_TX_SET_QTAIL, %o5
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ta FAST_TRAP
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retl
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nop
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END(hvio_ldc_tx_set_qtail)
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/*
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* configure ldc rx queue
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* arg0 ldc_id (%o0)
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* arg1 base_raddr (%o1)
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* arg2 nentries (%o2)
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*
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* ret0 status (%o0)
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*
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*/
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ENTRY(hvio_ldc_rx_qconf)
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mov HVIO_LDC_RX_QCONF, %o5
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ta FAST_TRAP
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retl
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nop
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END(hvio_ldc_rx_qconf)
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/*
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* return configuration info for ldc rx queue
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* arg0 ldc_id (%o0)
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*
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* ret0 status (%o0)
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* ret1 base_raddr (%o1)
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* ret2 nentries (%o2)
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*
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*/
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ENTRY(hvio_ldc_rx_qinfo)
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mov %o1, %o3
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mov %o2, %o4
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mov HVIO_LDC_RX_QINFO, %o5
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ta FAST_TRAP
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brnz %o0, 1f
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nop
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stx %o1, [%o3]
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stx %o2, [%o4]
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1: retl
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nop
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END(hvio_ldc_rx_qinfo)
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/*
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* get the state of the ldc rx queue
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* arg0 ldc_id (%o0)
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*
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* ret0 status (%o0)
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* ret1 head_offset (%o1)
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* ret2 tail_offset (%o2)
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* ret3 channel_state (%o3)
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*
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*/
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ENTRY(hvio_ldc_rx_get_state)
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mov %o1, %o4
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mov HVIO_LDC_RX_GET_STATE, %o5
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ta FAST_TRAP
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brnz %o0, 1f
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nop
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stx %o1, [%o4]
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stx %o2, [%o4 + 8]
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stx %o3, [%o4 + 16]
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1: retl
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nop
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END(hvio_ldc_rx_get_state)
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/*
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* update the head pointer of the ldc rx queue
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* arg0 ldc_id (%o0)
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* arg1 head_offset (%o1)
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*
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* ret0 status (%o0)
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*
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*/
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ENTRY(hvio_ldc_rx_set_qhead)
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mov HVIO_LDC_RX_SET_QHEAD, %o5
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ta FAST_TRAP
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retl
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nop
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END(hvio_ldc_rx_set_qhead)
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/*
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* arg0 - devhandle
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* arg1 - pci_device
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@ -854,8 +1007,8 @@ END(hv_dump_buf_update)
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* For memory scrub
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* int hv_mem_scrub(uint64_t real_addr, uint64_t length,
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* uint64_t *scrubbed_len);
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* Retun %o0 -- status
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* %o1 -- bytes scrubbed
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* Return %o0 -- status
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* %o1 -- bytes scrubbed
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*/
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ENTRY(hv_mem_scrub)
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mov %o2, %o4
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@ -869,8 +1022,8 @@ END(hv_mem_scrub)
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* Flush ecache
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* int hv_mem_sync(uint64_t real_addr, uint64_t length,
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* uint64_t *flushed_len);
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* Retun %o0 -- status
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* %o1 -- bytes flushed
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* Return %o0 -- status
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* %o1 -- bytes flushed
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*/
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ENTRY(hv_mem_sync)
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mov %o2, %o4
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