Merge AIM and Book-E PCPU fields
This is part of a long-term goal of merging Book-E and AIM into a single GENERIC kernel. As more work is done, the struct may be optimized further. Reviewed by: nwhitehorn
This commit is contained in:
parent
e35dc5149d
commit
bce6d88bc1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=329469
@ -442,7 +442,7 @@ cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
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{
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#ifdef __powerpc64__
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/* Copy the SLB contents from the current CPU */
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memcpy(pcpu->pc_slb, PCPU_GET(slb), sizeof(pcpu->pc_slb));
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memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));
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#endif
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}
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@ -601,7 +601,7 @@ moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
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uint64_t esid, slbe;
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uint64_t i;
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cache = PCPU_GET(slb);
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cache = PCPU_GET(aim.slb);
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esid = va >> ADDR_SR_SHFT;
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slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
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@ -840,8 +840,8 @@ moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
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*/
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#ifdef __powerpc64__
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for (i = 0; i < 64; i++) {
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pcpup->pc_slb[i].slbv = 0;
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pcpup->pc_slb[i].slbe = 0;
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pcpup->pc_aim.slb[i].slbv = 0;
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pcpup->pc_aim.slb[i].slbe = 0;
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}
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#else
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for (i = 0; i < 16; i++)
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@ -1017,9 +1017,10 @@ moea64_pmap_init_qpages(void)
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if (pc->pc_qmap_addr == 0)
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panic("pmap_init_qpages: unable to allocate KVA");
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PMAP_LOCK(kernel_pmap);
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pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
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pc->pc_aim.qmap_pvo =
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moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
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PMAP_UNLOCK(kernel_pmap);
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mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF);
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mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
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}
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}
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@ -1038,7 +1039,7 @@ moea64_activate(mmu_t mmu, struct thread *td)
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CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
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#ifdef __powerpc64__
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PCPU_SET(userslb, pm->pm_slb);
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PCPU_SET(aim.userslb, pm->pm_slb);
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__asm __volatile("slbmte %0, %1; isync" ::
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"r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
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#else
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@ -1057,7 +1058,7 @@ moea64_deactivate(mmu_t mmu, struct thread *td)
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pm = &td->td_proc->p_vmspace->vm_pmap;
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CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
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#ifdef __powerpc64__
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PCPU_SET(userslb, NULL);
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PCPU_SET(aim.userslb, NULL);
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#else
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PCPU_SET(curpmap, NULL);
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#endif
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@ -1153,12 +1154,12 @@ moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
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while (xfersize > 0) {
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a_pg_offset = a_offset & PAGE_MASK;
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cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
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a_cp = (char *)PHYS_TO_DMAP(
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a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
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VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
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a_pg_offset;
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b_pg_offset = b_offset & PAGE_MASK;
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cnt = min(cnt, PAGE_SIZE - b_pg_offset);
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b_cp = (char *)PHYS_TO_DMAP(
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b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
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VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
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b_pg_offset;
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bcopy(a_cp, b_cp, cnt);
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@ -1219,7 +1220,7 @@ moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
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panic("moea64_zero_page: size + off > PAGE_SIZE");
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if (hw_direct_map) {
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bzero((caddr_t)PHYS_TO_DMAP(pa) + off, size);
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bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
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} else {
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mtx_lock(&moea64_scratchpage_mtx);
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moea64_set_scratchpage_pa(mmu, 0, pa);
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@ -1270,10 +1271,10 @@ moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
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*/
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sched_pin();
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mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED);
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pvo = PCPU_GET(qmap_pvo);
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mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
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pvo = PCPU_GET(aim.qmap_pvo);
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mtx_lock(PCPU_PTR(qmap_lock));
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mtx_lock(PCPU_PTR(aim.qmap_lock));
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pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
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(uint64_t)pa;
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MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
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@ -1288,10 +1289,10 @@ moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
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if (hw_direct_map)
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return;
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mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED);
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mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
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KASSERT(PCPU_GET(qmap_addr) == addr,
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("moea64_quick_remove_page: invalid address"));
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mtx_unlock(PCPU_PTR(qmap_lock));
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mtx_unlock(PCPU_PTR(aim.qmap_lock));
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sched_unpin();
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}
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@ -1417,11 +1418,11 @@ moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
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* If PMAP is not bootstrapped, we are likely to be
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* in real mode.
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*/
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__syncicache((void *)pa, sz);
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__syncicache((void *)(uintptr_t)pa, sz);
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} else if (pmap == kernel_pmap) {
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__syncicache((void *)va, sz);
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} else if (hw_direct_map) {
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__syncicache((void *)PHYS_TO_DMAP(pa), sz);
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__syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
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} else {
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/* Use the scratch page to set up a temp mapping */
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@ -1802,8 +1803,8 @@ moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
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}
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if (error != 0 && error != ENOENT)
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panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
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pa, error);
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panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
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(uintmax_t)pa, error);
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}
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void
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@ -2767,7 +2768,7 @@ void
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moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
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{
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*va = (void *)pa;
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*va = (void *)(uintptr_t)pa;
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}
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extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
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@ -2799,7 +2800,7 @@ moea64_scan_init(mmu_t mmu)
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dump_map[0].pa_start;
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/* 2nd: msgbuf and tables (see pmap_bootstrap()). */
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dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
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dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
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dump_map[1].pa_size = round_page(msgbufp->msg_size);
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/* 3rd: kernel VM. */
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@ -365,7 +365,7 @@ moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
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{
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int i = 0;
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#ifdef __powerpc64__
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struct slb *slb = PCPU_GET(slb);
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struct slb *slb = PCPU_GET(aim.slb);
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register_t seg0;
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#endif
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@ -426,7 +426,7 @@ slb_insert_kernel(uint64_t slbe, uint64_t slbv)
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/* We don't want to be preempted while modifying the kernel map */
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critical_enter();
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slbcache = PCPU_GET(slb);
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slbcache = PCPU_GET(aim.slb);
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/* Check for an unused slot, abusing the user slot as a full flag */
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if (slbcache[USER_SLB_SLOT].slbe == 0) {
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@ -380,14 +380,14 @@ void
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cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
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{
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pcpu->pc_tid_next = TID_MIN;
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pcpu->pc_booke.tid_next = TID_MIN;
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#ifdef SMP
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uintptr_t *ptr;
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int words_per_gran = RES_GRANULE / sizeof(uintptr_t);
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ptr = &tlb0_miss_locks[cpuid * words_per_gran];
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pcpu->pc_booke_tlb_lock = ptr;
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pcpu->pc_booke.tlb_lock = ptr;
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*ptr = TLB_UNLOCKED;
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*(ptr + 1) = 0; /* recurse counter */
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#endif
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@ -501,12 +501,12 @@ tlb_miss_lock(void)
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if (pc != pcpup) {
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CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
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"tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
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"tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
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KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
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("tlb_miss_lock: tried to lock self"));
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tlb_lock(pc->pc_booke_tlb_lock);
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tlb_lock(pc->pc_booke.tlb_lock);
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CTR1(KTR_PMAP, "%s: locked", __func__);
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}
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@ -528,7 +528,7 @@ tlb_miss_unlock(void)
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CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
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__func__, pc->pc_cpuid);
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tlb_unlock(pc->pc_booke_tlb_lock);
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tlb_unlock(pc->pc_booke.tlb_lock);
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CTR1(KTR_PMAP, "%s: unlocked", __func__);
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}
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@ -3738,10 +3738,10 @@ tid_alloc(pmap_t pmap)
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thiscpu = PCPU_GET(cpuid);
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tid = PCPU_GET(tid_next);
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tid = PCPU_GET(booke.tid_next);
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if (tid > TID_MAX)
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tid = TID_MIN;
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PCPU_SET(tid_next, tid + 1);
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PCPU_SET(booke.tid_next, tid + 1);
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/* If we are stealing TID then clear the relevant pmap's field */
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if (tidbusy[thiscpu][tid] != NULL) {
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@ -3759,7 +3759,7 @@ tid_alloc(pmap_t pmap)
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__asm __volatile("msync; isync");
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CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
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PCPU_GET(tid_next));
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PCPU_GET(booke.tid_next));
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return (tid);
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}
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@ -52,23 +52,22 @@ struct pvo_entry;
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register_t pc_tempsave[CPUSAVE_LEN]; \
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register_t pc_disisave[CPUSAVE_LEN]; \
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register_t pc_dbsave[CPUSAVE_LEN]; \
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void *pc_restore;
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void *pc_restore; \
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vm_offset_t pc_qmap_addr;
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#define PCPU_MD_AIM32_FIELDS \
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vm_offset_t pc_qmap_addr; \
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struct pvo_entry *pc_qmap_pvo; \
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struct mtx pc_qmap_lock; \
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char __pad[128]
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struct pvo_entry *qmap_pvo; \
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struct mtx qmap_lock; \
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char __pad[128];
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#define PCPU_MD_AIM64_FIELDS \
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struct slb pc_slb[64]; \
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struct slb **pc_userslb; \
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register_t pc_slbsave[18]; \
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uint8_t pc_slbstack[1024]; \
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vm_offset_t pc_qmap_addr; \
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struct pvo_entry *pc_qmap_pvo; \
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struct mtx pc_qmap_lock; \
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char __pad[1345]
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struct slb slb[64]; \
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struct slb **userslb; \
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register_t slbsave[18]; \
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uint8_t slbstack[1024]; \
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struct pvo_entry *qmap_pvo; \
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struct mtx qmap_lock; \
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char __pad[1345];
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#ifdef __powerpc64__
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#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM64_FIELDS
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@ -87,14 +86,13 @@ struct pvo_entry;
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#define BOOKE_PCPU_PAD 429
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#endif
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#define PCPU_MD_BOOKE_FIELDS \
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register_t pc_booke_critsave[BOOKE_CRITSAVE_LEN]; \
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register_t pc_booke_mchksave[CPUSAVE_LEN]; \
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register_t pc_booke_tlbsave[BOOKE_TLBSAVE_LEN]; \
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register_t pc_booke_tlb_level; \
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vm_offset_t pc_qmap_addr; \
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uintptr_t *pc_booke_tlb_lock; \
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int pc_tid_next; \
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char __pad[BOOKE_PCPU_PAD]
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register_t critsave[BOOKE_CRITSAVE_LEN]; \
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register_t mchksave[CPUSAVE_LEN]; \
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register_t tlbsave[BOOKE_TLBSAVE_LEN]; \
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register_t tlb_level; \
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uintptr_t *tlb_lock; \
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int tid_next; \
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char __pad[BOOKE_PCPU_PAD];
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/* Definitions for register offsets within the exception tmp save areas */
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#define CPUSAVE_R27 0 /* where r27 gets saved */
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@ -129,24 +127,16 @@ struct pvo_entry;
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#define TLBSAVE_BOOKE_R30 14
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#define TLBSAVE_BOOKE_R31 15
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#ifdef AIM
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#define PCPU_MD_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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PCPU_MD_AIM_FIELDS
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#endif
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#if defined(BOOKE)
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#define PCPU_MD_FIELDS \
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PCPU_MD_COMMON_FIELDS \
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PCPU_MD_BOOKE_FIELDS
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#endif
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/*
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* Catch-all for ports (e.g. lsof, used by gtop)
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*/
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#ifndef PCPU_MD_FIELDS
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#define PCPU_MD_FIELDS \
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int pc_md_placeholder[32]
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#endif
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union { \
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struct { \
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PCPU_MD_AIM_FIELDS \
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} pc_aim; \
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struct { \
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PCPU_MD_BOOKE_FIELDS \
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} pc_booke; \
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}
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#ifdef _KERNEL
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@ -66,11 +66,11 @@ ASSYM(PC_DBSAVE, offsetof(struct pcpu, pc_dbsave));
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ASSYM(PC_RESTORE, offsetof(struct pcpu, pc_restore));
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#if defined(BOOKE)
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ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke_critsave));
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ASSYM(PC_BOOKE_MCHKSAVE, offsetof(struct pcpu, pc_booke_mchksave));
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ASSYM(PC_BOOKE_TLBSAVE, offsetof(struct pcpu, pc_booke_tlbsave));
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ASSYM(PC_BOOKE_TLB_LEVEL, offsetof(struct pcpu, pc_booke_tlb_level));
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ASSYM(PC_BOOKE_TLB_LOCK, offsetof(struct pcpu, pc_booke_tlb_lock));
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ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke.critsave));
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ASSYM(PC_BOOKE_MCHKSAVE, offsetof(struct pcpu, pc_booke.mchksave));
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ASSYM(PC_BOOKE_TLBSAVE, offsetof(struct pcpu, pc_booke.tlbsave));
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ASSYM(PC_BOOKE_TLB_LEVEL, offsetof(struct pcpu, pc_booke.tlb_level));
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ASSYM(PC_BOOKE_TLB_LOCK, offsetof(struct pcpu, pc_booke.tlb_lock));
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#endif
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ASSYM(CPUSAVE_R27, CPUSAVE_R27*sizeof(register_t));
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@ -109,10 +109,10 @@ ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock));
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#if defined(AIM)
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ASSYM(USER_ADDR, USER_ADDR);
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#ifdef __powerpc64__
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ASSYM(PC_KERNSLB, offsetof(struct pcpu, pc_slb));
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ASSYM(PC_USERSLB, offsetof(struct pcpu, pc_userslb));
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ASSYM(PC_SLBSAVE, offsetof(struct pcpu, pc_slbsave));
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ASSYM(PC_SLBSTACK, offsetof(struct pcpu, pc_slbstack));
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ASSYM(PC_KERNSLB, offsetof(struct pcpu, pc_aim.slb));
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ASSYM(PC_USERSLB, offsetof(struct pcpu, pc_aim.userslb));
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ASSYM(PC_SLBSAVE, offsetof(struct pcpu, pc_aim.slbsave));
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ASSYM(PC_SLBSTACK, offsetof(struct pcpu, pc_aim.slbstack));
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ASSYM(USER_SLB_SLOT, USER_SLB_SLOT);
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ASSYM(USER_SLB_SLBE, USER_SLB_SLBE);
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ASSYM(SEGMENT_MASK, SEGMENT_MASK);
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@ -652,7 +652,7 @@ handle_kernel_slb_spill(int type, register_t dar, register_t srr0)
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int i;
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addr = (type == EXC_ISE) ? srr0 : dar;
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slbcache = PCPU_GET(slb);
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slbcache = PCPU_GET(aim.slb);
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esid = (uintptr_t)addr >> ADDR_SR_SHFT;
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slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
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@ -121,7 +121,7 @@ mps3_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
|
||||
static void
|
||||
mps3_cpu_bootstrap(mmu_t mmup, int ap)
|
||||
{
|
||||
struct slb *slb = PCPU_GET(slb);
|
||||
struct slb *slb = PCPU_GET(aim.slb);
|
||||
register_t seg0;
|
||||
int i;
|
||||
|
||||
|
@ -221,7 +221,7 @@ mphyp_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
|
||||
static void
|
||||
mphyp_cpu_bootstrap(mmu_t mmup, int ap)
|
||||
{
|
||||
struct slb *slb = PCPU_GET(slb);
|
||||
struct slb *slb = PCPU_GET(aim.slb);
|
||||
register_t seg0;
|
||||
int i;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user