drm/i915: Further reduce the diff with Linux 3.8
There is no functional change. The goal is to ease the future update to Linux 3.8's i915 driver.
This commit is contained in:
Jean-Sébastien Pédron
parent
4ec1c9bfac
commit
bd2ebb612d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=293837
@ -156,7 +156,7 @@ i915_gem_wait_for_error(struct drm_device *dev)
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int ret;
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if (!atomic_load_acq_int(&dev_priv->mm.wedged))
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return (0);
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return 0;
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mtx_lock(&dev_priv->error_completion_lock);
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while (dev_priv->error_completion == 0) {
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@ -166,7 +166,7 @@ i915_gem_wait_for_error(struct drm_device *dev)
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ret = -ERESTARTSYS;
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if (ret != 0) {
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mtx_unlock(&dev_priv->error_completion_lock);
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return (ret);
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return ret;
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}
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}
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mtx_unlock(&dev_priv->error_completion_lock);
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@ -1861,26 +1861,30 @@ i915_gem_object_put_pages_range(struct drm_i915_gem_object *obj,
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static void
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i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
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{
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vm_page_t page;
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int page_count, i;
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int page_count = obj->base.size / PAGE_SIZE;
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int i;
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KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
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if (obj->tiling_mode != I915_TILING_NONE)
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i915_gem_object_save_bit_17_swizzle(obj);
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if (obj->madv == I915_MADV_DONTNEED)
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obj->dirty = 0;
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page_count = obj->base.size / PAGE_SIZE;
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VM_OBJECT_WLOCK(obj->base.vm_obj);
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#if GEM_PARANOID_CHECK_GTT
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i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
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#endif
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for (i = 0; i < page_count; i++) {
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page = obj->pages[i];
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vm_page_t page = obj->pages[i];
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if (obj->dirty)
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vm_page_dirty(page);
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if (obj->madv == I915_MADV_WILLNEED)
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vm_page_reference(page);
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vm_page_lock(page);
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vm_page_unwire(obj->pages[i], PQ_ACTIVE);
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vm_page_unlock(page);
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@ -1888,6 +1892,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
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}
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VM_OBJECT_WUNLOCK(obj->base.vm_obj);
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obj->dirty = 0;
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free(obj->pages, DRM_I915_GEM);
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obj->pages = NULL;
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}
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@ -411,8 +411,8 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
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reloc->offset += obj->gtt_offset;
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reloc_page = pmap_mapdev_attr(dev->agp->base + (reloc->offset &
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~PAGE_MASK), PAGE_SIZE, PAT_WRITE_COMBINING);
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reloc_entry = (uint32_t *)(reloc_page + (reloc->offset &
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PAGE_MASK));
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reloc_entry = (uint32_t *)
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(reloc_page + (reloc->offset & PAGE_MASK));
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*(volatile uint32_t *)reloc_entry = reloc->delta;
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pmap_unmapdev((vm_offset_t)reloc_page, PAGE_SIZE);
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}
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@ -502,7 +502,7 @@ i915_gem_execbuffer_relocate(struct drm_device *dev,
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struct list_head *objects)
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{
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struct drm_i915_gem_object *obj;
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int ret, pflags;
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int ret = 0, pflags;
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/* Try to move as many of the relocation targets off the active list
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* to avoid unnecessary fallbacks to the slow path, as we cannot wait
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@ -510,7 +510,6 @@ i915_gem_execbuffer_relocate(struct drm_device *dev,
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*/
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i915_gem_retire_requests(dev);
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ret = 0;
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/* This is the fast path and we cannot handle a pagefault whilst
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* holding the device lock lest the user pass in the relocations
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* contained within a mmaped bo. For in such a case we, the page
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@ -952,6 +951,7 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec, int count,
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*map = malloc(count * sizeof(*ma), DRM_I915_GEM, M_WAITOK | M_ZERO);
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*maplen = malloc(count * sizeof(*maplen), DRM_I915_GEM, M_WAITOK |
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M_ZERO);
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for (i = 0; i < count; i++) {
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/* First check for malicious input causing overflow */
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if (exec[i].relocation_count >
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@ -107,21 +107,22 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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I915_PPGTT_PT_ENTRIES);
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ppgtt->pd_offset = (first_pd_entry_in_global_pt) * sizeof(uint32_t);
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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return (0);
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return 0;
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}
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static void
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i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt, unsigned first_entry,
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unsigned num_entries, vm_page_t *pages, uint32_t pte_flags)
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static void i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned num_entries,
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vm_page_t *pages,
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uint32_t pte_flags)
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{
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uint32_t *pt_vaddr, pte;
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struct sf_buf *sf;
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unsigned act_pd, first_pte;
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unsigned last_pte, i;
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned j, last_pte;
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vm_paddr_t page_addr;
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act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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struct sf_buf *sf;
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while (num_entries) {
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last_pte = first_pte + num_entries;
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@ -132,10 +133,10 @@ i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt, unsigned first_entry,
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sf = sf_buf_alloc(ppgtt->pt_pages[act_pd], SFB_CPUPRIVATE);
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pt_vaddr = (uint32_t *)(uintptr_t)sf_buf_kva(sf);
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for (i = first_pte; i < last_pte; i++) {
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for (j = first_pte; j < last_pte; j++) {
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page_addr = VM_PAGE_TO_PHYS(*pages);
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pte = GEN6_PTE_ADDR_ENCODE(page_addr);
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pt_vaddr[i] = pte | pte_flags;
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pt_vaddr[j] = pte | pte_flags;
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pages++;
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}
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@ -194,18 +195,21 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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u_int first_pd_entry_in_global_pt;
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vm_paddr_t pt_addr;
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uint32_t pd_entry;
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int i;
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if (!dev_priv->mm.aliasing_ppgtt)
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return;
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first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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vm_paddr_t pt_addr;
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pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
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}
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intel_gtt_read_pte(first_pd_entry_in_global_pt);
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@ -217,7 +221,7 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
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gab_ctl = I915_READ(GAB_CTL);
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@ -336,9 +340,8 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
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return 0;
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}
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void
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i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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struct drm_device *dev;
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struct drm_i915_private *dev_priv;
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@ -375,15 +378,14 @@ void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
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}
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int i915_gem_init_global_gtt(struct drm_device *dev,
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unsigned long start,
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unsigned long mappable_end,
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unsigned long end)
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unsigned long start,
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unsigned long mappable_end,
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unsigned long end)
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{
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drm_i915_private_t *dev_priv;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long mappable;
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int error;
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dev_priv = dev->dev_private;
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mappable = min(end, mappable_end) - start;
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/* Substract the guard page ... */
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@ -453,15 +453,15 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
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* by the GPU.
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*/
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static void
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i915_gem_swizzle_page(vm_page_t m)
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i915_gem_swizzle_page(vm_page_t page)
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{
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char temp[64];
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char *vaddr;
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struct sf_buf *sf;
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char *vaddr;
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int i;
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/* XXXKIB sleep */
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sf = sf_buf_alloc(m, SFB_DEFAULT);
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sf = sf_buf_alloc(page, SFB_DEFAULT);
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vaddr = (char *)sf_buf_kva(sf);
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for (i = 0; i < PAGE_SIZE; i += 128) {
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@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/drm2/i915/i915_drm.h>
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#include <dev/drm2/i915/i915_drv.h>
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#include <dev/drm2/i915/intel_drv.h>
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#include <sys/sched.h>
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#include <sys/sf_buf.h>
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#include <sys/sleepqueue.h>
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@ -770,42 +771,47 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
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struct drm_i915_gem_object *src)
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{
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struct drm_i915_error_object *dst;
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struct sf_buf *sf;
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void *d, *s;
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int page, page_count;
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int i, count;
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u32 reloc_offset;
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if (src == NULL || src->pages == NULL)
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return NULL;
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page_count = src->base.size / PAGE_SIZE;
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count = src->base.size / PAGE_SIZE;
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dst = malloc(sizeof(*dst) + page_count * sizeof(u32 *), DRM_I915_GEM,
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M_NOWAIT);
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dst = malloc(sizeof(*dst) + count * sizeof(u32 *), DRM_I915_GEM, M_NOWAIT);
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if (dst == NULL)
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return (NULL);
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return NULL;
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reloc_offset = src->gtt_offset;
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for (page = 0; page < page_count; page++) {
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for (i = 0; i < count; i++) {
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void *d;
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d = malloc(PAGE_SIZE, DRM_I915_GEM, M_NOWAIT);
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if (d == NULL)
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goto unwind;
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if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
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src->has_global_gtt_mapping) {
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void *s;
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/* Simply ignore tiling or any overlapping fence.
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* It's part of the error state, and this hopefully
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* captures what the GPU read.
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*/
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s = pmap_mapdev_attr(src->base.dev->agp->base +
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reloc_offset, PAGE_SIZE, PAT_WRITE_COMBINING);
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reloc_offset,
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PAGE_SIZE, PAT_WRITE_COMBINING);
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memcpy(d, s, PAGE_SIZE);
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pmap_unmapdev((vm_offset_t)s, PAGE_SIZE);
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} else {
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drm_clflush_pages(&src->pages[page], 1);
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struct sf_buf *sf;
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void *s;
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drm_clflush_pages(&src->pages[i], 1);
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sched_pin();
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sf = sf_buf_alloc(src->pages[page], SFB_CPUPRIVATE |
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sf = sf_buf_alloc(src->pages[i], SFB_CPUPRIVATE |
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SFB_NOWAIT);
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if (sf != NULL) {
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s = (void *)(uintptr_t)sf_buf_kva(sf);
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@ -817,21 +823,21 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
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}
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sched_unpin();
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drm_clflush_pages(&src->pages[page], 1);
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drm_clflush_pages(&src->pages[i], 1);
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}
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dst->pages[page] = d;
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dst->pages[i] = d;
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reloc_offset += PAGE_SIZE;
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}
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dst->page_count = page_count;
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dst->page_count = count;
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dst->gtt_offset = src->gtt_offset;
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return dst;
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unwind:
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while (page--)
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free(dst->pages[page], DRM_I915_GEM);
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while (i--)
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free(dst->pages[i], DRM_I915_GEM);
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free(dst, DRM_I915_GEM);
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return NULL;
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}
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@ -2571,6 +2577,7 @@ void intel_irq_init(struct drm_device *dev)
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dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
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dev->driver->get_vblank_counter = gm45_get_vblank_counter;
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}
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
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else
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@ -598,8 +598,7 @@ void intel_crt_init(struct drm_device *dev)
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crt = malloc(sizeof(struct intel_crt), DRM_MEM_KMS, M_WAITOK | M_ZERO);
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intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS,
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M_WAITOK | M_ZERO);
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intel_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, M_WAITOK | M_ZERO);
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connector = &intel_connector->base;
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drm_connector_init(dev, &intel_connector->base,
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@ -1382,9 +1382,8 @@ intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
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static u32
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intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
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{
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u32 value;
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u32 value = 0;
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value = 0;
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mtx_lock(&dev_priv->dpio_lock);
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if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, 100)) {
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DRM_ERROR("timeout waiting for SBI to become ready\n");
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@ -1469,7 +1468,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
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/* PCH only available on ILK+ */
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KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
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if (pll == NULL)
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return;
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return;
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if (pll->refcount == 0) {
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DRM_DEBUG_KMS("pll->refcount == 0\n");
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@ -1495,7 +1494,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
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/* Make sure transcoder isn't still depending on us */
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assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
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reg = pll->pll_reg;
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val = I915_READ(reg);
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val &= ~DPLL_VCO_ENABLE;
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@ -1507,7 +1506,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
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}
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static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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enum pipe pipe)
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{
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int reg;
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u32 val, pipeconf_val;
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@ -1517,7 +1516,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
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KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
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/* Make sure PCH DPLL is enabled */
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assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
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assert_pch_pll_enabled(dev_priv,
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to_intel_crtc(crtc));
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/* FDI must be feeding us bits for PCH ports */
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assert_fdi_tx_enabled(dev_priv, pipe);
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@ -1527,9 +1527,11 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
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DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
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return;
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}
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reg = TRANSCONF(pipe);
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val = I915_READ(reg);
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pipeconf_val = I915_READ(PIPECONF(pipe));
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if (HAS_PCH_IBX(dev_priv->dev)) {
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/*
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* make the BPC in transcoder be consistent with
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@ -1886,6 +1888,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
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return -EINVAL;
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}
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if (INTEL_INFO(dev)->gen >= 4) {
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if (obj->tiling_mode != I915_TILING_NONE)
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dspcntr |= DISPPLANE_TILED;
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@ -2525,7 +2528,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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||||
POSTING_READ(reg);
|
||||
DELAY(150);
|
||||
|
||||
for (i = 0; i < 4; i++ ) {
|
||||
for (i = 0; i < 4; i++) {
|
||||
reg = FDI_TX_CTL(pipe);
|
||||
temp = I915_READ(reg);
|
||||
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
|
||||
@ -7132,7 +7135,7 @@ int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
|
||||
else
|
||||
gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
|
||||
pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct intel_display_error_state {
|
||||
|
||||
@ -1138,8 +1138,7 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
|
||||
return ret;
|
||||
}
|
||||
|
||||
params = malloc(sizeof(struct put_image_params), DRM_I915_GEM,
|
||||
M_WAITOK | M_ZERO);
|
||||
params = malloc(sizeof(struct put_image_params), DRM_I915_GEM, M_WAITOK | M_ZERO);
|
||||
|
||||
drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
|
||||
DRM_MODE_OBJECT_CRTC);
|
||||
@ -1403,8 +1402,7 @@ void intel_setup_overlay(struct drm_device *dev)
|
||||
if (!HAS_OVERLAY(dev))
|
||||
return;
|
||||
|
||||
overlay = malloc(sizeof(struct intel_overlay), DRM_I915_GEM,
|
||||
M_WAITOK | M_ZERO);
|
||||
overlay = malloc(sizeof(struct intel_overlay), DRM_I915_GEM, M_WAITOK | M_ZERO);
|
||||
DRM_LOCK(dev);
|
||||
if (dev_priv->overlay != NULL)
|
||||
goto out_free;
|
||||
@ -1523,16 +1521,15 @@ intel_overlay_capture_error_state(struct drm_device *dev)
|
||||
memcpy(&error->regs, regs, sizeof(struct overlay_registers));
|
||||
intel_overlay_unmap_regs(overlay, regs);
|
||||
|
||||
return (error);
|
||||
return error;
|
||||
|
||||
err:
|
||||
free(error, DRM_I915_GEM);
|
||||
return (NULL);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void
|
||||
intel_overlay_print_error_state(struct sbuf *m,
|
||||
struct intel_overlay_error_state *error)
|
||||
intel_overlay_print_error_state(struct sbuf *m, struct intel_overlay_error_state *error)
|
||||
{
|
||||
sbuf_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
|
||||
error->dovsta, error->isr);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user