expand CFI_ARMEDANDDANGEROUS to include writing the user segment
of the PR; this register is actually write-once so deserves the safety-belt as much as the PLR
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=188267
@ -438,9 +438,9 @@ cfi_write_block(struct cfi_softc *sc)
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* used for security. There are two 64-bit segments; one is programmed
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* at the factory with a unique 64-bit number which is immutable.
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* The other segment is left blank for User (OEM) programming.
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* Once the User/OEM segment is programmed it can be locked
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* to prevent future programming by writing bit 0 of the Protection
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* Lock Register (PLR). The PLR can written only once.
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* The User/OEM segment is One Time Programmable (OTP). It can also
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* be locked to prevent any firther writes by setting bit 0 of the
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* Protection Lock Register (PLR). The PLR can written only once.
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*/
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static uint16_t
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@ -496,17 +496,21 @@ cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
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/*
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* Write the User/OEM 64-bit segment of the PR.
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* XXX should allow writing individual words/bytes
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*/
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int
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cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
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{
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#ifdef CFI_ARMEDANDDANGEROUS
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register_t intr;
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int i, error;
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#endif
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if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
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return EOPNOTSUPP;
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KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
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#ifdef CFI_ARMEDANDDANGEROUS
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for (i = 7; i >= 4; i--, id >>= 16) {
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intr = intr_disable();
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cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
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@ -519,6 +523,11 @@ cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
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}
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return error;
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#else
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device_printf(sc->sc_dev, "%s: OEM PR not set, "
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"CFI_ARMEDANDDANGEROUS not configured\n", __func__);
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return ENXIO;
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#endif
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}
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/*
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