Follow up r223485, which made AIM use the ABI thread pointer instead of
PCPU fields for curthread, by doing the same to Book-E. This closes some potential races switching between CPUs. As a side effect, it turns out the AIM and Book-E swtch.S implementations were the same to within a few registers, so move that to powerpc/powerpc. MFC after: 3 months
This commit is contained in:
parent
6878c9db4a
commit
bdac436008
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=258002
@ -96,8 +96,6 @@ powerpc/aim/moea64_if.m optional aim
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powerpc/aim/moea64_native.c optional aim
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powerpc/aim/mp_cpudep.c optional aim smp
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powerpc/aim/slb.c optional aim powerpc64
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powerpc/aim/swtch32.S optional aim powerpc
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powerpc/aim/swtch64.S optional aim powerpc64
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powerpc/aim/trap.c optional aim
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powerpc/aim/uma_machdep.c optional aim
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powerpc/booke/copyinout.c optional booke
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@ -108,7 +106,6 @@ powerpc/booke/machdep_e500.c optional booke_e500
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powerpc/booke/mp_cpudep.c optional booke smp
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powerpc/booke/platform_bare.c optional booke
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powerpc/booke/pmap.c optional booke
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powerpc/booke/swtch.S optional booke
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powerpc/booke/trap.c optional booke
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powerpc/cpufreq/dfs.c optional cpufreq
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powerpc/cpufreq/pcr.c optional cpufreq aim
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@ -205,6 +202,8 @@ powerpc/powerpc/sc_machdep.c optional sc
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powerpc/powerpc/setjmp.S standard
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powerpc/powerpc/sigcode32.S optional powerpc | compat_freebsd32
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powerpc/powerpc/sigcode64.S optional powerpc64
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powerpc/powerpc/swtch32.S optional powerpc
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powerpc/powerpc/swtch64.S optional powerpc64
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powerpc/powerpc/stack_machdep.c optional ddb | stack
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powerpc/powerpc/suswintr.c standard
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powerpc/powerpc/syncicache.c standard
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@ -738,8 +738,7 @@ ENTRY(icache_enable)
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setfault:
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mflr %r0
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mfsprg0 %r4
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lwz %r4, PC_CURTHREAD(%r4)
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lwz %r4, TD_PCB(%r4)
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lwz %r4, TD_PCB(%r2)
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stw %r3, PCB_ONFAULT(%r4)
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mfcr %r10
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mfctr %r11
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@ -409,6 +409,11 @@ booke_init(uint32_t arg1, uint32_t arg2)
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pc = &__pcpu[0];
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pcpu_init(pc, 0, sizeof(struct pcpu));
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pc->pc_curthread = &thread0;
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#ifdef __powerpc64__
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__asm __volatile("mr 13,%0" :: "r"(pc->pc_curthread));
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#else
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__asm __volatile("mr 2,%0" :: "r"(pc->pc_curthread));
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#endif
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__asm __volatile("mtsprg 0, %0" :: "r"(pc));
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/* Initialize system mutexes. */
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@ -71,6 +71,11 @@ cpudep_ap_bootstrap()
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/* Assign pcpu fields, return ptr to this AP's idle thread kstack */
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pcpup->pc_curthread = pcpup->pc_idlethread;
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#ifdef __powerpc64__
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__asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
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#else
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__asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
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#endif
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pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
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sp = pcpup->pc_curpcb->pcb_sp;
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@ -100,8 +100,6 @@ __FBSDID("$FreeBSD$");
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#define TODO panic("%s: not implemented", __func__);
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extern struct mtx sched_lock;
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extern int dumpsys_minidump;
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extern unsigned char _etext[];
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@ -1906,7 +1904,7 @@ mmu_booke_activate(mmu_t mmu, struct thread *td)
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KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
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mtx_lock_spin(&sched_lock);
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sched_pin();
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cpuid = PCPU_GET(cpuid);
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CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
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@ -1919,7 +1917,7 @@ mmu_booke_activate(mmu_t mmu, struct thread *td)
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mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
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__asm __volatile("isync");
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mtx_unlock_spin(&sched_lock);
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sched_unpin();
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CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
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pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
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@ -1,159 +0,0 @@
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/*-
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* Copyright (C) 2001 Benno Rice
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: $NetBSD: locore.S,v 1.24 2000/05/31 05:09:17 thorpej Exp $
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* from: $FreeBSD$
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*
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* $FreeBSD$
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.s"
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#include <sys/syscall.h>
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#include <machine/trap.h>
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#include <machine/param.h>
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#include <machine/asm.h>
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#include <machine/spr.h>
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/*
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* void cpu_throw(struct thread *old, struct thread *new)
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*/
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ENTRY(cpu_throw)
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mr %r15, %r4
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b cpu_switchin
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/*
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* void cpu_switch(struct thread *old, struct thread *new, struct mutex *mtx);)
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*
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* Switch to a new thread saving the current state in the old thread.
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*/
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ENTRY(cpu_switch)
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stw %r5, TD_LOCK(%r3)
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lwz %r5, TD_PCB(%r3) /* Get the old thread's PCB ptr */
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mr %r12, %r2
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stmw %r12, PCB_CONTEXT(%r5) /* Save the non-volatile GP regs.
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These can now be used for scratch */
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mfcr %r16 /* Save the condition register */
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stw %r16, PCB_CR(%r5)
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mflr %r16 /* Save the link register */
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stw %r16, PCB_LR(%r5)
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mfctr %r16
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stw %r16, PCB_BOOKE_CTR(%r5)
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mfxer %r16
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stw %r16, PCB_BOOKE_XER(%r5)
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mfspr %r16, SPR_DBCR0
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stw %r16, PCB_BOOKE_DBCR0(%r5)
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stw %r1, PCB_SP(%r5) /* Save the stack pointer */
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mr %r14, %r3 /* Copy the old thread ptr... */
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mr %r15, %r4 /* and the new thread ptr in scratch */
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bl pmap_deactivate /* Deactivate the current pmap */
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cpu_switchin:
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mr %r3, %r15 /* Get new thread ptr */
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bl pmap_activate /* Activate the new address space */
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mfsprg %r7, 0 /* Get the pcpu pointer */
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stw %r15, PC_CURTHREAD(%r7) /* Store new current thread */
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lwz %r17, TD_PCB(%r15) /* Store new current PCB */
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stw %r17, PC_CURPCB(%r7)
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mr %r3, %r17 /* Recover PCB ptr */
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lmw %r12, PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */
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mr %r2, %r12
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lwz %r5, PCB_CR(%r3) /* Load the condition register */
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mtcr %r5
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lwz %r5, PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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lwz %r5, PCB_BOOKE_CTR(%r3)
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mtctr %r5
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lwz %r5, PCB_BOOKE_XER(%r3)
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mtxer %r5
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lwz %r5, PCB_BOOKE_DBCR0(%r3)
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mtspr SPR_DBCR0, %r5
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lwz %r1, PCB_SP(%r3) /* Load the stack pointer */
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blr
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/*
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* savectx(pcb)
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* Update pcb, saving current processor state
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*/
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ENTRY(savectx)
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mr %r12, %r2
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stmw %r12, PCB_CONTEXT(%r3) /* Save the non-volatile GP regs */
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mfcr %r4 /* Save the condition register */
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stw %r4, PCB_CONTEXT(%r3)
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blr
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/*
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* fork_trampoline()
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* Set up the return from cpu_fork()
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*/
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ENTRY(fork_trampoline)
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lwz %r3, CF_FUNC(%r1)
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lwz %r4, CF_ARG0(%r1)
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lwz %r5, CF_ARG1(%r1)
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bl fork_exit
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addi %r1, %r1, CF_SIZE-FSP /* Allow 8 bytes in front of
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trapframe to simulate FRAME_SETUP
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does when allocating space for
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a frame pointer/saved LR */
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b trapexit
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@ -219,7 +219,8 @@
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lwz %r30, (savearea+CPUSAVE_SRR0)(%r2); \
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lwz %r31, (savearea+CPUSAVE_SRR1)(%r2); \
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stw %r30, FRAME_SRR0+8(%r1); \
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stw %r31, FRAME_SRR1+8(%r1)
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stw %r31, FRAME_SRR1+8(%r1); \
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lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */
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/*
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*
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@ -734,7 +735,8 @@ interrupt_vector_top:
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INTERRUPT(int_debug)
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STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
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FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG)
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lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r2);
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GET_CPUINFO(%r3)
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lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r3)
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lis %r4, interrupt_vector_base@ha
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addi %r4, %r4, interrupt_vector_base@l
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cmplw cr0, %r3, %r4
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@ -748,9 +750,10 @@ INTERRUPT(int_debug)
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rlwinm %r3, %r3, 0, 23, 21
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stw %r3, FRAME_SRR1+8(%r1);
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/* Restore srr0 and srr1 as they could have been clobbered. */
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lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r2);
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GET_CPUINFO(%r4)
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lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r4);
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mtspr SPR_SRR0, %r3
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lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r2);
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lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r4);
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mtspr SPR_SRR1, %r4
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b 9f
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1:
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@ -135,7 +135,6 @@ struct pmap;
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#define pcpup ((struct pcpu *) powerpc_get_pcpup())
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#ifdef AIM /* Book-E not yet adapted */
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static __inline __pure2 struct thread *
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__curthread(void)
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{
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@ -148,7 +147,6 @@ __curthread(void)
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return (td);
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}
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#define curthread (__curthread())
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#endif
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#define PCPU_GET(member) (pcpup->pc_ ## member)
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@ -64,6 +64,7 @@
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#include <machine/trap.h>
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#include <machine/param.h>
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#include <machine/asm.h>
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#include <machine/spr.h>
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/*
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* void cpu_throw(struct thread *old, struct thread *new)
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@ -88,6 +89,14 @@ ENTRY(cpu_switch)
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stw %r16,PCB_CR(%r6)
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mflr %r16 /* Save the link register */
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stw %r16,PCB_LR(%r6)
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#ifdef BOOKE
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mfctr %r16
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stw %r16,PCB_BOOKE_CTR(%r6)
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mfxer %r16
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stw %r16,PCB_BOOKE_XER(%r6)
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mfspr %r16,SPR_DBCR0
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stw %r16,PCB_BOOKE_DBCR0(%r6)
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#endif
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stw %r1,PCB_SP(%r6) /* Save the stack pointer */
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mr %r14,%r3 /* Copy the old thread ptr... */
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@ -95,6 +104,7 @@ ENTRY(cpu_switch)
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mr %r16,%r5 /* and the new lock */
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mr %r17,%r6 /* and the PCB */
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#ifdef AIM
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lwz %r7,PCB_FLAGS(%r17)
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/* Save FPU context if needed */
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andi. %r7, %r7, PCB_FPU
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@ -110,6 +120,7 @@ ENTRY(cpu_switch)
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bl save_vec
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.L2:
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#endif
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mr %r3,%r14 /* restore old thread ptr */
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bl pmap_deactivate /* Deactivate the current pmap */
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@ -136,6 +147,7 @@ blocked_loop:
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mr %r3,%r2 /* Get new thread ptr */
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bl pmap_activate /* Activate the new address space */
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#ifdef AIM
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lwz %r6, PCB_FLAGS(%r17)
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/* Restore FPU context if needed */
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andi. %r6, %r6, PCB_FPU
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@ -151,18 +163,29 @@ blocked_loop:
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mr %r3,%r2 /* Pass curthread to enable_vec */
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bl enable_vec
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/* thread to restore is in r3 */
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.L4:
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#endif
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/* thread to restore is in r3 */
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mr %r3,%r17 /* Recover PCB ptr */
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lmw %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */
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lwz %r5,PCB_CR(%r3) /* Load the condition register */
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mtcr %r5
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lwz %r5,PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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#ifdef AIM
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lwz %r5,PCB_AIM_USR_VSID(%r3) /* Load the USER_SR segment reg */
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isync
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mtsr USER_SR,%r5
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isync
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#endif
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#ifdef BOOKE
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lwz %r5,PCB_BOOKE_CTR(%r3)
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mtctr %r5
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lwz %r5,PCB_BOOKE_XER(%r3)
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mtctr %r5
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lwz %r5,PCB_BOOKE_DBCR0(%r3)
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mtspr SPR_DBCR0,%r5
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#endif
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lwz %r1,PCB_SP(%r3) /* Load the stack pointer */
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/*
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* Perform a dummy stwcx. to clear any reservations we may have
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