Vendor import of clang release_60 branch r323948:
https://llvm.org/svn/llvm-project/cfe/branches/release_60@323948
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/clang/dist-release_60/; revision=328739 svn path=/vendor/clang/clang-release_60-r323948/; revision=328740; tag=vendor/clang/clang-release_60-r323948
@ -213,7 +213,49 @@ Objective-C Language Changes in Clang
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OpenCL C Language Changes in Clang
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----------------------------------
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...
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- Added subgroup builtins to enqueue kernel support.
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- Added CL2.0 atomics as Clang builtins that now accept
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an additional memory scope parameter propagated to atomic IR instructions
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(this is to align with the corresponding change in LLVM IR) (see `spec s6.13.11.4
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<https://www.khronos.org/registry/OpenCL/specs/opencl-2.0-openclc.pdf#107>`_).
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- Miscellaneous fixes in the CL header.
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- Allow per target selection of address space during CodeGen of certain OpenCL types.
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Default target implementation is provided mimicking old behavior.
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- Macro ``__IMAGE_SUPPORT__`` is now automatically added (as per `spec s6.10
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<https://www.khronos.org/registry/OpenCL/specs/opencl-2.0-openclc.pdf#55>`_).
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- Added ``cl_intel_subgroups`` and ``cl_intel_subgroups_short`` extensions.
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- All function calls are marked by `the convergent attribute
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<https://clang.llvm.org/docs/AttributeReference.html#convergent-clang-convergent>`_
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to prevent optimizations that break SPMD program semantics. This will be removed
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by LLVM passes if it can be proved that the function does not use convergent
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operations.
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- Create a kernel wrapper for enqueued blocks, which simplifies enqueue support by
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providing common functionality.
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- Added private address space explicitly in AST and refactored address space support
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with several simplifications and bug fixes (`PR33419 <https://llvm.org/pr33419>`_
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and `PR33420 <https://llvm.org/pr33420>`_).
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- OpenCL now allows functions with empty parameters to be treated as if they had a
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void parameter list (inspired from C++ support). OpenCL C spec update to follow.
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- General miscellaneous refactoring and cleanup of blocks support for OpenCL to
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remove unused parts inherited from Objective C implementation.
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- Miscellaneous improvements in vector diagnostics.
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- Added half float load and store builtins without enabling half as a legal type
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(``__builtin_store_half for double``, ``__builtin_store_halff`` for double,
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``__builtin_load_half for double``, ``__builtin_load_halff`` for float).
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OpenMP Support in Clang
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----------------------------------
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@ -354,4 +354,12 @@ def warn_drv_fine_grained_bitfield_accesses_ignored : Warning<
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def note_drv_verify_prefix_spelling : Note<
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"-verify prefixes must start with a letter and contain only alphanumeric"
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" characters, hyphens, and underscores">;
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def warn_drv_experimental_isel_incomplete : Warning<
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"-fexperimental-isel support for the '%0' architecture is incomplete">,
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InGroup<ExperimentalISel>;
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def warn_drv_experimental_isel_incomplete_opt : Warning<
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"-fexperimental-isel support is incomplete for this architecture at the current optimization level">,
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InGroup<ExperimentalISel>;
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}
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@ -985,3 +985,6 @@ def UnknownArgument : DiagGroup<"unknown-argument">;
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// A warning group for warnings about code that clang accepts when
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// compiling OpenCL C/C++ but which is not compatible with the SPIR spec.
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def SpirCompat : DiagGroup<"spir-compat">;
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// Warning for the experimental-isel options.
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def ExperimentalISel : DiagGroup<"experimental-isel">;
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@ -1031,6 +1031,8 @@ def finline_functions : Flag<["-"], "finline-functions">, Group<f_clang_Group>,
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def finline_hint_functions: Flag<["-"], "finline-hint-functions">, Group<f_clang_Group>, Flags<[CC1Option]>,
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HelpText<"Inline functions which are (explicitly or implicitly) marked inline">;
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def finline : Flag<["-"], "finline">, Group<clang_ignored_f_Group>;
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def fexperimental_isel : Flag<["-"], "fexperimental-isel">, Group<f_clang_Group>,
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HelpText<"Enables the experimental global instruction selector">;
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def fexperimental_new_pass_manager : Flag<["-"], "fexperimental-new-pass-manager">,
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Group<f_clang_Group>, Flags<[CC1Option]>,
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HelpText<"Enables an experimental new pass manager in LLVM.">;
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@ -1237,6 +1239,8 @@ def fno_exceptions : Flag<["-"], "fno-exceptions">, Group<f_Group>;
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def fno_gnu_keywords : Flag<["-"], "fno-gnu-keywords">, Group<f_Group>, Flags<[CC1Option]>;
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def fno_inline_functions : Flag<["-"], "fno-inline-functions">, Group<f_clang_Group>, Flags<[CC1Option]>;
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def fno_inline : Flag<["-"], "fno-inline">, Group<f_clang_Group>, Flags<[CC1Option]>;
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def fno_experimental_isel : Flag<["-"], "fno-experimental-isel">, Group<f_clang_Group>,
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HelpText<"Disables the experimental global instruction selector">;
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def fno_experimental_new_pass_manager : Flag<["-"], "fno-experimental-new-pass-manager">,
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Group<f_clang_Group>, Flags<[CC1Option]>,
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HelpText<"Disables an experimental new pass manager in LLVM.">;
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@ -409,7 +409,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
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if (Enabled) {
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switch (Level) {
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case AVX512F:
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Features["avx512f"] = true;
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Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
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LLVM_FALLTHROUGH;
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case AVX2:
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Features["avx2"] = true;
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@ -623,6 +623,8 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
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} else if (Name == "fma") {
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if (Enabled)
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setSSELevel(Features, AVX, Enabled);
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else
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setSSELevel(Features, AVX512F, Enabled);
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} else if (Name == "fma4") {
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setXOPLevel(Features, FMA4, Enabled);
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} else if (Name == "xop") {
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@ -632,6 +634,8 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
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} else if (Name == "f16c") {
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if (Enabled)
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setSSELevel(Features, AVX, Enabled);
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else
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setSSELevel(Features, AVX512F, Enabled);
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} else if (Name == "sha") {
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if (Enabled)
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setSSELevel(Features, SSE2, Enabled);
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@ -4639,6 +4639,37 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
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CmdArgs.push_back("-fwhole-program-vtables");
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}
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if (Arg *A = Args.getLastArg(options::OPT_fexperimental_isel,
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options::OPT_fno_experimental_isel)) {
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CmdArgs.push_back("-mllvm");
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if (A->getOption().matches(options::OPT_fexperimental_isel)) {
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CmdArgs.push_back("-global-isel=1");
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// GISel is on by default on AArch64 -O0, so don't bother adding
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// the fallback remarks for it. Other combinations will add a warning of
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// some kind.
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bool IsArchSupported = Triple.getArch() == llvm::Triple::aarch64;
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bool IsOptLevelSupported = false;
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Arg *A = Args.getLastArg(options::OPT_O_Group);
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if (Triple.getArch() == llvm::Triple::aarch64) {
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if (!A || A->getOption().matches(options::OPT_O0))
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IsOptLevelSupported = true;
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}
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if (!IsArchSupported || !IsOptLevelSupported) {
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CmdArgs.push_back("-mllvm");
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CmdArgs.push_back("-global-isel-abort=2");
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if (!IsArchSupported)
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D.Diag(diag::warn_drv_experimental_isel_incomplete) << Triple.getArchName();
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else
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D.Diag(diag::warn_drv_experimental_isel_incomplete_opt);
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}
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} else {
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CmdArgs.push_back("-global-isel=0");
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}
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}
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// Finally add the compile command to the compilation.
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if (Args.hasArg(options::OPT__SLASH_fallback) &&
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Output.getType() == types::TY_Object &&
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@ -46,7 +46,7 @@ static void handleHVXWarnings(const Driver &D, const ArgList &Args) {
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// Handle the unsupported values passed to mhvx-length.
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if (Arg *A = Args.getLastArg(options::OPT_mhexagon_hvx_length_EQ)) {
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StringRef Val = A->getValue();
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if (Val != "64B" && Val != "128B")
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if (!Val.equals_lower("64b") && !Val.equals_lower("128b"))
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D.Diag(diag::err_drv_unsupported_option_argument)
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<< A->getOption().getName() << Val;
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}
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24
test/Driver/global-isel.c
Normal file
24
test/Driver/global-isel.c
Normal file
@ -0,0 +1,24 @@
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// REQUIRES: x86-registered-target,aarch64-registered-target
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// RUN: %clang -fexperimental-isel -S -### %s 2>&1 | FileCheck --check-prefix=ENABLED %s
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// RUN: %clang -fno-experimental-isel -S -### %s 2>&1 | FileCheck --check-prefix=DISABLED %s
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// RUN: %clang -target aarch64 -fexperimental-isel -S %s -### 2>&1 | FileCheck --check-prefix=ARM64-DEFAULT %s
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// RUN: %clang -target aarch64 -fexperimental-isel -S -O0 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O0 %s
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// RUN: %clang -target aarch64 -fexperimental-isel -S -O2 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O2 %s
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// RUN: %clang -target aarch64 -fexperimental-isel -Wno-experimental-isel -S -O2 %s -### 2>&1 | FileCheck --check-prefix=ARM64-O2-NOWARN %s
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// RUN: %clang -target x86_64 -fexperimental-isel -S %s -### 2>&1 | FileCheck --check-prefix=X86_64 %s
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// ENABLED: "-mllvm" "-global-isel=1"
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// DISABLED: "-mllvm" "-global-isel=0"
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// ARM64-DEFAULT-NOT: warning: -fexperimental-sel
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// ARM64-DEFAULT-NOT: "-global-isel-abort=2"
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// ARM64-O0-NOT: warning: -fexperimental-sel
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// ARM64-O2: warning: -fexperimental-isel support is incomplete for this architecture at the current optimization level
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// ARM64-O2: "-mllvm" "-global-isel-abort=2"
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// ARM64-O2-NOWARN-NOT: warning: -fexperimental-isel
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// X86_64: -fexperimental-isel support for the 'x86_64' architecture is incomplete
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// X86_64: "-mllvm" "-global-isel-abort=2"
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@ -21,6 +21,9 @@
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \
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// RUN: -mhvx-length=128B 2>&1 | FileCheck -check-prefix=CHECKHVX2 %s
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \
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// RUN: -mhvx-length=128b 2>&1 | FileCheck -check-prefix=CHECKHVX2 %s
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// CHECKHVX2-NOT: "-target-feature" "+hvx-length64b"
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// CHECKHVX2: "-target-feature" "+hvx-length128b"
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@ -79,8 +82,10 @@
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// The default mode on v60,v62 is 64B.
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \
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// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx -mhvx-length=64B\
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// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \
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// RUN: -mhvx-length=64b 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \
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// RUN: -mhvx-length=64B 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-64B %s
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// CHECK-HVXLENGTH-64B: "-target-feature" "+hvx{{.*}}" "-target-feature" "+hvx-length64b"
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// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx -mhvx-length=128B\
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// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVXLENGTH-128B %s
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