tegra124: Implement new get_gate method for tegra124 clocks.
MFC after: 1 week
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0d5fac2872
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@ -697,6 +697,7 @@ periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
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/* -------------------------------------------------------------------------- */
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static int pgate_init(struct clknode *clk, device_t dev);
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static int pgate_set_gate(struct clknode *clk, bool enable);
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static int pgate_get_gate(struct clknode *clk, bool *enableD);
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struct pgate_sc {
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device_t clkdev;
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@ -710,6 +711,7 @@ static clknode_method_t pgate_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, pgate_init),
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CLKNODEMETHOD(clknode_set_gate, pgate_set_gate),
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CLKNODEMETHOD(clknode_get_gate, pgate_get_gate),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
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@ -771,6 +773,23 @@ pgate_set_gate(struct clknode *clk, bool enable)
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return(0);
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}
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static int
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pgate_get_gate(struct clknode *clk, bool *enabled)
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{
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struct pgate_sc *sc;
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uint32_t reg, mask, base_reg;
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sc = clknode_get_softc(clk);
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mask = 1 << (sc->idx % 32);
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base_reg = get_enable_reg(sc->idx);
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DEVICE_LOCK(sc);
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RD4(sc, base_reg, ®);
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DEVICE_UNLOCK(sc);
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*enabled = reg & mask ? true: false;
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return(0);
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}
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int
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tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)
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{
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@ -382,6 +382,7 @@ static struct clk_pll_def pll_clks[] = {
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static int tegra124_pll_init(struct clknode *clk, device_t dev);
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static int tegra124_pll_set_gate(struct clknode *clk, bool enable);
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static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled);
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static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq);
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static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin,
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uint64_t *fout, int flags, int *stop);
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@ -403,6 +404,7 @@ static clknode_method_t tegra124_pll_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, tegra124_pll_init),
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CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate),
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CLKNODEMETHOD(clknode_get_gate, tegra124_pll_get_gate),
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CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc),
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CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq),
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CLKNODEMETHOD_END
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@ -688,6 +690,19 @@ tegra124_pll_set_gate(struct clknode *clknode, bool enable)
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return (rv);
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}
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static int
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tegra124_pll_get_gate(struct clknode *clknode, bool *enabled)
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{
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uint32_t reg;
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struct pll_sc *sc;
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sc = clknode_get_softc(clknode);
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RD4(sc, sc->base_reg, ®);
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*enabled = reg & PLL_BASE_ENABLE ? true: false;
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WR4(sc, sc->base_reg, reg);
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return (0);
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}
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static int
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pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
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uint32_t m, uint32_t n, uint32_t p)
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